CN111509037A - Silicon carbide MOS device with groove type JFET and preparation process thereof - Google Patents
Silicon carbide MOS device with groove type JFET and preparation process thereof Download PDFInfo
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- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 19
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000000463 material Substances 0.000 claims abstract description 14
- 210000000746 body region Anatomy 0.000 claims abstract description 10
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000002955 isolation Methods 0.000 claims abstract description 8
- 238000004519 manufacturing process Methods 0.000 claims description 18
- 238000001259 photo etching Methods 0.000 claims description 18
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 238000005530 etching Methods 0.000 claims description 15
- 238000000137 annealing Methods 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 11
- 238000002513 implantation Methods 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 238000009616 inductively coupled plasma Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 238000001704 evaporation Methods 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 5
- 239000007943 implant Substances 0.000 claims description 5
- 230000004913 activation Effects 0.000 claims description 4
- 239000005380 borophosphosilicate glass Substances 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 239000011261 inert gas Substances 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 4
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 239000004642 Polyimide Substances 0.000 claims description 3
- 238000002161 passivation Methods 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 238000004528 spin coating Methods 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 description 12
- 238000010586 diagram Methods 0.000 description 8
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
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- 239000000243 solution Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
Abstract
The invention discloses a silicon carbide MOS device with a groove type JFET and a preparation process thereof, wherein the silicon carbide MOS device with the groove type JFET comprises the following components: the doping type of the silicon carbide substrate material is a first conduction type; a first conductive type semiconductor epitaxial layer and a drain electrode are respectively arranged on the front surface and the back surface of the silicon carbide substrate; the active region of the first conductive type semiconductor epitaxial layer is provided with a JFET region, the JFET region is provided with a first surface, a second surface and a third surface, and the first surface and the second surface are respectively provided with a first conductive type source region and a second conductive type base region from outside to inside; a source electrode is arranged above the first surface, a gate dielectric and a gate electrode are arranged above the third surface, a second conductive type injection body region is arranged between the second conductive type base region and the source electrode, and an interelectrode isolation dielectric is arranged between the source electrode and the gate electrode.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a silicon carbide MOS device with a groove type JFET and a preparation process thereof.
Background
Silicon carbide (SiC) fabricated MOS field effect transistor power devices can withstand higher voltages and faster switching speeds than Si devices. Because silicon carbide is commonly used in high-voltage occasions, the doping concentration of the epitaxial layer is low, so that the proportion of JFET (junction field effect transistor) resistance in the MOSFET (metal-oxide-semiconductor field effect transistor) to the total on-resistance is large, and the on-resistance and the on-loss of the MOS device are increased. Moreover, since the silicon carbide MOS has high manufacturing cost and a high difficulty in defining the channel, how to obtain a narrower channel under the condition of reducing the number of times of photolithography becomes a difficulty in mass production of silicon carbide MOS devices at the present stage.
Because the silicon carbide MOS device has lower channel mobility, the size of a unit cell of the silicon carbide MOS device is often required to be reduced, and the proportion of channel resistance of the device in a conducting state is reduced by increasing the channel density. However, the cell size is reduced, and the on-resistance proportion of the JFET area of the device is increased. Meanwhile, the higher channel density also enables the device to have higher saturation current, which results in poor short-circuit characteristics of the device. Therefore, if the saturation current at the time of occurrence of a short circuit can be effectively reduced, the short circuit resistance of the device can be improved.
Disclosure of Invention
In view of the technical problems, the invention is used for providing a silicon carbide MOS device with a groove-type JFET and a preparation process thereof, wherein a current enhancement injection region is added in an active region, so that the problem of overlarge resistance of the JFET due to too low epitaxial doping concentration is solved.
In order to solve the technical problems, the invention adopts the following technical scheme:
one aspect of the embodiments of the present invention provides a silicon carbide MOS device with a trench JFET, including:
the doping type of the silicon carbide substrate material is a first conduction type;
a first conductive type semiconductor epitaxial layer and a drain electrode are respectively arranged on the front surface and the back surface of the silicon carbide substrate;
the active region of the first conduction type semiconductor epitaxial layer is provided with a first conduction type JFET region, the first conduction type JFET region is provided with a first surface, a second surface and a third surface, and the first surface and the second surface are respectively provided with a first conduction type source region and a second conduction type base region from outside to inside; a source electrode is arranged above the first surface, a gate dielectric and a gate electrode are arranged above the third surface, a second conductive type injection body region is arranged between the second conductive type base region and the source electrode, and an interelectrode isolation dielectric is arranged between the source electrode and the gate electrode.
Preferably, the concentration of the JFET area of the first conduction type is 1.2-1000 times higher than that of the epitaxial layer of the first conduction type.
Preferably, the first conductivity type is N-type and the second conductivity type is P-type.
Preferably, the first conductivity type is P-type and the second conductivity type is N-type.
In another aspect, the embodiment of the invention provides a preparation process of a silicon carbide MOS device with a groove-type JFET, which includes the following steps:
(a) the front surface and the back surface of the silicon carbide substrate are respectively provided with a first conductive type semiconductor epitaxial layer, wherein the doping type of the silicon carbide substrate material is the first conductive type; implanting first conductivity type ions on the first conductivity type epitaxial layer to form a first conductivity type JFET region;
(b) shielding part of the surface by using a mask material, and etching a silicon carbide table board by using ICP (inductively coupled plasma);
(c) using the same mask to carry out ion implantation;
(d) growing 10-100 nm SiO on the surface of the first conductive type semiconductor epitaxial layer by adopting thermal oxidation2Performing NO annealing to improve the reliability of gate oxide, and performing chemical vapor deposition on SiO2Growing 300-1000 nm polysilicon by upper deposition, photoetching and etching the gate oxide and the polysilicon of the reserved gate part by adopting the same photoetching plate, and forming a P-type doped gate;
(e) adopting chemical vapor deposition (BPSG) as a grid isolation medium, exposing a source electrode region through photoetching, evaporating Ni on the front surface and the back surface of a silicon carbide epitaxial wafer to serve as ohmic contact metal, annealing in a nitrogen atmosphere to form ohmic contact, and evaporating Ti and Al on the front surface to serve as source metal;
(f) adopting chemical vapor deposition SiN and spin-coating polyimide as passivation layers on the front metal, and exposing the source metal through photoetching and etching;
(g) and depositing Ti/Ni/Ag on the back surface to form back surface drain metal.
Preferably, the step (c) further comprises:
(c.1) obliquely injecting a second conductive type base region, wherein the injection angle and the angle of the plane of the wafer are 0-90 degrees;
(c.2) forming a second conductivity type body region using vertical implantation;
(c.3) obliquely implanting first conductive type ions to form a first conductive type source region, wherein the implantation angle and the angle of the plane of the wafer are 0-90 degrees;
and (c.4) after removing the mask, carrying out high-temperature activation annealing in inert gas to activate and implant impurities.
Preferably, in the step (a), the concentration of the first conductivity type JFET region is 1.2 to 1000 times higher than that of the first conductivity type epitaxial layer.
Preferably, in step (b), the etching depth is 0.1 to 4 um.
Preferably, the first conductivity type is N-type and the second conductivity type is P-type.
Preferably, the first conductivity type is P-type and the second conductivity type is N-type.
The invention has the following beneficial effects:
(1) a current reinforced injection region is added in the active region, so that the problem of overlarge resistance of the JFET caused by too low epitaxial doping concentration is solved;
(2) the same photoetching plate is used for defining mesa etching, a gate dielectric, a gate electrode, a body region, a base region and a source region, so that the photoetching number of MOS devices is greatly reduced, the volume production period is shortened, and the chip cost is effectively reduced;
(3) the channel resistance is reduced while the JFET resistance and the saturation current are kept low under the condition that the device is ensured to be under the condition of a small unit cell size. The reason is that after the doping of the JFET region is increased, the electric field of the gate oxide under reverse bias is very low, and the JFET region of the groove is pinched off, so that the saturation current is ensured to be low. Although the conventional MOSFET also has a JFET region, the JFET region cannot be pinched off during short-circuit operation, so that short-circuit current is high, and the short-circuit characteristic of the device is poor. Therefore, the invention can reduce the whole on-resistance of the device and ensure the strong short-circuit characteristic.
Drawings
Fig. 1 is a schematic structural diagram of a silicon carbide substrate with an epitaxial layer of a first conductivity type semiconductor on the front surface in a process for manufacturing a silicon carbide MOS device with a trench-type JFET according to an embodiment of the present invention;
FIG. 2 is a schematic structural diagram of a first conductivity type JFET region formed in a process for manufacturing a silicon carbide MOS device with trench type JFETs according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a silicon carbide mesa etched by ICP in the process for manufacturing a silicon carbide MOS device with a groove type JFET according to the embodiment of the invention;
FIG. 4 is a schematic structural diagram of a process for manufacturing a silicon carbide MOS device with a trench type JFET according to an embodiment of the present invention, wherein a second conductivity type base region is obliquely implanted;
FIG. 5 is a schematic structural diagram of a second conductivity type implanted body region formed by vertical implantation in a process for manufacturing a silicon carbide MOS device with a trench type JFET according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram of a first conductivity type source region formed in a process for manufacturing a silicon carbide MOS device with a trench type JFET according to an embodiment of the present invention;
FIG. 7 is a schematic structural diagram of a gate formed in a process for manufacturing a silicon carbide MOS device with a trench type JFET according to an embodiment of the invention;
fig. 8 is a schematic structural diagram of a silicon carbide MOS device with a groove-type JFET formed by a silicon carbide MOS device manufacturing process according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The embodiment of the invention discloses a step flow chart of a preparation process of a silicon carbide MOS device with a groove type JFET, which comprises the following steps:
(a) referring to fig. 1 and 2, a first conductive type semiconductor epitaxial layer 002 is provided on the front surface of a silicon carbide substrate 001, wherein the doping type of the material of the silicon carbide substrate 001 is the first conductive type; implanting first conductivity type ions on the first conductivity type epitaxial layer 002 to form a first conductivity type JFET region 009;
the advantages of adding a Junction Field-Effect Transistor (JFET) region are: firstly, a current reinforced injection region is added in an active region, so that the problem of overlarge JFET resistance caused by too low epitaxial doping concentration is solved; in addition, the embodiment of the invention can reduce the channel resistance and keep lower JFET resistance and lower saturation current under the condition of ensuring that the device has smaller cell size. The reason is that after the doping of the JFET region is increased, the electric field of the gate oxide under reverse bias is very low, and the JFET region of the groove is pinched off, so that the saturation current is ensured to be low. Although the conventional MOSFET also has a JFET region, the JFET region of the conventional MOSFET is not pinched off during short-circuit operation, resulting in high short-circuit current and poor short-circuit characteristics of the device. Therefore, the embodiment of the invention can reduce the whole on-resistance of the device and ensure the strong short-circuit characteristic.
(b) Referring to fig. 3, a mask material is used for shielding part of the surface, and a silicon carbide table top is etched by using ICP;
(c) using the same mask to carry out ion implantation; the benefits of using the same mask are: the same photoetching plate is used for defining mesa etching, a gate medium, a gate electrode, a body region, a base region and a source region, so that the photoetching number of MOS devices is greatly reduced, the production period is shortened, and the manufacturing cost of chips is effectively reduced.
Specifically, the step (c) further comprises:
the method specifically comprises the following steps:
(c.1) referring to fig. 4, the second conductive type base region 005 is implanted with an inclination, and the implantation angle is 0 to 90 degrees with respect to the wafer plane;
(c.2) referring to fig. 5, a second conductive type implant body region 010 is formed using vertical implantation;
(c.3) forming a first conductive type source region 004 by obliquely implanting first conductive type ions, wherein the implantation angle is 0 to 90 degrees with respect to the plane of the wafer, referring to fig. 6;
and (c.4) after removing the mask, carrying out high-temperature activation annealing in inert gas to activate and implant impurities.
(d) Referring to fig. 7, a gate dielectric 007 with the thickness of 10-100 nm is grown on the surface of a first conductive type semiconductor epitaxial layer 002 by thermal oxidation and NO annealing is performed, the reliability of gate oxide is improved, a gate 008 with the thickness of 300-1000 nm is deposited and grown on the gate dielectric 007 by chemical vapor deposition, the gate oxide and polysilicon at the gate part are kept by photoetching and etching by using the same photomask, and a P-type doped gate 008 is formed;
(e) adopting chemical vapor deposition BPSG as a grid isolation medium 011, exposing a source electrode 006 region through photoetching, evaporating Ni on the front side and the back side of a silicon carbide epitaxial wafer to be used as ohmic contact metal, annealing in a nitrogen atmosphere to form ohmic contact, and evaporating Ti and Al on the front side to be used as source metal;
(f) adopting chemical vapor deposition SiN and spin-coating polyimide as passivation layers on the front metal, and exposing the source metal through photoetching and etching;
(g) and depositing Ti/Ni/Ag on the back to form a back drain metal 003.
The silicon carbide MOS device with the groove-type JFET prepared by the above process has a structure shown in fig. 8, that is, the silicon carbide MOS device with the groove-type JFET according to another embodiment of the present invention includes:
the silicon carbide substrate 001 is made of a silicon carbide substrate 001 material, and the doping type of the silicon carbide substrate 001 material is a first conduction type;
a first conductive type semiconductor epitaxial layer 002 and a drain electrode 003 are respectively arranged on the front surface and the back surface of the silicon carbide substrate 001;
a JFET region 009 is arranged on the active region of the first conductive type semiconductor epitaxial layer 002, the JFET region 009 is provided with a first surface, a second surface and a third surface, wherein the first surface and the second surface are respectively provided with a first conductive type source region 004 and a second conductive type base region 005 from outside to inside; a source electrode 006 is arranged above the first surface, a gate dielectric 007 and a gate electrode 008 are arranged above the third surface, a second conductive type injection body area 010 is arranged between the second conductive type base area 005 and the source electrode 006, and an interelectrode isolation dielectric 011 is arranged between the source electrode 006 and the gate electrode 008.
In order to enable a person skilled in the art to better understand the implementation process of the embodiment of the present invention, in a specific application example, the process of the preparation process of the silicon carbide MOS device with the trench-type JFET according to the embodiment of the present invention is further described with the first conductivity type being N-type and the second conductivity type being P-type, and includes the following steps:
(a) firstly, injecting N ions into a silicon carbide N-type epitaxial layer to form an N-type JFET region, wherein the concentration of a current enhancement region is 1.2-1000 times higher than that of the epitaxial layer.
(b) And (3) shielding part of the surface by using a mask material, and etching the silicon carbide mesa by using ICP (inductively coupled plasma), wherein the etching depth is 0.1-4 um.
(c) And performing ion implantation by using the same mask, wherein the specific process comprises the following steps:
and (c.1) obliquely injecting Al ions to form a P-type base region, wherein the injection angle and the plane angle of the wafer are 0-90 degrees.
And (c.2) forming a P + type body region by vertically injecting Al ions.
And (c.3) adopting inclined implantation of N ions to form an N + type source region, wherein the implantation angle and the plane angle of the wafer are 0-90 degrees.
And (c.4) after removing the mask, carrying out high-temperature activation annealing in inert gas to activate and implant impurities.
(d) Growing 10-100 nm SiO on the surface of the SiC epitaxial layer by thermal oxidation2And NO annealing is carried out, so that the reliability of the gate oxide is improved. By chemical vapor deposition on SiO2And growing 300-1000 nm polysilicon by upper deposition, photoetching and etching the gate oxide and the polysilicon of the reserved gate part by adopting the same photoetching plate, and forming a P-type doped gate.
(e) And (3) adopting chemical vapor deposition (BPSG) as an isolation medium, and exposing the source electrode region through photoetching. Ni is evaporated on the front surface and the back surface of the silicon carbide epitaxial wafer to be used as ohmic contact metal, and the ohmic contact is formed by annealing in a nitrogen atmosphere. Since Ni reacts with SiC, part of the N + -type source region is reacted away. Ti and Al are evaporated on the front surface to be used as source electrode metals.
In other application examples, the first conductivity type may be N-type and the second conductivity type may be P-type according to different material choices.
It is to be understood that the exemplary embodiments described herein are illustrative and not restrictive. Although one or more embodiments of the present invention have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the following claims.
Claims (10)
1. A silicon carbide MOS device with a trench JFET, comprising:
the silicon carbide substrate (001) is made of a silicon carbide substrate (001) material, and the doping type of the silicon carbide substrate (001) material is a first conduction type;
a first conductive type semiconductor epitaxial layer (002) and a drain electrode (003) are respectively arranged on the front surface and the back surface of a silicon carbide substrate (001);
a first conduction type JFET region (009) is arranged on an active region of the first conduction type semiconductor epitaxial layer (002), a first surface, a second surface and a third surface are arranged on the first conduction type JFET region (009), and a first conduction type source region (004) and a second conduction type base region (005) are respectively arranged on the first surface and the second surface from outside to inside; a source electrode (006) is arranged above the first surface, a gate dielectric (007) and a gate electrode (008) are arranged above the third surface, a second conductive type injection body region (010) is arranged between the second conductive type base region (005) and the source electrode (006), and an interelectrode isolation dielectric (011) is arranged between the source electrode (006) and the gate electrode (008).
2. The silicon carbide MOS device with the trench-type JFET of claim 1, wherein the concentration of the first-conductivity-type JFET region (009) is higher than the concentration of the first-conductivity-type epitaxial layer (002) by a factor of 1.2 to 1000.
3. The silicon carbide MOS device with the slotted JFET of claim 1 wherein the first conductivity type is N-type and the second conductivity type is P-type.
4. The silicon carbide MOS device with the slotted JFET of claim 1 wherein the first conductivity type is P-type and the second conductivity type is N-type.
5. A preparation process of a silicon carbide MOS device with a groove type JFET (junction field effect transistor) is characterized by comprising the following steps of:
(a) a first conductive type semiconductor epitaxial layer (002) is respectively arranged on the front surface and the back surface of a silicon carbide substrate (001), wherein the doping type of the material of the silicon carbide substrate (001) is the first conductive type; implanting first conductivity type ions on the first conductivity type epitaxial layer (002) to form a first conductivity type JFET region (009);
(b) shielding part of the surface by using a mask material, and etching a silicon carbide table board by using ICP (inductively coupled plasma);
(c) using the same mask to carry out ion implantation;
(d) growing a 10-100 nm gate dielectric (007) on the surface of a first conductive type semiconductor epitaxial layer (002) by adopting thermal oxidation, carrying out NO annealing, improving the reliability of gate oxide, depositing and growing a 300-1000 nm gate (008) on the gate dielectric (007) by adopting chemical vapor deposition, photoetching and etching by adopting the same photoetching plate to retain the gate oxide and polysilicon of a gate part, and forming a P-type doped gate (008);
(e) adopting chemical vapor deposition BPSG as an inter-gate isolation medium (011), exposing a source electrode region through photoetching, evaporating Ni on the front side and the back side of a silicon carbide epitaxial wafer to be used as ohmic contact metal, annealing in a nitrogen atmosphere to form ohmic contact, and evaporating Ti and Al on the front side to be used as source metal;
(f) adopting chemical vapor deposition SiN and spin-coating polyimide as passivation layers on the front metal, and exposing the source metal through photoetching and etching;
(g) and depositing Ti/Ni/Ag on the back surface to form back surface drain metal (003).
6. The process for preparing a silicon carbide MOS device with a slotted JFET of claim 5, wherein the step (c) further comprises:
(c.1) obliquely injecting a second conductive type base region, wherein the injection angle and the angle of the plane of the wafer are 0-90 degrees;
(c.2) forming a second conductivity type body region using vertical implantation;
(c.3) obliquely implanting first conductive type ions to form a first conductive type source region, wherein the implantation angle and the angle of the plane of the wafer are 0-90 degrees;
and (c.4) after removing the mask, carrying out high-temperature activation annealing in inert gas to activate and implant impurities.
7. The process for preparing a silicon carbide MOS device with trench type JFETs according to claim 5 or 6, wherein in the step (a), the concentration of the first conductivity type JFET regions (009) is higher than the concentration of the first conductivity type epitaxial layer (002) by 1.2 to 1000 times.
8. The process for preparing a silicon carbide MOS device with a trench type JFET according to claim 3 or 4, wherein in the step (b), the etching depth is 0.1 to 4 um.
9. The process for preparing a silicon carbide MOS device with a slotted JFET of claim 5, wherein the first conductivity type is N-type and the second conductivity type is P-type.
10. The process for preparing a silicon carbide MOS device with a slotted JFET of claim 5, wherein the first conductivity type is P-type and the second conductivity type is N-type.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113257897A (en) * | 2021-06-10 | 2021-08-13 | 北京中科新微特科技开发股份有限公司 | Semiconductor device and method for manufacturing the same |
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| CN113257897A (en) * | 2021-06-10 | 2021-08-13 | 北京中科新微特科技开发股份有限公司 | Semiconductor device and method for manufacturing the same |
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