CN106876485B - SiC double-groove MOSFET device integrated with Schottky diode and preparation method thereof - Google Patents
SiC double-groove MOSFET device integrated with Schottky diode and preparation method thereof Download PDFInfo
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Abstract
The invention discloses a SiC double-groove type MOSFET device integrated with a Schottky diode, wherein two grooves are arranged in a cell structure of an active area of the SiC double-groove type MOSFET device, namely a grid groove arranged in the center of the cell structure and a source groove arranged at the periphery of the grid groove; the periphery of the bottom of the gate trench and the periphery of the bottom of the source trench are doped with the conductivity type opposite to that of the drift region; a Schottky contact is arranged in the central area of the bottom of the source groove to form a Schottky diode electrically communicated with the source electrode; forming ohmic contact in the periphery of the bottom of the source trench and the doped region with the opposite conductivity type of the drift region; the depth of both trenches is greater than the p-base region. The MOS gate adopts a source and gate double-groove structure, and the bottom of the gate groove and the periphery of the bottom of the source groove are doped with the conduction type opposite to that of the drift region, so that the MOS gate is shielded, and the reliability of the gate is improved. Meanwhile, the electric field of the base region can be shielded, and the base region is prevented from penetrating through; and integrates a MPS schottky diode with high surge capability.
Description
Technical Field
The invention belongs to the field of semiconductors, and particularly relates to a SiC double-groove MOSFET device integrated with a Schottky diode and a preparation method thereof.
Background
SiC U-channel mosfets (umosfets) have many advantages, such as the p-base region can be formed by epitaxial growth, eliminating the effects of defects when the p-base region is formed by ion implantation, better MOS gate quality and channel mobility, and easier control of channel length. In addition, the cell structure (the basic unit forming the active region of the device) of the trench MOSFET can be smaller, the current density is higher, particularly for the expensive price of SiC materials, and the chip cost can be obviously reduced. However, the UMOSFET has the problem that the electric field at the bottom of the trench is concentrated, so that the reliability of the gate dielectric is poor. As shown in fig. 1, which is a schematic diagram of a conventional n-channel UMOSFET cell structure, in the off state, a high voltage applied to the drain acts on the drift layer, the point a at the bottom of the trench is where the electric field is most concentrated, and the electric field strength in the dielectric is 2-3 times that in SiC, resulting in the gate dielectric at the bottom of the trench being easily broken down and having poor reliability.
On the other hand, in many applications, such as full-bridge application, the transistor needs to be connected with a freewheeling diode in an anti-parallel mode to work together, and as a currently common silicon IGBT module, a silicon fast recovery diode is connected in an anti-parallel mode to serve as the freewheeling diode. If the free wheel diode is integrated in one device, the integration level and the reliability of the chip are improved, and the cost of the chip is effectively reduced.
Disclosure of Invention
In view of the problems in the prior art, an object of the present invention is to provide a SiC double trench MOSFET device integrated with a schottky diode, which effectively solves the problems in the prior art. Another object of the present invention is to provide a method of fabricating a SiC double trench MOSFET device integrated with a schottky diode.
In order to achieve the purpose, the invention adopts the following technical scheme:
a SiC double-groove type MOSFET device integrated with a Schottky diode is characterized in that a cell structure of an active region of the SiC double-groove type MOSFET device sequentially comprises a drain electrode, an n + substrate, a buffer layer, an n-drift layer, a p base region and an n + + layer from bottom to top; two grooves are arranged in the cell structure, namely a grid groove arranged in the center of the cell structure and a source groove arranged on the periphery of the grid groove; the periphery of the bottom of the gate trench and the periphery of the bottom of the source trench are doped with the conductivity type opposite to that of the drift region; a Schottky contact is arranged in the central area of the bottom of the source groove to form a Schottky diode electrically communicated with the source electrode; forming ohmic contact in the periphery of the bottom of the source trench and the doped region with the opposite conductivity type of the drift region; the depth of both trenches is greater than the p-base region.
Further, the p + region under the gate trench is floating, i.e., not in electrical communication with the source.
Further, a p + region under the gate trench is in electrical communication with the source and the p-base region.
Furthermore, the doping concentration of the p base region is 1E15-5E17cm-3The thickness of the p base region is 0.2-3 μm.
Further, the doping concentration of the n + + layer is more than 1E19cm-3And the thickness of the n + + layer is 0.2-2 μm.
Furthermore, the doping concentration of a region below the p-base region and between the doping depths of the bottom of the gate trench and the bottom of the source trench is higher than that of the n-drift layer.
Further, the p-type doped region at the bottom of the trench of the source trench is electrically connected with the p-base region through the doping of the side wall of the source trench, that is, the source electrode is also electrically connected with the p-base region.
A method of making a SiC double trench MOSFET device integrated with a schottky diode, said method comprising the steps of:
1) preparing a buffer layer, an n-drift layer, a p base region and an n + + layer on a substrate in sequence;
2) making a first patterned mask layer on the SiC surface, depositing by CVD method, and photoetching to form SiO2A graph; etching the SiC groove by an ICP method to form a source groove and a grid groove; simultaneously, etching the junction terminal area and the scribing area;
3) making a second mask layer on the surface of the SiC, taking the second mask layer as a mask for subsequent injection, performing Al ion injection, and forming doping on the side wall and the periphery of the bottom of the source trench, wherein the injection direction is a direction vertical to the wafer direction and a direction with a set inclination angle; removing the second mask layer after the injection is finished;
4) a third mask layer is formed on the surface of the SiC, and after deposition is finished, a photoetching method is used for forming covering protection by using glue as a fourth mask layer in other areas, no photoresist is arranged in a gate groove, and meanwhile, a glue mask in the form of a field limiting ring is also formed in a junction terminal area; removing SiO at the bottom of the gate trench by ICP anisotropic etching2Dielectric while continuing to retain SiO on the sidewall of the gate trench2A dielectric protecting the gate channel region; injecting Al ions to form p + doping at the bottom of the gate trench; removing photoresist and SiO after the injection2Medium, and RCA cleaning; depositing a graphite layer on the surface, and carrying out high-temperature activation annealing; with O2、N2Removing the graphite layer by plasma etching or thermal oxidation;
5) cleaning with RCA and BOE, and performing sacrificial oxidation; growing a layer of SiO by thermal oxidation2Removing by BOE corrosion; growing a gate dielectric layer by thermal oxidation, oxidizing, and then growing NO or N2O or POCl3Annealing in atmosphere; depositing high-doped polysilicon by CVD method, or depositing undoped polycrystal, and then forming doped polysilicon by injection and annealing method; filling the gate trench with polysilicon, and planarizing the surface; forming a photomask by using a photoetching method, and etching off the polycrystalline silicon outside the gate trench to form a polycrystalline silicon gate;
6) and depositing an isolation passivation layer, removing the medium in the source groove and the ohmic contact area by using a photoetching method, and reserving the medium on the gate polysilicon to form the isolation between the gate and the source. Depositing ohmic contact metal on the source ohmic contact area, depositing ohmic contact metal on the back surface, and performing rapid thermal annealing in vacuum or inert atmosphere to respectively form source and drain ohmic contacts;
7) depositing Schottky metal by a PVD method, removing metal in other areas outside the source groove and the ohmic contact area by a photoetching re-etching method, and performing thermal annealing to form Schottky contact in the middle area at the bottom of the source groove and form ohmic contact in the peripheral highly-doped p + area;
8) making thick electrode metal, electrically connecting a source electrode with the Schottky metal, and isolating the electrode pressing metal above the primitive cell from the grid electrode through an isolation passivation layer; making thick electrode metal on the back; and finally, a thick passivation layer is formed, and a window is opened to expose the metal welding area of the source and gate voltage blocks.
Further, the substrate in the step 1) is a high-doping low-resistance n + layer, and the concentration of the n + layer is more than 1E18cm-3The thickness of the buffer layer is 1-2 μm; the concentration of the drift layer is 1E14-1E17cm-3The thickness is more than 5 mu m; the doping concentration of the p-base region is 1E15-5E17cm-3The thickness is 0.2-3 μm; the concentration of the n + + layer is greater than 1E19cm-3And the thickness is more than 0.2 mu m.
Further, the first mask layer in the step 2) is SiO22-4 μm in thickness, the source and the gateThe depth of the groove is larger than the sum of the thicknesses of the n + + layer and the p base region and is 1-4 mu m; the width of the gate trench is 0.5-2 μm, the width of the source trench is 2.5-10 μm, and SiO is used2The selectivity ratio of mask etching SiC is greater than 3.
Further, the concentration of the doped region in the step 3) is more than 1E18cm-3Surface concentration greater than 1E19cm-3And the depth is more than 0.35 mu m.
Further, the p + doping concentration formed at the bottom of the gate trench in the step 4) is more than 1E18cm-3Depth greater than 0.35 μm; the thickness of the graphite layer is 10-100 nm; the annealing temperature of the high-temperature activation annealing is more than 1600 ℃ and the time is more than 3 minutes.
Further, SiO grown by thermal oxidation method in step 5)2The thickness is 10-100 nm; the temperature of thermal oxidation is 1200-1500 ℃, and the thermal oxidation is carried out at O2And (3) performing in an atmosphere.
Further, the isolation passivation layer in the step 6) is SiO deposited by using a CVD method2Or a layer of SiOxNy with a thickness of more than 0.5 μm; the annealing temperature of the rapid thermal annealing is between 900 and 1100 ℃, and the time is between 1 minute and 15 minutes; the ohmic contact metal of the source and the drain is Ni or Ti/Ni.
Further, the schottky metal in the step 7) is Ti, Mo, Ni or Pt; the annealing temperature of the thermal annealing is 400-600 ℃, and the time is 5-30 minutes.
Further, the thick passivation layer in the step 8) is SiO2、Si3N4Or a polyimide.
Further, a JFET layer is arranged between the n-drift region and the p-base region in the step 1), and the concentration of the JFET layer is less than 1E18cm-3And the thickness of the p-type base region is equal to the distance from the p-type base region to the junction depth of the p + type region under the gate trench.
The invention has the following beneficial technical effects:
the MOS gate adopts a source and gate double-groove structure, and the bottom of the gate groove and the periphery of the bottom of the source groove are doped with the conduction type opposite to that of the drift region, so that the MOS gate is shielded, and the reliability of the gate is improved. Meanwhile, the electric field of the base region can be shielded, and the base region is prevented from being penetrated. And (3) making Schottky contact in the central region of the bottom of the source trench, forming ohmic contact with the peripheral opposite-conductivity-type doped region, and integrating the MPS Schottky diode with high surge capacity.
Drawings
FIG. 1 is a schematic diagram of a prior art cell plan structure of a UMOSFET;
FIG. 2 is a schematic diagram of a planar structure of a cell of the MOSFET device of the present invention;
FIG. 3 is a schematic plan view of a device with a hexagonal cell close-packed active region according to an embodiment of the present invention;
FIG. 4 is a circuit schematic of a MOSFET device of the present invention;
FIG. 5 is a schematic view of an epitaxial material structure during the fabrication of a MOSFET device according to the present invention;
FIG. 6 is a schematic diagram of a planar structure of a cell after etching a SiC trench in the process of manufacturing a MOSFET device according to the present invention;
FIG. 7 is a schematic diagram of a planar structure of a cell after source trench ion implantation in a process of manufacturing a MOSFET device according to the present invention;
FIG. 8 is a schematic diagram of a planar structure of a cell after ion implantation of a gate trench in a process of manufacturing a MOSFET device according to the present invention;
FIG. 9 is a schematic diagram of a planar structure of a cell after forming a polysilicon gate in a process of fabricating a MOSFET device according to the present invention;
FIG. 10 is a schematic diagram of a planar structure of a cell after source and drain ohmic contacts are formed in a MOSFET device fabrication process in accordance with the present invention;
FIG. 11 is a schematic diagram of a planar structure of a cell after a Schottky contact is formed during the fabrication of a MOSFET device according to the present invention;
fig. 12 is a schematic plan view of a cell after the MOSFET device of the present invention is fabricated.
Detailed Description
The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
As shown in fig. 2, the invention provides a SiC double-trench MOSFET device integrated with a schottky diode, wherein a cell structure of an active region of the SiC double-trench MOSFET device sequentially comprises a drain electrode, an n + substrate, a buffer layer, an n-drift layer, a p-base region and an n + + layer from bottom to top; two grooves are arranged in the cell structure, namely a grid groove arranged in the center of the cell structure and a source groove arranged on the periphery of the grid groove; the periphery of the bottom of the gate trench and the periphery of the bottom of the source trench are doped with the conductivity type opposite to that of the drift region, so that on one hand, the electric fields at the bottoms of the gate trench and the source trench can be shielded together with the doping at the bottom of the gate trench, the concentration of the electric fields is reduced, and the reliability is provided; on the other hand, the embedded pn diode part also used as an integrated Schottky diode has high surge resistance; a Schottky contact is arranged in the central area of the bottom of the source groove to form a Schottky diode electrically communicated with the source electrode; forming ohmic contact in the periphery of the bottom of the source trench and the doped region with the opposite conductivity type of the drift region; the depth of the two grooves is larger than that of the p base region; the depth of the gate trench and the depth of the source trench may be the same or different, and preferably, the depth of the gate trench and the depth of the source trench are the same, so that the gate trench and the source trench can be formed simultaneously by one-step etching in the device manufacturing process.
The p + region under the gate trench is floating, i.e., not in electrical communication with the source, in one embodiment of the invention. In another embodiment of the invention, the p + region under the gate trench is in electrical communication with the source and the p-base regions, and since the gate trench is in communication, sidewall implantation is also performed through a portion of the region of the gate trench to complete electrical communication between the p + and p-base regions and thus the source, while the gate in that portion of the region is no longer functional.
The base region layer (for an n-type MOSFET, the p-base region layer is the same as the p-type MOSFET) of the device is formed by epitaxial growth, so that the device has very good material quality and very accurate thickness and doping concentration, and is beneficial to manufacturing a high-quality MOS gate structure. The doping concentration is 1E15-5E17cm-3And designing according to the threshold voltage. The base layer thickness is greater than 0.2 μm, preferably between 0.2-3 μm, too thin to punch through easily and too thick to increase the channel length and resistance.
An n + + layer on the p base region is used as a source electrode conductive layer, and the doping concentration is more than 1E19cm-3And a thickness of more than 0.2 μm, preferably between 0.2 and 2 μm. Ohmic contacts with too thin a thickness are easily pierced and too thick increases the on-resistance and the depth and difficulty of etching the trench.
And the n-layer below the p base region is used as a voltage-resistant drift layer of the device, the doping concentration and the thickness of the n-layer are determined according to the voltage resistance of the device design, and the n-layer is optimally designed by minimizing the on-resistance under a certain voltage resistance. For example, for a 1200V device, the concentration may be 5-8E15cm-3The thickness may be 10-15 μm. The doping concentration in the region below the p-base region and between the doping depths of the trench bottom may also be slightly higher than that of the drift layer, e.g. may be 1E16-1E17cm-3The main purpose of the method is to reduce diffusion of electrons to all directions of the drift layer after passing through the channel and reduce on-resistance. The doping concentration of the n + substrate is greater than 1E18cm-3。
The p-type doped region at the bottom of the trench is electrically communicated with the p-base region layer through the doping of the side wall of the source trench, so that the source electrode is also electrically communicated with the p-base region at the same time, and a parasitic npn structure is avoided. The p doping around the bottom of the source groove is a high-concentration p-type area, which is beneficial to forming ohmic contact with metal and is connected with the Schottky contact at the center, so that the Schottky diode embedded into the pn diode is formed together.
As shown in fig. 3, wherein the cross-sectional structure of AA' is schematically shown in fig. 1. The plane structure of the primitive cell can be in various forms such as rectangle, strip, hexagon and the like. The simple parallel arrangement of the primitive cells forms the active region of a device, and the arrangement mode can be simple arrangement, and can also be in the forms of close arrangement, atomic structure arrangement and the like. Meanwhile, the whole device consists of an active region, a junction terminal region and a scribing groove region, metal extraction is carried out on the grid and the source of each cell on the active region respectively, corresponding briquetting metal is made, and subsequent packaging application of the device is facilitated. This is well known to the engineers in the industry and is not shown on the schematic.
As shown in fig. 4, the MOSFET and the schottky diode form an anti-parallel circuit structure, which realizes integration in one chip. The power density and reliability of the device can be effectively increased, and the volume and cost of the packaged module or system can be reduced.
The n-type doping and the p-type doping referred to in the present invention are relative terms, and may also be referred to as a first doping and a second doping, i.e., the interchanging of n-type and p-type is equally applicable to the device.
The device structure of the invention is not only suitable for SiC, but also suitable for Si, GaN and Ga2O3And the like, but the preparation method is different.
The SiC MOSFET structure can be used for other MOS-controlled transistor structures, such as IGBT. There are related structures and principles in the structural part of MOS control.
The invention also provides a method for preparing the SiC double-groove type MOSFET device of the integrated Schottky diode, and the method is explained in detail by taking an n-type (n-channel) SiC MOSFET as an example.
As shown in FIG. 5, the substrate (or referred to as a base plate) is a highly doped, low resistance n + layer with a concentration greater than 1E18cm-3. The concentration of the buffer layer was approximately 1E18cm-3Approximately 1-2 μm thick, the purpose of the buffer layer being to reduce the lattice mismatch between the substrate and the epitaxial layer, while terminating part of the defects of the substrate in the buffer layer and avoiding the defects extending to the drift layer. The concentration of the drift layer is 1E14-1E17cm-3The thickness is larger than 5 μm, the device voltage-resistant function is born, and the concentration and the thickness are determined according to the rated voltage-resistant optimized design of the device. A p-base region layer with a concentration of 1E15-5E17cm is arranged on the drift region-3The thickness is more than 0.2 μm, preferably 0.2-2 μm. In another embodiment, a JFET layer is arranged between the n-drift region and the p-base region and has the concentration of less than 1E18cm-3And the thickness is approximately equal to the distance from the p base region to the junction depth of the p + region under the gate, so that the on-resistance between JFET regions is reduced. An n + region is arranged above the p base region and has a doping concentration greater than 1E19cm-3And the thickness is more than 0.2 mu m.
As shown in fig. 6, a first mask is patterned on the SiC surface. The first mask may be typically SiO2The thickness is determined by adding the thickness required by the mask to the SiO consumed in etching the trench2The sum of the thicknesses is generally from 2 to 4 μm. By CVD, followed by photolithographic etching to form SiO2And (6) a graph. And etching the SiC groove by using an ICP method to form a source groove and a grid groove. And the junction termination region and the scribe region are etched. The depth of the trench is slightly deeper than the sum of the thicknesses of the n + + region and the p-base region, typically between 1-4 μm, depending on the breakdown voltage and on-resistance of the device being designed. The width of the gate trench is preferably between 0.5-2 μm and the width of the source trench is preferably between 2.5-10 μm. By SiO2The SiC selection ratio of mask etching can be more than 3, so most SiO will remain after etching2And the mask is used as a blocking mask for the next ion implantation. In addition, SiO is used2The mask etching SiC can obtain the effect of a groove with low defect and U-shaped bottom, and is beneficial to the reliability of the device.
As shown in fig. 7, a second mask is applied as a mask for a subsequent implantation. The mask protects the middle schottky region and the gate trench within the source trench. The width of the middle schottky region is typically 1.5-8 μm. The mask may be a photoresist, a dielectric, or the like, and preferably may be a photoresist. The mask thickness depends on the mask material and the energy of the subsequent ion implantation, typically above 2.5 μm for photoresist. Performing Al ion implantation to form a doped region with a concentration greater than 1E18cm-3Surface concentration greater than 1E19cm-3And the depth is more than 0.35 mu m. The direction of implantation is perpendicular to the wafer direction and with a certain tilt angle. The directional injection with a certain inclination angle is mainly used for effectively injecting the side wall of the source groove to form highly doped p +, and the electric communication between the source electrode and the p base region is completed. The purpose of the higher implantation concentration of the surface is to form a surface with higher doping concentration so as to facilitate the subsequent ohmic contact of the p + region at the bottom of the source trench. And removing the second mask after the implantation is finished.
As shown in FIG. 8, a third mask layer, preferably a dielectric such as SiO, is deposited on the surface2. The third mask is mainly used for protecting the side wall of the gate trench in the subsequent injection. After deposition, using photoetching method to form covering protection in other region by using glue as fourth mask layer, and forming junction terminal region without photoresist in gate trenchA glue mask in the form of a field limiting ring. Removing SiO at the bottom of the gate trench by ICP anisotropic etching2Dielectric while continuing to retain SiO on the sidewall of the gate trench2And the dielectric protects the gate channel region. Al ion implantation to form p + doping at the bottom of the gate trench with concentration greater than 1E18cm-3And the depth is more than 0.35 μm, and the depth is preferably consistent with the p + region at the bottom of the source trench. Meanwhile, a junction termination structure in the form of a field limiting ring is also formed, and other junction termination structures such as an implanted JTE (junction termination extension), an etched JTE, a JTE and field limiting ring combination form, and the like can be adopted in other embodiments of the present invention. Removing photoresist and SiO after the injection2Media, and RCA cleaning. Depositing a graphite layer on the surface, the thickness is about 10-100nm, and carrying out high-temperature activation annealing at the annealing temperature of more than 1600 ℃ for more than 3 minutes. With O2、N2And removing the graphite layer by plasma etching or thermal oxidation.
As shown in fig. 9, a sacrificial oxidation process was performed with RCA and BOE cleans. Growing a layer of SiO by thermal oxidation2And the thickness is about 10-100nm, and the BOE etching is used for removing the film. The sacrificial oxidation process can remove defects and damaged layers caused by surface etching. And growing a gate dielectric layer by a thermal oxidation method, wherein the thickness is determined according to the threshold voltage of the device, and the preferred thickness is 40-80 nm. The temperature of thermal oxidation is 1200-1500 ℃, and the thermal oxidation is carried out at O2In the atmosphere, oxidizing and then adding NO or N2O or POCl3And annealing in the same atmosphere to improve the interface state of the MOS. The CVD method is used to deposit the high-doped polysilicon, or the non-doped polysilicon can be deposited first, and then the doping is formed by the implantation and annealing method. And filling the gate trench with polysilicon, and flattening the surface. And forming a photomask by using a photoetching method, and etching off the polycrystalline silicon outside the gate groove to form a polycrystalline silicon gate.
As shown in FIG. 10, an isolation passivation layer is deposited, typically by CVD, to deposit SiO2Or SiOxNy layer, the thickness is preferably larger than 0.5 μm, the media of the source trench and the ohmic contact region are removed by a photoetching method, the media on the gate polysilicon are reserved, and the isolation between the gate and the source is formed. Depositing ohmic contact metal on source ohmic contact areaDepositing ohmic contact metal on the back, and performing rapid thermal annealing at 900-1100 ℃ for 1-15 minutes in vacuum or inert atmosphere to form source and drain ohmic contacts respectively. The ohmic contact metal of the source and drain is generally Ni, Ti/Ni, etc.
As shown in fig. 11, a schottky metal is deposited by PVD. The PVD method can produce isotropic metal deposition, which is beneficial to the metal deposition of the source trench side wall. And removing the metal in the source groove and other areas outside the ohmic contact area by using a photoetching re-etching method. The Schottky metal may be Ti, Mo, Ni, Pt, etc. And then carrying out thermal annealing, for example, for the Ti Schottky metal, the annealing temperature is 400-600 ℃, the time is 5-30 minutes, forming Schottky contact in the middle area of the bottom of the source trench, and simultaneously forming ohmic contact in the peripheral highly-doped p + area. Annealing may improve the performance and uniformity of the schottky contact.
As shown in fig. 12, the thick electrode metal is made to facilitate the encapsulation of the device in application. The source is in electrical communication with the schottky metal, and the electrode block metal is above the cell and isolated from the gate by an isolation passivation layer. The gate electrode compact metal is led out at the other end as shown in the plan view of fig. 3. And the back surface is provided with thick electrode metal. Finally, a thick passivation layer, such as SiO, is formed2、Si3N4Polyimide, etc. and opening the window to expose the bonding area of the source and gate voltage block metals.
The above description is only for the purpose of illustrating the present invention, and it should be understood that the present invention is not limited to the above embodiments, and various modifications conforming to the spirit of the present invention are within the scope of the present invention.
Claims (10)
1. A method for preparing a SiC double-groove type MOSFET device of an integrated Schottky diode is characterized by comprising the following steps:
1) preparing a buffer layer, an n-drift layer, a p base region and an n + + layer on a substrate in sequence;
2) making a first patterned mask layer on the SiC surface, depositing by CVD method, and photoetching to form SiO2A graph; by usingEtching the SiC groove by an ICP method to form a source groove and a grid groove; simultaneously, etching the junction terminal area and the scribing area;
3) making a second mask layer on the surface of the SiC, taking the second mask layer as a mask for subsequent injection, performing Al ion injection, and forming doped regions on the side wall and the periphery of the bottom of the source trench, wherein the injection direction is a direction vertical to the wafer direction and a direction with a set inclination angle; removing the second mask layer after the injection is finished;
4) a third mask layer is formed on the surface of the SiC, and after deposition is finished, a photoetching method is used for forming covering protection by using glue as a fourth mask layer in other areas, no photoresist is arranged in a gate groove, and meanwhile, a glue mask in the form of a field limiting ring is also formed in a junction terminal area; removing SiO at the bottom of the gate trench by ICP anisotropic etching2Dielectric while continuing to retain SiO on the sidewall of the gate trench2A dielectric protecting the gate channel region; injecting Al ions to form p + doping at the bottom of the gate trench; removing photoresist and SiO after the injection2Medium, and RCA cleaning; depositing a graphite layer on the surface, and carrying out high-temperature activation annealing; with O2、N2Removing the graphite layer by plasma etching or thermal oxidation;
5) cleaning with RCA and BOE, and performing sacrificial oxidation; growing a layer of SiO by thermal oxidation2Removing by BOE corrosion; growing a gate dielectric layer by thermal oxidation, oxidizing, and then growing NO or N2O or POCl3Annealing in atmosphere; depositing high-doped polysilicon by CVD method, or depositing undoped polycrystal, and then forming doped polysilicon by injection and annealing method; filling the gate trench with polysilicon, and planarizing the surface; forming a photomask by using a photoetching method, and etching off the polycrystalline silicon outside the gate trench to form a polycrystalline silicon gate;
6) depositing an isolation passivation layer, removing the medium in the source groove and the ohmic contact area by using a photoetching method, and reserving the medium on the gate polysilicon to form the isolation between the gate and the source; depositing ohmic contact metal on the source ohmic contact area, depositing ohmic contact metal on the back surface, and performing rapid thermal annealing in vacuum or inert atmosphere to respectively form source and drain ohmic contacts;
7) depositing Schottky metal by a PVD method, removing metal in other areas outside the source groove and the ohmic contact area by a photoetching re-etching method, and performing thermal annealing to form Schottky contact in the middle area at the bottom of the source groove and form ohmic contact in the peripheral highly-doped p + area;
8) making thick electrode metal, electrically connecting a source electrode with the Schottky metal, and isolating the electrode pressing metal above the primitive cell from the grid electrode through an isolation passivation layer; making thick electrode metal on the back; and finally, a thick passivation layer is formed, and a window is opened to expose the metal welding area of the source and gate voltage blocks.
2. The method of claim 1, wherein the substrate of step 1) is a highly doped low resistance n + layer with a concentration greater than 1E18cm-3The thickness of the buffer layer is 1-2 μm; the concentration of the drift layer is 1E14-1E17cm-3The thickness is more than 5 mu m; the doping concentration of the p base region is 1E15-5E17cm-3The thickness is 0.2-3 μm; the concentration of the n + + layer is greater than 1E19cm-3And the thickness is more than 0.2 mu m.
3. The method of claim 1, wherein the first mask layer in step 2) is SiO (silicon oxide semiconductor) and the SiC double trench MOSFET device is integrated with the schottky diode2The thickness is 2-4 μm, the depth of the source and gate trenches is greater than the sum of the thicknesses of the n + + layer and the p base region and is 1-4 μm; the width of the gate trench is 0.5-2 μm, the width of the source trench is 2.5-10 μm, and SiO is used2The selectivity ratio of mask etching SiC is greater than 3.
4. The method of claim 1, wherein the concentration of the doped region in step 3) is greater than 1E18cm-3Surface concentration greater than 1E19cm-3And the depth is more than 0.35 mu m.
5. According to claimThe method for manufacturing the SiC double trench MOSFET device of the integrated schottky diode of claim 1, wherein the p + doping concentration formed at the bottom of the gate trench in the step 4) is greater than 1E18cm-3Depth greater than 0.35 μm; the thickness of the graphite layer is 10-100 nm; the annealing temperature of the high-temperature activation annealing is more than 1600 ℃ and the time is more than 3 minutes.
6. The method of claim 1, wherein the thermal oxidation of the SiO grown in step 5) is used to form a Schottky diode-integrated SiC double trench MOSFET device2The thickness is 10-100 nm; the temperature of thermal oxidation is 1200-1500 ℃, and the thermal oxidation is carried out at O2And (3) performing in an atmosphere.
7. The method of claim 1 wherein the isolation passivation layer in step 6) is deposited SiO using CVD methods2Or a layer of SiOxNy with a thickness of more than 0.5 μm; the annealing temperature of the rapid thermal annealing is between 900 and 1100 ℃, and the time is between 1 minute and 15 minutes; the ohmic contact metal of the source and the drain is Ni or Ti/Ni.
8. The method of manufacturing the schottky diode-integrated SiC double trench MOSFET device of claim 1, wherein the schottky metal in step 7) is Ti, Mo, Ni or Pt; the annealing temperature of the thermal annealing is 400-600 ℃, and the time is 5-30 minutes.
9. The method of claim 1, wherein the thick passivation layer in step 8) is SiO2、Si3N4Or a polyimide.
10. The method of claim 1, wherein a JFET is further provided between the n-drift layer and the p-base region in step 1)A layer of concentration of the JFET layer less than 1E18cm-3And the thickness of the p-type drift layer is equal to the distance from the p base region to the junction depth of the p + region under the gate trench.
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| PCT/CN2017/081004 WO2018161412A1 (en) | 2017-03-06 | 2017-04-19 | Sic dual-trench mosfet device having integrated schottky diode and preparation method therefor |
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