CN110190127A - A kind of silicon carbide MOSFET device with L-type masking layer structure - Google Patents
A kind of silicon carbide MOSFET device with L-type masking layer structure Download PDFInfo
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- CN110190127A CN110190127A CN201910458095.4A CN201910458095A CN110190127A CN 110190127 A CN110190127 A CN 110190127A CN 201910458095 A CN201910458095 A CN 201910458095A CN 110190127 A CN110190127 A CN 110190127A
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- 230000000873 masking effect Effects 0.000 title claims abstract description 91
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 title claims abstract description 32
- 229910010271 silicon carbide Inorganic materials 0.000 title claims abstract description 32
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000007514 turning Methods 0.000 claims abstract description 6
- 239000004020 conductor Substances 0.000 claims description 17
- 238000005516 engineering process Methods 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 239000010931 gold Substances 0.000 claims 1
- 229910052737 gold Inorganic materials 0.000 claims 1
- 238000002347 injection Methods 0.000 claims 1
- 239000007924 injection Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 238000010586 diagram Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 8
- 230000005684 electric field Effects 0.000 description 8
- 238000000034 method Methods 0.000 description 8
- -1 boron ion Chemical class 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 230000002829 reductive effect Effects 0.000 description 5
- 229910052796 boron Inorganic materials 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000002360 preparation method Methods 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 4
- 235000012239 silicon dioxide Nutrition 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 238000001816 cooling Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 229910003978 SiClx Inorganic materials 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 2
- 230000002776 aggregation Effects 0.000 description 2
- 238000005275 alloying Methods 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 239000002210 silicon-based material Substances 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 1
- 241000790917 Dioxys <bee> Species 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052799 carbon Inorganic materials 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000670 limiting effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000000704 physical effect Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Abstract
The present invention relates to a kind of silicon carbide MOSFET devices with L-type masking layer structure, including drain electrode, n-type doping substrate layer, N-type drift region and the p-type base area set gradually from bottom to up, wherein be provided with p-type source region and N-type source region on the p-type base area；The p-type base area is internally provided with slot grid structure, and the bottom of the slot grid structure extends to the inside of the N-type drift region, extends the upper surface of the p-type base area at the top of the slot grid structure；The corner of the slot grid structure bottom is provided with masking layer structure, the masking layer structure to the turning of the slot grid structure bottom in parcel-like, and the not following table face contact with the p-type base area；Active electrode is set in the p-type source region and the N-type source region；Gate electrode is provided on the slot grid structure.Silicon carbide MOSFET device of the invention is provided with masking layer structure in slot grid structure bottom, improves the breakdown voltage of device.
Description
Technical field
The invention belongs to microelectronics technologies, and in particular to a kind of silicon carbide MOSFET with L-type masking layer structure
Device.
Background technique
Wide bandgap semiconductor materials silicon carbide has biggish forbidden bandwidth, higher critical breakdown electric field, high heat conductance
With desirable physicals and the chemical characteristic such as high electronics saturation drift velocity, it is suitble to production high temperature, high pressure, high-power and Flouride-resistani acid phesphatase half
Conductor device.In field of power electronics, power metal oxide semiconductor field-effect transistor (MOSFET, Metal-
Oxide-Semiconductor-Field-Effect-Transistor it) is introduced extensively, it has gate driving letter
Singly, the features such as switch time is short.
Slot grid structure MOSFET is a kind of highly efficient power switching device of the new development after MOSFET, it is using groove-shaped
Gate structure field-effect tube not only inherits metal-oxide-semiconductor field effect transistor input impedance height (>=108Ω), small (0.1 left side μ A of driving current
It is right) the advantages of, also there are the good characteristics such as high pressure resistant, operating current is big, output power is high, transconductance linearity is good, switching speed is fast.
Since it rolls into one electron tube and the advantages of power transistor, in Switching Power Supply, inverter, voltage amplifier, function
It is widely applied in the circuits such as rate amplifier.Therefore high-breakdown-voltage, high current, low on-resistance be MOSFET element the most
Crucial index.
Currently, having been able to reach higher pressure-resistant water by design in traditional slot grid structure MOSFET element
It is flat, but in practical applications, the gate oxide corner electric field concentration in slot grid structure MOSFET element leads to gate dielectric layer
Breakdown, so that device seriously affects the forward blocking characteristic of device lower than puncturing under breakdown voltage rating.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the present invention provides a kind of with L-type masking layer structure
Silicon carbide MOSFET device.The technical problem to be solved in the present invention is achieved through the following technical solutions:
The present invention provides a kind of silicon carbide MOSFET devices with L-type masking layer structure, including from bottom to up successively
Drain electrode, n-type doping substrate layer, N-type drift region and the p-type base area of setting, wherein
P-type source region and N-type source region are provided on the p-type base area；
The p-type base area is internally provided with slot grid structure, and the bottom of the slot grid structure extends to the N-type drift region
Inside, extend the upper surface of the p-type base area at the top of the slot grid structure；
The corner of the slot grid structure bottom is provided with masking layer structure, and the masking layer structure is to the slot grid structure
The turning of bottom is in parcel-like, and the not following table face contact with the p-type base area；
Active electrode is set in the p-type source region and the N-type source region；
Gate electrode is provided on the slot grid structure.
In one embodiment of the invention, two p-type source regions are in the shape of a rod, are located on the p-type base area
The both ends on surface；
Two N-type source regions are in the shape of a rod, be located at the inside of two p-type source regions and with described in respective side
P-type source region is in contact；
The slot grid structure includes gate medium groove and the conductive material positioned at the gate medium trench interiors, wherein institute
Gate medium groove is stated to stretch out the part of p-type base area upper surface while contacting with the side of two N-type source regions.
In one embodiment of the invention, the p-type source region is annular in shape, and around the four of p-type base area upper surface
Week；
The N-type source region is annular in shape, is located at the cricoid inside of p-type source region；
And the lateral surface of the N-type source region is in contact with the medial surface of the p-type source region；
The slot grid structure includes gate medium groove and the conductive material positioned at the gate medium trench interiors, wherein institute
State gate medium groove and stretch out the part of p-type base area upper surface and be located at the center of N-type source region upper surface, and with the N
The medial surface of type source region is in contact.
In one embodiment of the invention, the upper surface of the conductive material is arranged in the gate electrode.
In one embodiment of the invention, the masking layer structure includes the first masking layer and the second masking layer, described
First masking layer and second masking layer are symmetricly set on the Liang Ge corner of the slot grid structure bottom, and described first covers
Layer is covered in └ type, and second masking layer is in ┘ type；
The inner surface of first masking layer is contacted with the corner of the gate medium groove；
The inner surface of second masking layer is contacted with another corner of the gate medium groove.
In one embodiment of the invention, first masking layer and the length a of second masking layer two sides are equal
It is 0.5-1.5 μm.
In one embodiment of the invention, the masking layer structure connects the source electrode by metal wire.
In one embodiment of the invention, the masking layer structure is p-type doping, and doping concentration is 1 × 1018-5×
1018cm-3。
In one embodiment of the invention, the masking layer structure is formed by ion implantation technology.
Compared with prior art, the beneficial effects of the present invention are:
1, the silicon carbide MOSFET device with L-type masking layer structure of the invention, by increasing L in slot grid structure bottom
Type masking layer structure, in the case where not increasing MOSFET element cell density, the electric field for reducing slot grid structure corner is poly-
Collection, improves the breakdown voltage of MOSFET element.
2, the silicon carbide MOSFET device with L-type masking layer structure of the invention, by increasing L in slot grid structure bottom
Type masking layer structure, reduces the capacitor between gate electrode and drain electrode, increases the switching speed of MOSFET element, reduces
Energy loss reduces the cooling requirements under the high-frequency work of MOSFET element.
The above description is only an overview of the technical scheme of the present invention, in order to better understand the technical means of the present invention,
And it can be implemented in accordance with the contents of the specification, and in order to allow above and other objects, features and advantages of the invention can
It is clearer and more comprehensible, it is special below to lift preferred embodiment, and cooperate attached drawing, detailed description are as follows.
Detailed description of the invention
Fig. 1 is a kind of structure of silicon carbide MOSFET device with L-type masking layer structure provided in an embodiment of the present invention
Schematic diagram；
Fig. 2 is a kind of part of silicon carbide MOSFET device with L-type masking layer structure provided in an embodiment of the present invention
Size marking schematic diagram；
Fig. 3 is that a kind of silicon carbide MOSFET device with L-type masking layer structure provided in an embodiment of the present invention removes electricity
The top view of pole；
Fig. 4 is that another silicon carbide MOSFET device with L-type masking layer structure provided in an embodiment of the present invention removes
The top view of electrode；
Fig. 5-Figure 12 is a kind of silicon carbide MOSFET device system with L-type masking layer structure provided in an embodiment of the present invention
The structural schematic diagram of the intermediate of Preparation Method step, in which:
Fig. 5 is the structural schematic diagram of n-type doping substrate layer and N-type drift region；
Fig. 6 is to form the structural schematic diagram of masking layer in N-type drift region；
Fig. 7 is the structural schematic diagram buried after masking layer；
Fig. 8 is the structural schematic diagram to form p-type base area；
Fig. 9 is the structural schematic diagram to form p-type source region and N-type source region；
Figure 10 is the structural schematic diagram to form groove；
Figure 11 is the structural schematic diagram to form slot grid structure；
Figure 12 is the structural schematic diagram to form electrode metal.
Description of symbols
1- drain electrode；2-N type doped substrate layer；3-N type drift region；31- the first N-type drift layer；The drift of the second N-type of 32-
Layer；4-P type base area；5-P type source region；6-N type source region；7- slot grid structure；8- masking layer structure；9- source electrode；10- gate electrode；
11- gate medium groove；12- conductive material；The first masking layer of 13-；The second masking layer of 14-.
Specific embodiment
In order to which the present invention is further explained to reach the technical means and efficacy that predetermined goal of the invention is taken, below in conjunction with
The drawings and the specific embodiments, to a kind of silicon carbide MOSFET device with L-type masking layer structure proposed according to the present invention
It is described in detail.
For the present invention aforementioned and other technology contents, feature and effect, in the specific embodiment party of following cooperation attached drawing
Formula can be clearly presented in being described in detail.By the explanation of specific embodiment, predetermined purpose institute can be reached to the present invention
The technical means and efficacy taken more understand deeply and specifically, however appended attached drawing be only to provide reference and description it
With, not be used to technical solution of the present invention is limited.
Referring to Figure 1, Fig. 1 is a kind of silicon carbide MOSFET with L-type masking layer structure provided in an embodiment of the present invention
The structural schematic diagram of device, as shown, the silicon carbide MOSFET device with L-type masking layer structure of the present embodiment includes,
Drain electrode 1, n-type doping substrate layer 2, N-type drift region 3 and the p-type base area 4 set gradually from bottom to up.Specifically, drain electrode 1
For Ti/Ni/Al alloying metal layer, with a thickness of 2-5 μm.N-type doping substrate layer 2 is as heavy doping substrate for reducing break-over of device
Resistance simultaneously transmits electric current, and with a thickness of 2-5 μm, doping concentration is 5 × 1018-1×1020cm-3.N-type drift region 3 is used as and is lightly doped
Area is used to prevent device breakdown reversely by the voltage for undertaking drain electrode 1 under work, with a thickness of 8-10 μm, doping concentration
It is 1 × 1015-1×1016cm-3, because doping concentration is excessively high, device on-resistance reduces, and device electric breakdown strength can reduce.P-type
Base area 4, which is used as, is lightly doped p-type source region for being isolated drain electrode 1 with source electrode 9 and forming conductive ditch when gate electrode 10 is opened
Road, with a thickness of 0.3-3 μm, the excessive length that will increase device conducts channel of thickness, so that conducting resistance increases, doping concentration is
1×1017-3×1017cm-3, because doping concentration is excessively high, the threshold voltage of device is higher, and grid charging rate reduces, to device gate
Electrode drive circuit requires to increase, and doping concentration is too low, and device threshold voltage is relatively low, is easy to open by mistake and open, so comprehensively considering choosing
Selecting doping concentration is 1 × 1017-3×1017cm-3。
Further, p-type source region 5 and N-type source region 6 are provided on p-type base area 4, p-type base area 4 is internally provided with slot grid
Structure 7, the bottom of slot grid structure 7 extend to the inside of N-type drift region 3, and the upper of p-type base area 4 is extended at the top of slot grid structure 7
Active electrode 9 is set in surface, p-type source region 5 and N-type source region 6, is provided with gate electrode 10 on slot grid structure 7.
Incorporated by reference to referring to figs. 2 and 3, as shown, two p-type source regions 5 are in the shape of a rod, it is located at table on p-type base area 4
The both ends in face, two N-type source regions 6 are in the shape of a rod, are located at the inside of two p-type source regions 5 and the p-type source region phase with respective side
Contact.Slot grid structure 7 includes gate medium groove 11 and the conductive material 12 inside gate medium groove 11, gate medium groove 11
The part for stretching out 4 upper surface of p-type base area is contacted with the side of two N-type source regions 6 simultaneously.Further, source electrode 9 is arranged in P
In type source region 5 and N-type source region 6, the upper surface of conductive material 12 is arranged in gate electrode 10.In the present embodiment, p-type source region 5 is used
In connection p-type base area 4 and source electrode 9, length b is 0.25-1 μm, and thickness c is 0.25-1 μm, and doping concentration is 1 × 1019-1
×1020cm-3.N-type source region 6 is used for electric current collection and conducts to source electrode 9, and length d is 0.25-1 μm, and thickness e is
0.25-1 μm, doping concentration is 1 × 1019-1×1020cm-3.Gate medium groove 11 is silicon dioxide layer groove, is used to form recessed
The conducting channel of groove profile, thickness f are 50-60nm, and the silicon dioxide layer passes through dry-oxygen oxidation technique and wet-oxygen oxidation technique
It is prepared.Conductive material 12 is filled in the inside of gate medium groove 11 by depositing technics, for control device unlatching with
Shutdown, material are the polycrystalline silicon material of boron ion doping, and doping concentration is 1 × 1019-1×1020cm-3.Gate electrode 10 is Al
Metal layer, with a thickness of 2-5 μm.
Incorporated by reference to referring to fig. 2 and Fig. 4, as shown, p-type source region 5 is annular in shape, and around the four of 4 upper surface of p-type base area
In week, N-type source region 6 is annular in shape, is located at the cricoid inside of p-type source region 5, and the medial surface of the lateral surface of N-type source region 6 and p-type source region 5
It is in contact.Slot grid structure 7 includes gate medium groove 11 and the conductive material 12 inside gate medium groove 11, wherein grid are situated between
The part that matter groove 11 stretches out 4 upper surface of p-type base area is located at the center of 6 upper surface of N-type source region, and the medial surface with N-type source region 6
It is in contact.Further, source electrode 9 is arranged in p-type source region 5 and N-type source region 6, and conductive material 12 is arranged in gate electrode 10
Upper surface.In the present embodiment, p-type source region 5 is 0.25-1 μm for connecting p-type base area 4 and source electrode 9, length b, thickness c
It is 0.25-1 μm, doping concentration is 1 × 1019-1×1020cm-3.N-type source region 6 is used for electric current collection and conducts to source electrode 9,
Its length d is 0.25-1 μm, and thickness e is 0.25-1 μm, and doping concentration is 1 × 1019-1×1020cm-3.Gate medium groove 11 is
Silicon dioxide layer groove is used to form the conducting channel of groove type, and thickness f is 50-60nm, and the silicon dioxide layer passes through dry
Oxygen oxidation technology is prepared with wet-oxygen oxidation technique.Conductive material 12 is filled in the interior of gate medium groove 11 by depositing technics
Portion, for opening and shutting off for control device, material is the polycrystalline silicon material of boron ion doping, and doping concentration is 1 × 1019-1
×1020cm-3.Gate electrode 10 is Al metal layer, with a thickness of 2-5 μm.
Further, the corner of 7 bottom of slot grid structure is provided with masking layer structure 8, and masking layer structure 8 is to slot grid knot
The turning of 7 bottom of structure is in parcel-like, and the not following table face contact with p-type base area 4.Specifically, masking layer structure 8 is covered including first
Layer 13 and the second masking layer 14 are covered, the first masking layer 13 and the second masking layer 14 are symmetricly set on two of 7 bottom of slot grid structure
Corner, and the first masking layer 13 is in └ type, the second masking layer 14 is in ┘ type.The inner surface and gate medium ditch of first masking layer 13
The corner of slot 11 contacts, and the inner surface of the second masking layer 14 is contacted with another corner of gate medium groove 11.
In the present embodiment, masking layer structure 8 is p-type doping, and doping concentration is 1 × 1018-5×1018cm-3, masking layer
Structure 8 is formed by ion implantation technology, wherein the first masking layer 13 and the length a of 14 two sides of the second masking layer are
0.5-1.5μm.Since in the semiconductor device, the corner of gate medium groove 11 is the place that electric field is concentrated, have biggish
Pressure drop will lead to punch-through when electric field strength is more than 4mV/cm in the semiconductor devices course of work.?
Masking layer structure 8 is arranged at the bottom corners of gate medium groove 11 to play a protective role to gate medium groove 11, due to masking layer
Structure 8 is P-doped zone, therefore forms PN junction with N-type drift region 3, thus it is possible to vary the field distribution of device inside reduces grid
The electric field of 11 corner of medium groove, protects the turning of gate medium groove 11, improves the breakdown voltage of semiconductor devices.
In the present embodiment, when the silicon carbide MOSFET device is applied in high frequency, interior metal line can be passed through
Masking layer structure 8 is connected with source electrode 9, when the MOSFET element is applied in open type switch, masking layer structure 8 is not
Connection electrode.
The silicon carbide MOSFET device with L-type masking layer structure of the present embodiment, by being turned in the bottom of slot grid structure 7
Masking layer structure 8 is set at angle, the corner of slot grid structure 7 is protected, so that not increasing MOSFET element cellular face
In the case where product, the electric field aggregation at 7 bottom corners of slot grid structure is reduced, the breakdown voltage of MOSFET element is improved.And
And masking layer structure 8, the capacitor between gate electrode and drain electrode is reduced, the switching speed of MOSFET element is increased, is reduced
Energy loss, reduces the cooling requirements under the high-frequency work of MOSFET element.
Fig. 5-Figure 12 is referred to, Fig. 5-Figure 12 is a kind of carbon with L-type masking layer structure provided in an embodiment of the present invention
The structural schematic diagram of the intermediate of the specific preparation method step of SiClx MOSFET element.The preparation of the MOSFET element of the present embodiment
Method, specifically includes the following steps:
Epitaxial growth is carried out on substrate, specifically, refers to Fig. 5, selects silicon carbide substrates as n-type doping substrate layer
2, in the first N-type drift layer 31 that 7-8 μm of silicon carbide substrates upper surface epitaxial growth of Nitrogen ion adulterates, doping concentration is
1×1015-1×1016cm-3。
It forms masking layer and specifically refers to Fig. 6, it is recessed first to etch formation two in the upper surface of the first N-type drift layer 31
Slot, then two rectangular p-type masking layers are formed by ion implanting, the side length of the rectangular p-type masking layer is 0.5-1.5 μ
M, doping concentration are 1 × 1018-5×1018cm-3。
It buries the p-type masking layer and specifically refers to Fig. 7, in the upper surface epitaxial growth of the first N-type drift layer 31
Second N-type drift layer 32 of 1-2 μm of Nitrogen ion doping, doping concentration are 1 × 1015-1×1016cm-3, the first N-type drift layer
31 and second N-type drift layer 32 form N-type drift region 3.
It forms p-type base area and specifically refers to Fig. 8, be epitaxially formed p-type base area 4 in the upper surface of N-type drift region 3, it is thick
Degree is 0.3-3 μm, and doping concentration is 1 × 1017-3×1017cm-3。
It forms p-type source region and N-type source region specifically refers to Fig. 9, pass through ion implanting in the upper surface of p-type base area 4
Mode form p-type source region 5 and N-type source region 6, the doping concentration of p-type source region 5 is 1 × 1019-1×1020cm-3, N-type source region 6
Doping concentration is 1 × 1019-1×1020cm-3, p-type source region 5 and N-type source region 6 with a thickness of 0.25-1 μm.
Groove is formed, specifically, referring to Figure 10, groove is formed by etching, the groove runs through N-type source region 6 and p-type
Base area 4, and extend in N-type drift region 3, and two turnings of the bottom of the groove are located at described two rectangular P
Inside type masking layer, the length g of the groove is 1-3 μm, and depth h is 2-3 μm, and described two rectangular p-type masking layers are by carving
The first masking layer 13 and the second masking layer 14 are formed after erosion.
Slot grid structure is formed, specifically, referring to Figure 11, pass through dry-oxygen oxidation technique and wet-oxygen oxidation technique forms dioxy
SiClx gate medium groove 11, conducting channel of the gate medium groove 11 as groove type, with a thickness of 50-60nm.In gate medium ditch
The polysilicon of the deposited inside boron ion doping of slot 11, as conductive material 12, the doping of the polysilicon of the boron ion doping
Concentration is 1 × 1019-1×1020cm-3, gate medium groove 11 and conductive material 12 form slot grid structure 7.
Electrode metal is formed, specifically, referring to Figure 12, in the upper surface deposited metal of conductive material 12, as grid
Electrode 10, in the upper surface deposited metal of p-type source region 5 and N-type source region 6, as source electrode 9, in n-type doping substrate layer 2
Lower surface deposited metal, as drain electrode 1.Source electrode 9 and drain electrode 1 are Ti/Ni/Al alloying metal layer, and gate electrode 10 is
Al metal layer, thickness are 2-5 μm.
The silicon carbide MOSFET device with L-type masking layer structure that preparation method through this embodiment obtains, in slot
Masking layer structure 8 is set at the bottom corners of grid structure 7, the corner of slot grid structure 7 is protected, so that not increasing
In the case where MOSFET element cell density, the electric field aggregation at 7 bottom corners of slot grid structure is reduced, MOSFET device is improved
The breakdown voltage of part.And masking layer structure 8, the capacitor between gate electrode and drain electrode is reduced, MOSFET element is increased
Switching speed, reduce energy loss, reduce the cooling requirements under the high-frequency work of MOSFET element.
In the description of the present invention, it is to be understood that, term " center ", " longitudinal direction ", " transverse direction ", " length ", " width ",
" thickness ", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outside", " up time
The orientation or positional relationship of the instructions such as needle ", " counterclockwise " is to be based on the orientation or positional relationship shown in the drawings, and is merely for convenience of
The description present invention and simplified description, rather than the device or element of indication or suggestion meaning must have a particular orientation, with spy
Fixed orientation construction and operation, therefore be not considered as limiting the invention.
In addition, term " first ", " second " are used for descriptive purposes only and cannot be understood as indicating or suggesting relative importance
Or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be expressed or
Implicitly include one or more of the features.In the description of the present invention, the meaning of " plurality " is two or more,
Unless otherwise specifically defined.
In the present invention unless specifically defined or limited otherwise, fisrt feature second feature "upper" or "lower"
It may include that the first and second features directly contact, also may include that the first and second features are not direct contacts but pass through it
Between other characterisation contact.Moreover, fisrt feature includes the first spy above the second feature " above ", " above " and " above "
Sign is right above second feature and oblique upper, or is merely representative of first feature horizontal height higher than second feature.Fisrt feature exists
Second feature " under ", " lower section " and " following " include that fisrt feature is directly below and diagonally below the second feature, or is merely representative of
First feature horizontal height is less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
What can be combined in any suitable manner in one or more embodiment or examples.In addition, those skilled in the art can say this
Different embodiments or examples described in bright book are engaged and are combined.
Although the application is described in conjunction with each embodiment herein, however, implementing the application claimed
In the process, those skilled in the art are by checking the attached drawing, disclosure and the appended claims, it will be appreciated that and it is real
Other variations of the existing open embodiment.In the claims, " comprising " (comprising) word is not excluded for other compositions
Part or step, "a" or "an" are not excluded for multiple situations.Claim may be implemented in single processor or other units
In several functions enumerating.Mutually different has been recited in mutually different dependent certain measures, it is not intended that these are arranged
It applies to combine and generates good effect.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that
Specific implementation of the invention is only limited to these instructions.For those of ordinary skill in the art to which the present invention belongs, exist
Under the premise of not departing from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to of the invention
Protection scope.
Claims (9)
1. a kind of silicon carbide MOSFET device with L-type masking layer structure, which is characterized in that including setting gradually from bottom to up
Drain electrode (1), n-type doping substrate layer (2), N-type drift region (3) and p-type base area (4), wherein
P-type source region (5) and N-type source region (6) are provided on the p-type base area (4)；
The p-type base area (4) is internally provided with slot grid structure (7), and the bottom of the slot grid structure (7) extends to the N-type
The inside of drift region (3) extends the upper surface of the p-type base area (4) at the top of the slot grid structure (7)；
The corner of slot grid structure (7) bottom is provided with masking layer structure (8), and the masking layer structure (8) is to the slot
The turning of grid structure (7) bottom is in parcel-like, and the not following table face contact with the p-type base area (4)；
Active electrode (9) are set on the p-type source region (5) and the N-type source region (6)；
Gate electrode (10) are provided on the slot grid structure (7).
2. silicon carbide MOSFET device according to claim 1, feature exist, two p-type source regions (5) are in bar
Shape is located at the both ends of p-type base area (4) upper surface；
Two N-type source regions (6) are in the shape of a rod, are located at the inside of two p-type source regions (5) and the institute with respective side
P-type source region (5) is stated to be in contact；
The slot grid structure (7) includes gate medium groove (11) and the conductive material for being located at gate medium groove (11) inside
(12), wherein the gate medium groove (11) stretch out the part of p-type base area (4) upper surface simultaneously with two N-type sources
The side in area (6) contacts.
3. silicon carbide MOSFET device according to claim 1, feature exist, the p-type source region (5) annularly, and ring
Surrounding around p-type base area (4) upper surface；
The N-type source region (6) annularly, is located at the cricoid inside of the p-type source region (5)；
And the lateral surface of the N-type source region (6) is in contact with the medial surface of the p-type source region (5)；
The slot grid structure (7) includes gate medium groove (11) and the conductive material for being located at gate medium groove (11) inside
(12), wherein the part that the gate medium groove (11) stretches out p-type base area (4) upper surface is located at the N-type source region (6)
The center of upper surface, and be in contact with the medial surface of the N-type source region (6).
4. silicon carbide MOSFET device according to claim 2 or 3, feature exist, the gate electrode (10) is arranged in institute
State the upper surface of conductive material (12).
5. silicon carbide MOSFET device according to claim 2 or 3, which is characterized in that
The masking layer structure (8) include the first masking layer (13) and the second masking layer (14), first masking layer (13) and
Second masking layer (14) is symmetricly set on the Liang Ge corner of the slot grid structure (7) bottom, and first masking layer
It (13) is in └ type, second masking layer (14) is in ┘ type；
The inner surface of first masking layer (13) is contacted with the corner of the gate medium groove (11)；
The inner surface of second masking layer (14) is contacted with another corner of the gate medium groove (11).
6. silicon carbide MOSFET device according to claim 5, which is characterized in that first masking layer (13) with it is described
The length a of the second masking layer (14) two sides is 0.5-1.5 μm.
7. silicon carbide MOSFET device according to claim 1, which is characterized in that the masking layer structure (8) passes through gold
Belong to line and connects the source electrode (9).
8. silicon carbide MOSFET device according to claim 1, which is characterized in that the masking layer structure (8) is mixed for p-type
Miscellaneous, doping concentration is 1 × 1018-5×1018cm-3。
9. silicon carbide MOSFET device according to claim 1, which is characterized in that the masking layer structure (8) by from
Sub- injection technology is formed.
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