CN116207156A - Trench MOSFET and manufacturing method thereof - Google Patents

Trench MOSFET and manufacturing method thereof Download PDF

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Publication number
CN116207156A
CN116207156A CN202310436210.4A CN202310436210A CN116207156A CN 116207156 A CN116207156 A CN 116207156A CN 202310436210 A CN202310436210 A CN 202310436210A CN 116207156 A CN116207156 A CN 116207156A
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Prior art keywords
gate oxide
layer
oxide layer
trench structure
doping type
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龚雪芹
张彦飞
刘梦新
温霄霞
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Beijing Zhongke Xinweite Science & Technology Development Co ltd
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Beijing Zhongke Xinweite Science & Technology Development Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
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    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
    • Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
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Abstract

The application discloses a trench MOSFET and a manufacturing method thereof, and relates to the technical field of semiconductors. The trench MOSFET includes: a substrate of a first doping type, on a first surface of which an epitaxial layer of the first doping type is arranged; a well region of a second doping type disposed within the epitaxial layer; the bottom gate oxide layer of the gate trench structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer which is in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side of the first bottom gate oxide layer far away from the first surface and is not in contact with the side gate oxide layer of the gate trench structure; a first doped region of a second doping type disposed within the epitaxial layer and in contact with a bottom corner of the gate trench structure. According to the embodiment of the application, the voltage withstand capability of the trench MOSFET device can be improved, the gate-drain capacitance can be reduced, and the switching loss is reduced.

Description

Trench MOSFET and manufacturing method thereof
Technical Field
The application belongs to the field of semiconductor devices, and particularly relates to a trench MOSFET and a manufacturing method thereof.
Background
In the field of power semiconductors, trench Metal-Oxide-semiconductor field effect MOSFETs (MOSFETs) can realize low resistance and high current due to small cell size, and rapidly develop in the low voltage field.
In the related art, the bottom corner of the gate trench structure is at a right angle, so a high electric field is easily generated at the bottom corner of the gate trench structure, and then the gate oxide layer in the gate trench structure is easily broken down, thereby causing the function failure of the trench MOSFET device, that is, the breakdown voltage capability of the trench MOSFET device is poor.
Disclosure of Invention
The embodiment of the application provides a trench MOSFET and a manufacturing method thereof, which can improve the voltage resistance of a trench MOSFET device, reduce the gate-drain capacitance and reduce the switching loss.
In a first aspect, an embodiment of the present application provides a trench MOSFET, including:
a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is provided;
a well region of a second doping type disposed within the epitaxial layer;
the bottom gate oxide layer of the gate trench structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer which is in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side of the first bottom gate oxide layer far away from the first surface and is not in contact with the side gate oxide layer of the gate trench structure;
a first doped region of a second doping type disposed within the epitaxial layer and in contact with a bottom corner of the gate trench structure;
the first doping type is opposite to the second doping type.
In some alternative embodiments, the bottom gate oxide layer has a "convex" cross-section in a direction perpendicular to the first surface.
In some alternative embodiments, the trench MOSFET further comprises:
the second doping region is arranged on the surface of the well region away from the first surface and is in contact with the grid groove structure;
and a third doped region of the second doping type disposed within the well region and spaced apart from the gate trench structure.
In some alternative embodiments, the trench MOSFET further comprises:
and the source metal regions are arranged in contact with the two adjacent second doped regions and the two adjacent third doped regions.
In some alternative embodiments, the substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.
In a second aspect, an embodiment of the present application provides a method for manufacturing a trench MOSFET, including:
providing a substrate of a first doping type, wherein the substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface;
forming a well region of a second doping type on a surface of the epitaxial layer away from the first surface;
and forming a gate trench structure in the well region, and forming a first doped region of a second doping type in contact with the bottom corner of the gate trench structure in the epitaxial layer, wherein the bottom gate oxide of the gate trench structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side of the first bottom gate oxide layer away from the first surface and is not in contact with the side gate oxide layer of the gate trench structure.
In some alternative embodiments, forming a gate trench structure within a well region and forming a first doped region of a second doping type within an epitaxial layer in contact with a bottom corner of the gate trench structure, comprising:
forming a first transition layer on a surface of the well region away from the first surface;
forming a first hard mask layer on a surface of the first transition layer away from the first surface;
forming a trench structure in the well region;
forming a second transition layer on the surface of the groove structure;
forming a second hard mask layer on the surface of the second transition layer far away from the first surface and the surface of the first hard mask layer far away from the first surface respectively;
etching the second hard mask layer at the bottom of the groove structure;
forming a second bottom gate oxide layer in the trench structure;
etching all the first hard mask layers and all the second hard mask layers;
forming a first doped region of a second doping type in the epitaxial layer in contact with the bottom corner of the trench structure;
removing all the first transition layers and all the second transition layers, and forming a first bottom gate oxide layer and a side gate oxide layer in the trench structure;
a gate is formed within the trench structure.
In some alternative embodiments, the bottom gate oxide layer has a "convex" cross-section in a direction perpendicular to the first surface.
In some alternative embodiments, after forming the gate within the trench structure, the method further comprises:
and forming a source metal region which is connected with two adjacent second doped regions and is contacted with the third doped region.
In some alternative embodiments, the length of the well region is less than the length of the gate trench structure in a direction perpendicular to the first surface.
According to the trench MOSFET and the manufacturing method thereof, the trench MOSFET comprises a well region, a gate trench structure and a first doped region which are arranged in an epitaxial layer. On the one hand, the bottom corner of the gate trench structure is contacted with the first doped region with the second doped type, when the trench MOSFET device is in a reverse bias state, the first doped region with the second doped type can improve the problem of electric field concentration at the bottom corner of the gate trench structure, so that the reliability of the gate oxide layer is improved, and the voltage withstand capability of the trench MOSFET device is improved. On the other hand, the bottom oxide layer of the gate trench structure may include a first bottom gate oxide layer and a second bottom gate oxide layer disposed in contact with the first bottom gate oxide layer, where the second bottom gate oxide layer is disposed on a side of the first bottom gate oxide layer away from the first surface, that is to say, the thickness of a portion of the first bottom gate oxide layer is increased, so that the gate-drain capacitance (i.e., the capacitance between the gate and the drain) can be effectively reduced, and the switching loss is reduced.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described, and it is possible for a person skilled in the art to obtain other drawings according to these drawings without inventive effort.
Fig. 1 is a schematic structural diagram of a trench MOSFET according to an embodiment of the present application;
fig. 2 is a schematic flow chart of a method for manufacturing a trench MOSFET according to an embodiment of the present disclosure;
FIG. 3 is a schematic cross-sectional structure of a substrate provided in an embodiment of the present application;
FIG. 4 is a schematic cross-sectional view of a well region according to an embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view of a first transition layer according to an embodiment of the present disclosure;
FIG. 6 is a schematic cross-sectional structure of forming a first hard mask layer according to an embodiment of the present application;
FIG. 7 is a schematic cross-sectional view of a trench structure according to an embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view of a second transition layer formed according to an embodiment of the present disclosure;
FIG. 9 is a schematic cross-sectional structure of forming a second hard mask layer according to an embodiment of the present application;
fig. 10 is a schematic cross-sectional structure of forming a second bottom gate oxide according to an embodiment of the present disclosure;
FIG. 11 is a schematic cross-sectional view of forming a first doped region according to an embodiment of the present application;
FIG. 12 is a schematic cross-sectional view of forming an oxide layer, a first bottom gate oxide layer, and a side gate oxide layer according to an embodiment of the present application;
fig. 13 is a schematic cross-sectional view of forming a gate trench structure and a second doped region according to an embodiment of the present disclosure;
FIG. 14 is a schematic cross-sectional view of forming a third doped region according to an embodiment of the present disclosure;
fig. 15 is a schematic cross-sectional structure of forming a source metal region provided in the present application.
Reference numerals in the drawings illustrate:
1. a substrate; 11. a first surface; 12. a second surface;
2. an epitaxial layer; 21. an oxide layer; 22. a contact hole;
3. a well region;
4. a gate trench structure; 41. a bottom gate oxide layer; 411. a first bottom gate oxide layer; 412. a second bottom gate oxide layer; 42. a side gate oxide layer; 43. a gate; 44. an isolation dielectric layer; 45. a trench structure; 46. a first transition layer; 47. a first hard mask layer; 48. a second transition layer; 49. a second hard mask layer;
5. a first doped region;
6. a second doped region;
7. a third doped region;
8. a source metal layer;
9. and a drain structure.
In the drawings, like parts are designated with like reference numerals. The figures are not drawn to scale.
Detailed Description
Features and exemplary embodiments of various aspects of the present application are described in detail below to make the objects, technical solutions and advantages of the present application more apparent, and to further describe the present application in conjunction with the accompanying drawings and the detailed embodiments. It should be understood that the specific embodiments described herein are intended to be illustrative of the application and are not intended to be limiting. It will be apparent to one skilled in the art that the present application may be practiced without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of the present application by showing examples of the present application.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The inventors have found that the depth of the P-type well region is increased (i.e., the deep P-type well region is formed) so that the depth of the P-type well region is greater than the depth of the gate trench structure, and the P-type well region can wrap around the bottom corner of the gate trench structure, although the electric field strength at the bottom corner of the gate trench structure can be reduced, thereby effectively protecting the bottom corner of the gate trench structure. However, the formation position of the deep P-type well region is not easy to control, and a junction field effect MOSFET (Junction Field Effect Transistor, JFET) is formed, so that the resistance of the MOSFET device is increased.
In addition, the related art also reduces the electric field strength at the corners of the gate trench structure by introducing a plurality of P-type shielding regions of different doping concentrations at the bottom of the gate trench structure. However, the implementation process of implanting multiple P-type shield regions of different doping concentrations is difficult and increases the resistance of the MOSFET device.
In order to solve the problem of poor voltage withstand capability of a trench MOSFET device in the prior art, embodiments of the present application provide a trench MOSFET and a manufacturing method thereof. The trench MOSFET provided in the embodiments of the present application will be first described below.
Fig. 1 shows a schematic structural diagram of a trench MOSFET according to an embodiment of the present application.
As shown in fig. 1, the trench MOSFET provided in the embodiment of the present application may include:
the substrate 1 of the first doping type, the substrate 1 comprising a first surface 11, the first surface 11 being provided with an epitaxial layer 2 of the first doping type.
The substrate 1 may be at least one of a silicon substrate, a silicon carbide substrate, a group III-V compound substrate, a germanium (SiGe) substrate, and an epi-substrate, which is not limited herein.
In some alternative embodiments, the substrate 1 may further comprise a second surface 12 opposite the first surface 11, the second surface 12 may be provided with the drain structure 9.
In this embodiment, the first doping type may be N-type.
The substrate 1 of the first doping type may be an N-type substrate 1 and the first surface 11 may be provided with an N-type epitaxial layer 2.
The resistivity of the epitaxial layer 2 can be selected according to the structure and breakdown voltage of the device, the resistivity of the epitaxial layer 2 corresponding to the device with the breakdown voltage of 100V-200V is 0.3 ohm cm-3 ohm cm, the thickness of the epitaxial layer 2 can be selected according to the breakdown voltage of the MOSFET device, and the higher the voltage is, the larger the thickness of the epitaxial layer 2 is.
A well region 3 of a second doping type is provided in the epitaxial layer 2.
In this embodiment, the well region 3 of the second doping type may be a P-type well region.
The cross section of the well region 3 may be rectangular in the direction perpendicular to the first surface 11, or may be in other regular patterns or irregular patterns, which are not limited herein.
The first doping type is opposite to the second doping type, which is understood to be one of N-type or P-type, and the second doping type is the other of N-type or P-type. Illustratively, where the first doping type is N-type, the second doping type may be P-type; in the case where the first doping type is P-type, the second doping type may be N-type.
The gate trench structure 4 disposed in the well region 3, the bottom gate oxide 41 of the gate trench structure 4 may include a first bottom gate oxide 411 and a second bottom gate oxide 412 disposed in contact with the first bottom gate oxide 411, the second bottom gate oxide 412 being disposed on a side of the first bottom gate oxide 411 away from the first surface 11 and not in contact with the side gate oxide 42 of the gate trench structure 4.
In this embodiment, the bottom oxide layer of the gate trench structure 4 may include a first bottom gate oxide layer 411 and a second bottom gate oxide layer 412 disposed in contact with the first bottom gate oxide layer 411, where the second bottom gate oxide layer 412 is disposed on a side of the first bottom gate oxide layer 411 away from the first surface 11, that is to say, the thickness of a portion of the first bottom gate oxide layer 411 is increased, so that the gate-drain capacitance (i.e. the coupling capacitance between the gate 43 and the drain) can be effectively reduced, and the switching loss is reduced.
The gate trench structure 4 may include a bottom gate oxide 41, a side gate oxide 42, and a gate 43. The gate 43 is disposed in an area surrounded by the bottom gate oxide 41, the side gate oxide 42 and the isolation dielectric 44, and the gate 43 is disposed in contact with the bottom gate oxide 41, the side gate oxide 42 and the isolation dielectric 44. The isolation dielectric layer 44 is used to isolate the gate electrode 43 from the source metal layer 8.
The materials of the bottom gate oxide 41, the side gate oxide 42, and the isolation dielectric 44 may each include an oxide such as silicon oxide. The material of the gate 43 may include polysilicon.
In some alternative embodiments, the bottom gate oxide 41 may be "convex" in cross-section in a direction perpendicular to the first surface 11. That is, the thickness of the bottom gate oxide 41 in the middle portion is greater than that of the bottom gate oxide 41 in the two side portions, that is, the thickness of the first bottom gate oxide 411 is increased, so that the gate-drain capacitance (that is, the capacitance between the gate electrode 43 and the drain electrode) can be effectively reduced, and the switching loss can be reduced.
In other alternative embodiments, the cross section of the bottom gate oxide 41 may take other shapes in the direction perpendicular to the first surface 11, as long as the thickness of the bottom gate oxide 41 in the middle portion is ensured to be larger than that of the bottom gate oxide 41 in the two side portions.
A first doped region 5 of the second doping type is provided within the epitaxial layer 2 and in contact with the bottom corner of the gate trench structure 4.
In this embodiment, the bottom corner of the gate trench structure 4 is provided with the first doped region 5 of the second doping type in contact, on one hand, when the trench MOSFET device is in the reverse bias state, the first doped region 5 of the second doping type can improve the problem of electric field concentration at the bottom corner of the gate trench structure 4, thereby improving the reliability of the oxide layer of the gate 43, and further improving the voltage withstanding capability of the trench MOSFET device; on the other hand, a plurality of P-type shielding areas with different doping concentrations do not need to be injected, so that the implementation process difficulty of the MOSFET device and the resistance of the MOSFET device are reduced.
The first doped region 5 of the second doping type may be a first doped region 5 of a P-type.
The first doped regions 5 of P-type are disposed at two bottom corners of the same gate trench structure 4, and the cross section of the first doped regions 5 may be fan-shaped or may be other shapes in the direction perpendicular to the first surface 11, which is not limited herein.
It is noted that the first doped region 5 can wrap around at least part of the bottom corners of the gate trench structure 4. When the first doped region 5 can wrap around all bottom corners of the gate trench structure 4, the problem of electric field concentration at the bottom corners of the gate trench structure 4 can be better improved, so that the voltage-withstanding capability of the trench MOSFET device can be better improved.
In some alternative embodiments, the length of the well region 3 may be smaller than the length of the gate trench structure 4 in a direction perpendicular to the first surface 11.
In this embodiment, the problem of electric field concentration at the bottom corner of the gate trench structure 4 can be improved by the first doped region 5 with the second doping type, and the length of the well region 3 in the direction perpendicular to the first surface 11 does not need to be further increased on the basis of improving the reliability of the oxide layer of the gate 43, and further the deep P-type well region 3 does not need to be formed, so that the formation difficulty of the P-type well region 3 and the resistance of the MOSFET device are reduced.
The length of the well region 3 in the direction perpendicular to the first surface 11 may be understood as the depth of the well region 3 and the length of the gate trench structure 4 may be understood as the depth of the gate trench structure 4.
In other alternative embodiments, the length of the well region 3 may be greater than the length of the gate trench structure 4 in a direction perpendicular to the first surface 11.
In some alternative embodiments, the trench MOSFET may further include:
a second doped region 6 of the first doping type disposed on a surface of the well region 3 remote from the first surface 11 and in contact with the gate trench structure 4;
a third doped region 7 of the second doping type disposed within the well region 3 and spaced apart from the gate trench structure 4.
In this embodiment, the first doped region 6 may be an N-type second doped region 6, and the N-type second doped region 6 may be understood as an N-type heavily doped region (NSD). The third doped region 7 of the second doping type may be a third doped region 7 of P-type. The third doped region 7 of the P-type can be understood as a heavily doped region (PSD) of the P-type.
In some alternative embodiments, the trench MOSFET may further include:
and the source metal layer 8 is arranged in contact with each of the two adjacent second doped regions 6 and the two adjacent third doped regions 7.
In this embodiment, the source metal layer 8 may be used to connect two adjacent third doped regions 7.
It should be noted that the first doping type is N-type and the second doping type is P-type in this embodiment. However, in actual implementation, the substrate 1 is not limited to the N-type, and may be P-type. When the substrate 1 is P-type, the doping types of the structures such as the epitaxial layer 2, the well region 3, the first doped region 5 and the second doped region 6 are correspondingly changed.
Based on the trench MOSFET provided in the above embodiment, the present application also provides a method for manufacturing the trench MOSFET. The trench MOSFET manufacturing method will be described below.
Fig. 2 is a schematic flow chart of an embodiment of a method for manufacturing a trench MOSFET provided in the present application.
As shown in fig. 2, the trench MOSFET manufacturing method may include S210 to S230. Referring to fig. 3 to 15 together, fig. 3 to 15 are schematic cross-sectional structures corresponding to a series of processes in the trench MOSFET manufacturing method provided in the present application.
S210, providing a substrate of a first doping type, wherein the substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface.
In this embodiment, the substrate 1 of the first doping type may be an N-type substrate 1.
In some alternative embodiments, as shown in fig. 3, an N-type substrate 1 is provided first, and then an epitaxy is performed on the substrate 1 to form an N-type epitaxial layer 2. Wherein the doping ion concentration of the substrate 1 may be greater than the doping ion concentration of the epitaxial layer 2.
And S220, forming a well region of the second doping type on the surface of the epitaxial layer away from the first surface.
In this embodiment, the well region 3 of the second doping type may be a P-type well region 3.
As shown in fig. 4, in some alternative embodiments, the formation of the well region 3 of the second doping type on the surface of the epitaxial layer 2 remote from the first surface 11 may be that ion doping of the second doping type is performed on the surface of the epitaxial layer 2 remote from the first surface 11, and annealing is performed to form the well region 3 of the second doping type.
Illustratively, ion doping of the P-type is performed on the surface of the epitaxial layer 2 remote from the first surface 11, and annealing forms the well region 3 of the P-type.
And S230, forming a gate groove structure in the well region, and forming a first doping region of a second doping type in contact with the bottom corner of the groove structure in the epitaxial layer, wherein the bottom gate oxide layer of the gate groove structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side, far away from the first surface, of the first bottom gate oxide layer and is not in contact with the side gate oxide layer of the gate groove structure.
In some alternative embodiments, as shown in fig. 5 to 11, and fig. 13, forming the gate trench structure 4 in the well region 3 and forming the first doped region 5 of the second doping type in the epitaxial layer 2 in contact with the bottom corner of the trench structure 45 may include:
forming a first transition layer 46 on a surface of the well region 3 remote from the first surface 11;
forming a first hard mask layer 47 on a surface of the first transition layer 46 remote from the first surface 11;
forming a trench structure 45 in the well region 3;
forming a second transition layer 48 on a surface of the trench structure 45;
forming a second hard mask layer 49 on a surface of the second transition layer 48 remote from the first surface 11 and a surface of the first hard mask layer 47 remote from the first surface 11, respectively;
etching the second hard mask layer 49 at the bottom of the trench structure 45;
forming a second bottom gate oxide layer 412 within trench structure 45;
etching all of the first hard mask layer 47 and all of the second hard mask layer 49;
forming a first doped region 5 of a second doping type in the epitaxial layer 2 in contact with the bottom corner of the trench structure 45;
removing all of the first transition layer 46 and all of the second transition layer 48, forming a first bottom gate oxide 411 and a side gate oxide 42 within the trench structure 45;
a gate 43 is formed within trench structure 45.
As shown in fig. 5, forming the first transition layer 46 on the surface of the well region 3 remote from the first surface 11 may include: the surface of the well region 3 remote from the first surface 11 is thermally oxidized to form a first transition layer 46. Wherein the material of the first transition layer 46 may comprise silicon oxide.
As shown in fig. 6, forming a first hard mask layer 47 on a surface of the first transition layer 46 remote from the first surface 11 may include: silicon nitride is deposited on the surface of the first transition layer 46 remote from the first surface 11 to form a first hard mask layer 47.
As shown in fig. 7, forming the trench structure 45 in the well region 3 may include: the etched region is defined by a lithography plate and a trench etch is performed down the surface of the epitaxial layer 2 remote from the first surface 11 to form a trench structure 45.
As shown in fig. 8, forming the second transition layer 48 on the surface of the trench structure 45 may include: the surface of trench structure 45 remote from first surface 11 is thermally oxidized to form a second transition layer 48. Wherein the material of the second transition layer 48 may comprise silicon oxide.
As shown in fig. 9, forming the second hard mask layer 49 on the surface of the second transition layer 48 away from the first surface 11 and the surface of the first hard mask layer 47 away from the first surface 11, respectively, may include: silicon nitride is deposited on the surface of the second transition layer 48 remote from the first surface 11 and on the surface of the first hard mask layer 47 remote from the first surface 11 to form a second hard mask layer 49.
The thickness of the second hard mask layer 49 may determine the width of the first doped region 5 and the width of the second bottom oxide layer. Width is understood to be the length in a direction parallel to the first surface 11.
Etching the second hard mask layer 49 at the bottom of the trench structure 45 may include: the second hard mask layer 49 at the bottom of the trench structure 45 is etched by anisotropic etching.
As shown in fig. 10, forming a second bottom gate oxide layer 412 within trench structure 45 may include:
depositing silicon oxide on the surface of trench structure 45 remote from first surface 11 to form initial bottom gate oxide 41; the initial bottom gate oxide 41 is back etched to form a second bottom gate oxide 412.
Wherein the time of the etch back is inversely related to the thickness of the second bottom gate oxide layer 412. The thickness of the second bottom gate oxide layer 412 may be controlled by controlling the time of the etch back. The thickness of the second bottom gate oxide layer 412 is capable of blocking the implantation of the dopant ions in the first doped region 5, i.e., the thickness of the second bottom gate oxide layer 412 is greater than the implantation range of the dopant ions in the first doped region 5.
Etching all of the first hard mask layer 47 and all of the second hard mask layer 49 may include: all of the first hard mask layer 47 and all of the second hard mask layer 49 are etched isotropically.
As shown in fig. 11, forming a first doped region 5 of a second doping type in contact with the bottom corner of the trench structure 45 within the epitaxial layer 2 may include: ion doping of the second doping type is performed at the surface of the epitaxial layer 2 remote from the first surface 11 and at the bottom corners of the trench structure 45 to form the first doped region 5.
It should be noted that, due to the blocking of the second bottom gate oxide layer 412 of the trench structure 45 away from the first surface 11, the first doped region 5 is formed only at the bottom corner of the trench structure 45.
As shown in fig. 12, forming the first bottom gate oxide 411 and the side gate oxide 42 within the trench structure 45 may include: the surface of epitaxial layer 2 remote from the first surface and the surface of trench structure 45 remote from first surface 11 are oxidized to form first bottom gate oxide 411, side gate oxide 42 and oxide 21.
As shown in fig. 13, forming the gate 43 within the trench structure 45 may include: polysilicon is deposited and etched back within trench structure 45 to form gate 43.
In some alternative embodiments, after forming gate 43 within trench structure 45, the method may further comprise:
an isolation dielectric layer 44 is formed on the surface of the epitaxial layer 2 remote from the first surface 11 in contact with the gate electrode 43. As shown in fig. 14, forming an isolation dielectric layer 44 in contact with the gate electrode 43 on a surface of the epitaxial layer 2 remote from the first surface 11 includes: silicon oxide is deposited on the surface of epitaxial layer 2 remote from first surface 11 and planarized to form isolation dielectric layer 44.
In this embodiment, the first transition layer 46 may function as a transition layer where the first hard mask layer 47 contacts the epitaxial layer 2. The second transition layer 48 may function as a transition layer in which the second hard mask layer 49 contacts the well region 3, or a transition layer in which the second hard mask layer 49 contacts the epitaxial layer 2.
According to the method for manufacturing the groove type MOSFET, the groove type MOSFET comprises a well region, a gate groove structure and a first doping region which are arranged in an epitaxial layer. On the one hand, the bottom corner of the gate trench structure is contacted with the first doped region with the second doped type, when the trench MOSFET device is in a reverse bias state, the first doped region with the second doped type can improve the problem of electric field concentration at the bottom corner of the gate trench structure, so that the reliability of the gate oxide layer is improved, and the voltage withstand capability of the trench MOSFET device is improved. On the other hand, the bottom oxide layer of the gate trench structure may include a first bottom gate oxide layer and a second bottom gate oxide layer disposed in contact with the first bottom gate oxide layer, where the second bottom gate oxide layer is disposed on a side of the first bottom gate oxide layer away from the first surface, that is to say, the thickness of a portion of the first bottom gate oxide layer is increased, so that the gate-drain capacitance (i.e., the capacitance between the gate and the drain) can be effectively reduced, and the switching loss is reduced.
In some alternative embodiments, as shown in fig. 13 and 14, after forming the gate 43 within the trench structure 45, the method may further include:
on the surface of the well region 3 remote from the first surface 11, a second doped region 6 of the first doping type is formed in contact with the gate trench structure 4.
After forming the isolation dielectric layer 44 in contact with the gate electrode 43 on the surface of the epitaxial layer 2 remote from the first surface 11, the method may further include:
a third doped region 7 of the second doping type is formed in the well region 3 spaced apart from the gate trench structure 4.
Illustratively, a contact hole 22 is etched in the well region 3, and a high concentration of an impurity of the second doping type is implanted in the well region 3 through the contact hole 22 to form a third doping region 7 of the second doping type spaced apart from the gate trench structure 4.
In some alternative embodiments, as shown in fig. 15, after forming the gate trench structure 4 in the well region 3 and forming the first doped region 5 of the second doping type in the epitaxial layer 2 in contact with the bottom corner of the gate trench structure 4, the method may further include:
a source metal layer 8 is formed in contact with both of the adjacent two second doped regions 6 and the adjacent two third doped regions 7.
The source metal layer 8, which is disposed in contact with both the adjacent two second doped regions 6 and the adjacent two third doped regions 7, may be formed by depositing a metal, for example.
In some alternative embodiments, as shown in fig. 1, the substrate 1 may further include a second surface 12 opposite to the first surface 11, a gate trench structure 4 is formed in the well region 3, and a first doped region 5 of a second doping type is formed in the epitaxial layer 2 in contact with a bottom corner of the gate trench structure 4, and the method may further include:
a drain structure 9 is formed at the second surface 12.
In some alternative embodiments, bottom gate oxide 41 has a "convex" cross-section in a direction perpendicular to first surface 11.
In some alternative embodiments, the length of the well region 3 is smaller than the length of the gate trench structure 4 in a direction perpendicular to said first surface 11.
It should be noted that the first doping type is N-type and the second doping type is P-type in this embodiment. However, in actual implementation, the substrate 1 is not limited to the N-type, and may be P-type. When the substrate 1 is P-type, the doping types of the structures such as the epitaxial layer 2, the well region 3, the first doped region 5 and the second doped region 6 are correspondingly changed.
The trench MOSFET manufacturing method in the above embodiment, in which the respective structures and advantageous effects have been described in detail in the embodiment related to the trench MOSFET, will not be described in detail here.
In the foregoing, only the specific embodiments of the present application are described, and it will be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the systems, modules and units described above may refer to the corresponding processes in the foregoing method embodiments, which are not repeated herein. It should be understood that the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive various equivalent modifications or substitutions within the technical scope of the present application, which are intended to be included in the scope of the present application.

Claims (10)

1. A trench MOSFET comprising:
a substrate of a first doping type, the substrate comprising a first surface on which an epitaxial layer of the first doping type is disposed;
a well region of a second doping type disposed within the epitaxial layer;
the bottom gate oxide layer of the gate trench structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer which is in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side of the first bottom gate oxide layer away from the first surface and is not in contact with the side gate oxide layer of the gate trench structure;
a first doped region of the second doping type disposed within the epitaxial layer and in contact with a bottom corner of the gate trench structure;
the first doping type is opposite to the second doping type.
2. The trench MOSFET of claim 1 wherein the bottom gate oxide has a "convex" cross-section in a direction perpendicular to the first surface.
3. The trench MOSFET of claim 1 wherein a length of the well region is less than a length of the gate trench structure in a direction perpendicular to the first surface.
4. The trench MOSFET of claim 1, further comprising:
a second doped region of the first doping type disposed on a surface of the well region remote from the first surface and in contact with the gate trench structure;
and a third doped region of the second doping type disposed within the well region and spaced apart from the gate trench structure.
5. The trench MOSFET of claim 4, further comprising:
and the source metal regions are contacted with the two adjacent second doped regions and the two adjacent third doped regions.
6. The trench MOSFET of claim 1, wherein the substrate further comprises a second surface opposite the first surface, the second surface being provided with a drain structure.
7. A method of fabricating a trench MOSFET, comprising: providing a substrate of a first doping type, wherein the substrate comprises a first surface, and an epitaxial layer of the first doping type is arranged on the first surface;
forming a well region of a second doping type on a surface of the epitaxial layer away from the first surface;
and forming a gate trench structure in the well region, and forming a first doped region of the second doping type in contact with the bottom corner of the gate trench structure in the epitaxial layer, wherein the bottom gate oxide of the gate trench structure comprises a first bottom gate oxide layer and a second bottom gate oxide layer which is in contact with the first bottom gate oxide layer, and the second bottom gate oxide layer is arranged on one side, far away from the first surface, of the first bottom gate oxide layer and is not in contact with the side gate oxide layer of the gate trench structure.
8. The method of claim 7, wherein forming a gate trench structure in the well region and forming a first doped region of the second doping type in the epitaxial layer in contact with a bottom corner of the gate trench structure, comprises:
forming a first transition layer on a surface of the well region away from the first surface;
forming a first hard mask layer on a surface of the first transition layer remote from the first surface;
forming a groove structure in the well region;
forming a second transition layer on the surface of the groove structure;
forming a second hard mask layer on a surface of the second transition layer away from the first surface and a surface of the first hard mask layer away from the first surface, respectively;
etching the second hard mask layer at the bottom of the groove structure;
forming a second bottom gate oxide layer in the trench structure;
etching all the first hard mask layer and all the second hard mask layer;
forming a first doped region of the second doping type within the epitaxial layer in contact with a bottom corner of the trench structure;
removing all the first transition layers and all the second transition layers, and forming a first bottom gate oxide layer and a side gate oxide layer in the groove structure;
a gate is formed within the trench structure.
9. The method of manufacturing a trench MOSFET according to claim 7, wherein the bottom gate oxide has a "convex" cross-section in a direction perpendicular to the first surface.
10. The method of claim 7, wherein the well region has a length in a direction perpendicular to the first surface that is less than a length of the gate trench structure.
CN202310436210.4A 2023-04-21 2023-04-21 Trench MOSFET and manufacturing method thereof Pending CN116207156A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006032420A (en) * 2004-07-12 2006-02-02 Toyota Motor Corp Insulation gate semiconductor device and manufacturing method thereof
CN106601795A (en) * 2016-11-25 2017-04-26 东莞市联洲知识产权运营管理有限公司 Trench field effect transistor and manufacturing method thereof
CN110190127A (en) * 2019-05-29 2019-08-30 陕西半导体先导技术中心有限公司 A kind of silicon carbide MOSFET device with L-type masking layer structure
CN113838909A (en) * 2021-08-19 2021-12-24 深圳深爱半导体股份有限公司 Groove type primitive cell structure and preparation method

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006032420A (en) * 2004-07-12 2006-02-02 Toyota Motor Corp Insulation gate semiconductor device and manufacturing method thereof
CN106601795A (en) * 2016-11-25 2017-04-26 东莞市联洲知识产权运营管理有限公司 Trench field effect transistor and manufacturing method thereof
CN110190127A (en) * 2019-05-29 2019-08-30 陕西半导体先导技术中心有限公司 A kind of silicon carbide MOSFET device with L-type masking layer structure
CN113838909A (en) * 2021-08-19 2021-12-24 深圳深爱半导体股份有限公司 Groove type primitive cell structure and preparation method

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