CN106601795A - Trench field effect transistor and manufacturing method thereof - Google Patents
Trench field effect transistor and manufacturing method thereof Download PDFInfo
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- CN106601795A CN106601795A CN201611051510.7A CN201611051510A CN106601795A CN 106601795 A CN106601795 A CN 106601795A CN 201611051510 A CN201611051510 A CN 201611051510A CN 106601795 A CN106601795 A CN 106601795A
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 238000002353 field-effect transistor method Methods 0.000 title abstract 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 44
- 230000005669 field effect Effects 0.000 claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 229920005591 polysilicon Polymers 0.000 claims description 41
- 238000000034 method Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 230000003647 oxidation Effects 0.000 claims description 3
- 238000007254 oxidation reaction Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 2
- 229910052760 oxygen Inorganic materials 0.000 claims description 2
- 239000001301 oxygen Substances 0.000 claims description 2
- 229910003978 SiClx Inorganic materials 0.000 claims 1
- 230000003071 parasitic effect Effects 0.000 abstract description 9
- 239000004065 semiconductor Substances 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 2
- 230000015556 catabolic process Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 238000009751 slip forming Methods 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000010615 ring circuit Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000008719 thickening Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to the technical field of semiconductors, particularly to a trench field effect transistor and manufacturing method thereof. The trench field effect transistor manufactured by the invention includes a substrate, an n- epitaxial layer, a p type body region, n+ active regions, a trench and a polycrystalline silicon gate and a gate oxide layer which are arranged in the trench, the trench also contains an insulating medium layer, the insulating medium layer segments one side of the polycrystalline silicon gate which is close to the bottom of the trench into two parts which are close to the p type body region at two sides separately, and a p type doping region is formed between the trench bottom corresponding to one side of the polycrystalline silicon gate close to the trench bottom and the n- epitaxial layer. The trench field effect transistor provided by the invention effectively reduces gate-drain parasitic capacitance, and improves switching speed.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of trench field effect transistor and its manufacture method.
Technical background
Slot type MOSFET (Trench MOSFET) is to develop rapidly in recent years
New Type Power Devices.Trench MOSFET have high input impedance, low driving current, not few sub- storage effect, switch speed
Degree is fast, and operating frequency is high, and electric current self-adjusting ability is strong, homogeneous current distribution, and easily by parallel way current capacity, tool are increased
There is stronger power handling capability, heat stability is good, safety operation area is big, without excellent characteristics such as second breakdowns, extensively should
In for various electronic equipments, such as high-speed switching circuit, Switching Power Supply, uninterrupted power source, high power amplifying circuit, high-fidelity sound
Ring circuit, radio-frequency (RF) power amplification circuit, power conversion circuit, motor frequency conversion circuit, motor-drive circuit, solid-state relay, control electricity
Interface circuit between road and power termination etc..
Prior art Trench MOSFET conventional structures, the thickness of channel bottom gate oxide and the grid oxygen of other positions
Change thickness degree identical, than relatively thin, cause larger parasitic gate-drain capacitance so that switching speed is reduced, so as to cause device performance
Reduce.
Chinese patent ZL 201010129265.3 discloses a kind of slot type MOSFET
Manufacture method, using unidirectional oxide layer thickening step, make the oxide layer of channel bottom can be than other parts in groove
Oxidation thickness, thus parasitic capacitance (Qgd) effect of element can be effectively reduced, lift the electrical effect of high voltage semiconductor device
Energy.
The present invention provides another kind of different mode and effectively reduces parasitic gate-drain capacitance.
The content of the invention
It is an object of the invention to provide a kind of trench field effect transistor for effectively reducing parasitic gate-drain capacitance, raising is opened
Close speed.
It is a further object of the present invention to provide the manufacture method of above-mentioned trench field effect transistor.
For achieving the above object, the present invention is employed the following technical solutions：
A kind of trench field effect transistor, including substrate, are formed in the n- epitaxial layers of the substrate surface, are formed in institute
The p-type body area of n- epi-layer surfaces is stated, the p-type body area top is provided with n+ active areas, and groove extends through the n+ active areas
With p-type body area until the n- epitaxial layers, there are polysilicon gate and gate oxide in the groove, the gate oxide is formed in
Also it is not more than the insulating medium layer of gate oxide comprising dielectric constant in flute surfaces, the groove, the insulating medium layer will
Polysilicon gate is divided into the two parts respectively close to both sides p-type body area, and the polysilicon gate near channel bottom side
P-type doped region is formed extremely between the corresponding channel bottom in channel bottom side and n- epitaxial layers, the polysilicon gate is leaned on
The side of nearly channel bottom is projected in p-type doped region.
Preferably, the dielectric constant of the insulating medium layer is less than gate oxide.
Preferably, channel bottom is arrived in the insulating medium layer top to the distance of channel bottom more than n+ active areas bottom
Distance.
Preferably, the dielectric layer material is silicon oxide, silicon nitride or silicon oxynitride.
Preferably, the p-type doped region doping content is less than p-type body area doping content.
Preferably, the p-type doped region is continuously formed at channel bottom.
Preferably, the p-type doped region both sides have overlap with n+ active areas in the projection of n- epitaxial layers.
A kind of trench field effect transistor manufacture method, comprises the following steps：
(1) substrate is provided, and sequentially forms n- epitaxial layers and p-type body area over the substrate；
(2) formed by the p-type body area until the groove of the n- epitaxial layers by etching technics；
(3) p-type doped region is formed in the channel bottom by doping process；
(4) gate oxide is formed in the flute surfaces；
(5) polysilicon gate is formed in the groove, the polysilicon gate is insulated Jie near channel bottom side
Matter floor is separated into the two parts respectively close to both sides p-type body area；
(6) groove top both sides adulterate to form n+ active areas in the p-type body area.
Preferably, step (4) forms gate oxide by thermal oxidation method.
Preferably, step (5) is in trench interiors point depositing doped polysilicon, then to etch first middle section, and
Filling dielectric forms insulating medium layer in the middle section for etching away, and finally again depositing doped polysilicon fills up groove,
Form polysilicon gate.
Relative to prior art, the present invention has advantages below：
Trench field effect transistor insulating medium layer of the present invention is divided polysilicon gate near channel bottom side
Into the two parts respectively close to both sides p-type body area, the contact area of polysilicon gate and gate oxide is partly reduced, and then subtracted
The parasitic gate-drain capacitance that few polysilicon gate, gate oxide and n- epitaxial layers are produced, improves switching speed；Insulation is set simultaneously
Dielectric layer, when field effect transistor works, strengthens the electric current density on the polysilicon gate in both sides p-type body area, quickly induces and leads
Electric raceway groove, further increases opening speed；Polysilicon gate is near the corresponding channel bottom in channel bottom side and n- epitaxial layers
Between form p-type doped region, p-type doped region and n- epitaxial layers form pn-junction, increase breakdown voltage.
Description of the drawings
Fig. 1 is the trench field effect transistor cross-sectional view of first embodiment of the invention；
Figure 1A-Fig. 1 F, the trench field effect transistor manufacture process cross-sectional view of first embodiment of the invention；
Fig. 2 is the trench field effect transistor cross-sectional view of second embodiment of the invention；
Fig. 3 is the trench field effect transistor cross-sectional view of third embodiment of the invention；
Fig. 4 is the trench field effect transistor cross-sectional view of fourth embodiment of the invention.
Specific embodiment
For a better understanding of the present invention, below in conjunction with the accompanying drawings and embodiment the invention will be described further, implement
Example is only limitted to explain the present invention, not to any restriction of present invention composition.
First embodiment
As shown in figure 1, the present embodiment trench field effect transistor, including substrate 10, it is formed in the surface of the substrate 10
N- epitaxial layers 20, be formed in the p-type body area 30 on the surface of n- epitaxial layers 20, it is active that the top of the p-type body area 30 is provided with n+
Area 40, groove 50 extends through the n+ active areas 40 to be had with p-type body area 30 in the n- epitaxial layers 20, the groove 50
Polysilicon gate 60 and gate oxide 70, the gate oxide 70 is formed in the surface of groove 50, the groove 50 also comprising Jie
Electric constant is not more than the insulating medium layer 80 of gate oxide 70, and the insulating medium layer 80 is by polysilicon gate 60 near groove 50
Bottom side is divided into the two parts respectively close to both sides p-type body area 30, and the polysilicon gate 60 near the bottom of groove 50
P-type doped region 90 is formed between the corresponding bottom of groove 50 in portion side and n- epitaxial layers 20, the polysilicon gate 60 is near ditch
The side of the bottom of groove 50 is projected in p-type doped region 90.
The substrate 10 forms drain region mixed with high concentration n-type dopant, the n- epitaxial layers 20 low with doping content, to
Drain region resistance value is reduced, n- epitaxial layers 20 are mixed with the n-type dopant of low concentration increasing hitting for trench field effect transistor
Wear voltage；P-type body area 30 is formed in the surface of n- epitaxial layers 20, when the voltage of polysilicon gate 60 is more than threshold voltage, p-type body
Area 30 forms conducting channel towards the region of polysilicon gate 60, and the n+ that the conducting channel is used to set up high-dopant concentration is active
Area 40 and corresponding to the electric connection between drain region n- epitaxial layer 20.
Insulating medium layer 80 is also included in the groove 50, the insulating medium layer 80 is by polysilicon gate 60 near groove
50 bottom sides are divided into the two parts respectively close to both sides p-type body area 30, the setting of insulating medium layer 80 to cause the present embodiment
Subtract with the contact area of gate oxide 70 with respect to polysilicon gate 60 of the Trench MOSFET conventional structures near channel bottom
It is little, so reduce polysilicon gate 60, the parasitic gate-drain capacitance that gate oxide 70 and n- epitaxial layers 20 are produced, or from another
Say in individual angle, and the polysilicon gate 60 away from channel bottom increases with the distance of n- epitaxial layers 20, and then reduce polysilicon
The parasitic gate-drain capacitance that grid 60, gate oxide 70 are produced with n- epitaxial layers 20；Insulating medium layer 80, field effect are set simultaneously
When pipe works, strengthen the electric current density on the polysilicon gate 60 in both sides p-type body area 30, quickly induce conducting channel, enter
One step increases opening speed.
The material of insulating medium layer 80 can be silicon oxide, silicon nitride or silicon oxynitride, it is preferred that the insulating medium layer 80
Dielectric constant is less than gate oxide 70, further reduces reduction polysilicon gate 60, gate oxide 70 and produces with n- epitaxial layers 20
Parasitic gate-drain capacitance.
Polysilicon gate 60 forms p-type between the corresponding bottom of groove 50 of the bottom side of groove 50 and n- epitaxial layers 20
Doped region 90, p-type doped region 90 forms pn-junction with n- epitaxial layers 20, prevents the lower section forceful electric power field breakdown of groove 50, increases breakdown potential
Pressure, it is preferred that the doping content of p-type doped region 90 is less than the doping content of p-type body area 30, strengthens compressive property.
The present embodiment trench field effect transistor manufacture method process cross-sectional view is as shown in Figure 1A-Fig. 1 F.
Comprise the following steps：
(1) such as Figure 1A, there is provided a substrate 10, and n- epitaxial layers 20 and p-type body area 30 are sequentially formed over the substrate；
(2) such as Figure 1B, formed by the p-type body area 30 until the n- epitaxial layers 20 by etching technics such as mask lithographies
Groove 50；
(3) such as Fig. 1 C, p-type doped region is formed in the bottom of the groove 50 by doping process such as diffusion or ion implantings
90；
(4) such as Fig. 1 D, the upper surface of thermal oxide p-type body area 30 and flute surfaces form gate oxide in the flute surfaces
70；
(5) such as Fig. 1 E, the technique such as deposition wet etching, in the interior part depositing doped polysilicon of the groove 50, is then carved
Erosion middle section, fills dielectric and forms insulating medium layer 80 in the middle section for etching away, finally deposition doping again
Polysilicon fills up groove 50, forms polysilicon gate 60；
(6) such as Fig. 1 F, the top both sides of groove 50 adulterate to form n+ active areas 40 in the p-type body area 30, remove p-type body
The oxide-film of the upper surface of area 30.
Second embodiment
As shown in Fig. 2 second embodiment is relative to first embodiment, the top of insulating medium layer 80 to the bottom of groove 50 away from
From more than the bottom of n+ active areas 40 to the bottom of groove 50 with a distance from so that entirely the corresponding polysilicon gate 60 in p-type body area 30 is electric
Current density uniformly strengthens, and preferably increases opening speed.
3rd embodiment
As shown in figure 3,3rd embodiment is relative to first embodiment, the p-type doped region 90 is continuously formed at groove
50 bottoms, increase the resistance performance to the strong voltage of polysilicon gate 60, while the work that doping forms p-type doped region 90 can be simplified
Skill process.
Fourth embodiment
As shown in figure 4, fourth embodiment is relative to 3rd embodiment, the both sides of p-type doped region 90 and n+ active areas 40
There is overlap in the projection of n- epitaxial layers 20, due to diffusion, the present embodiment phase in the technical process for forming p-type doped region 90 of adulterating
For first embodiment and 3rd embodiment are easily realized, meanwhile, in the off state, source ground, drain electrode is plus just
During to voltage, the both sides of p-type doped region 90 have overlap with n+ active areas 40 in the projection of n- epitaxial layers 20, and the pn-junction of formation can increase
Plus the compressive property between source and drain.
Claims (10)
1. a kind of trench field effect transistor, including substrate, is formed in the n- epitaxial layers of the substrate surface, is formed in described
The p-type body area of n- epi-layer surfaces, the p-type body area top is provided with n+ active areas, and groove extends through the n+ active areas and p
There are polysilicon gate and gate oxide in Xing Ti areas until the n- epitaxial layers in the groove, the gate oxide is formed in ditch
Rooved face, it is characterised in that：Also it is not more than the insulating medium layer of gate oxide, the insulation comprising dielectric constant in the groove
Polysilicon gate is divided into two parts respectively close to both sides p-type body area by dielectric layer near channel bottom side, and described
Polysilicon gate forms p-type doped region, the polycrystalline between the corresponding channel bottom in channel bottom side and n- epitaxial layers
Silicon gate being projected in p-type doped region near the side of channel bottom.
2. trench field effect transistor according to claim 1, it is characterised in that：The dielectric of the insulating medium layer is normal
Number is less than gate oxide.
3. trench field effect transistor according to claim 1, it is characterised in that：The insulating medium layer top is to ditch
Distance of the distance of trench bottom more than n+ active areas bottom to channel bottom.
4. trench field effect transistor according to claim 1, it is characterised in that：The dielectric layer material is oxygen
SiClx, silicon nitride or silicon oxynitride.
5. trench field effect transistor according to claim 1, it is characterised in that：The p-type doped region doping content
Less than p-type body area doping content.
6. trench field effect transistor according to claim 1, it is characterised in that：The continuous landform of the p-type doped region
Into in channel bottom.
7. the trench field effect transistor according to claim 1 or 6, it is characterised in that：The p-type doped region both sides with
N+ active areas have overlap in the projection of n- epitaxial layers.
8. a kind of trench field effect transistor manufacture method, it is characterised in that comprise the following steps：
(1) substrate is provided, and sequentially forms n- epitaxial layers and p-type body area over the substrate；
(2) formed by the p-type body area until the groove of the n- epitaxial layers by etching technics；
(3) p-type doped region is formed in the channel bottom by doping process；
(4) gate oxide is formed in the flute surfaces；
(5) polysilicon gate is formed in the groove, the polysilicon gate is near channel bottom side by insulating medium layer
It is separated into the two parts respectively close to both sides p-type body area；
(6) groove top both sides adulterate to form n+ active areas in the p-type body area.
9. the manufacture method of trench field effect transistor according to claim 8, it is characterised in that：Step (4) passes through
Thermal oxidation method forms gate oxide.
10. the manufacture method of trench field effect transistor according to claim 8, it is characterised in that：Headed by step (5)
First in trench interiors point depositing doped polysilicon, middle section, and the filling insulation in the middle section for etching away then are etched
Medium forms insulating medium layer, and finally again depositing doped polysilicon fills up groove, forms polysilicon gate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611051510.7A CN106601795B (en) | 2016-11-25 | 2016-11-25 | A kind of trench field effect transistor and its manufacturing method |
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|---|---|---|---|
| CN201611051510.7A CN106601795B (en) | 2016-11-25 | 2016-11-25 | A kind of trench field effect transistor and its manufacturing method |
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| CN106601795A true CN106601795A (en) | 2017-04-26 |
| CN106601795B CN106601795B (en) | 2019-05-28 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111244181A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN116207156A (en) * | 2023-04-21 | 2023-06-02 | 北京中科新微特科技开发股份有限公司 | Trench MOSFET and manufacturing method thereof |
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| CN1540770A (en) * | 2003-04-23 | 2004-10-27 | 株式会社东芝 | Semiconductor device and its mfg. method |
| US20070023828A1 (en) * | 2005-07-26 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN103545216A (en) * | 2012-07-13 | 2014-01-29 | 力祥半导体股份有限公司 | Method for manufacturing groove type grid metal oxide semiconductor field effect transistor |
| WO2016009736A1 (en) * | 2014-07-18 | 2016-01-21 | トヨタ自動車株式会社 | Switching element |
-
2016
- 2016-11-25 CN CN201611051510.7A patent/CN106601795B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1540770A (en) * | 2003-04-23 | 2004-10-27 | 株式会社东芝 | Semiconductor device and its mfg. method |
| US20070023828A1 (en) * | 2005-07-26 | 2007-02-01 | Kabushiki Kaisha Toshiba | Semiconductor device and method of manufacturing the same |
| CN103545216A (en) * | 2012-07-13 | 2014-01-29 | 力祥半导体股份有限公司 | Method for manufacturing groove type grid metal oxide semiconductor field effect transistor |
| WO2016009736A1 (en) * | 2014-07-18 | 2016-01-21 | トヨタ自動車株式会社 | Switching element |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111244181A (en) * | 2020-01-19 | 2020-06-05 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN111244181B (en) * | 2020-01-19 | 2022-05-17 | 深圳市昭矽微电子科技有限公司 | Metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN116207156A (en) * | 2023-04-21 | 2023-06-02 | 北京中科新微特科技开发股份有限公司 | Trench MOSFET and manufacturing method thereof |
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| CN106601795B (en) | 2019-05-28 |
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