CN110061057B - Super junction power MOSFET with integrated tunneling diode - Google Patents
Super junction power MOSFET with integrated tunneling diode Download PDFInfo
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- CN110061057B CN110061057B CN201910373014.0A CN201910373014A CN110061057B CN 110061057 B CN110061057 B CN 110061057B CN 201910373014 A CN201910373014 A CN 201910373014A CN 110061057 B CN110061057 B CN 110061057B
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- 230000005641 tunneling Effects 0.000 title claims abstract description 19
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 26
- 229920005591 polysilicon Polymers 0.000 claims abstract description 26
- 238000007667 floating Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 6
- 230000005669 field effect Effects 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 4
- 239000000377 silicon dioxide Substances 0.000 claims description 4
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910002601 GaN Inorganic materials 0.000 claims description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 3
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 3
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052454 barium strontium titanate Inorganic materials 0.000 claims description 3
- 210000000746 body region Anatomy 0.000 claims description 3
- 229910052732 germanium Inorganic materials 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- 238000011084 recovery Methods 0.000 abstract description 10
- 238000000034 method Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- Power Engineering (AREA)
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- Condensed Matter Physics & Semiconductors (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
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Abstract
The invention relates to a super junction power MOSFET with an integrated tunneling diode, and belongs to the field of semiconductor power devices. The MOSFET includes: the gate structure comprises a drain terminal electrode, an N-type substrate, an N-type doped region, an insulating layer I, a P-type doped region II, an N + doped region I, a P + doped region I, a gate oxide layer, a polysilicon gate, a source terminal electrode, a P + doped region II, an N + doped region II, an insulating layer II and a floating electrode. The invention can greatly reduce the reverse recovery charge of the device without increasing the specific on-resistance and the leakage current of the device and can not increase the process difficulty.
Description
Technical Field
The invention belongs to the field of semiconductor power devices, and relates to a super junction power MOSFET with an integrated tunneling diode.
Background
A super junction Metal-Oxide-Semiconductor Field effect transistor (MOSFET), i.e., a Metal-Oxide-Semiconductor Field effect transistor, can improve the contradiction between the breakdown voltage and the specific on-resistance in the conventional power MOSFET device, has extremely low specific on-resistance and extremely high switching speed, and is widely applied to the fields of industry, new energy, information traffic, and the like. However, the body diode of the super junction MOSFET has a very large reverse recovery charge, which will reduce the efficiency of the power converter to which the super junction technology MOSFET is applied and increase the noise of the power converter.
In order to reduce the reverse recovery charge of the body diode, a carrier lifetime control technique is generally used, such as introducing effective recombination centers by doping heavy metal impurities such as gold and platinum, or performing high-energy electron irradiation at the end of device fabrication. Another type of solution is to improve the device structure, such as an integrated schottky diode or a semi-superjunction structure. However, the above-mentioned techniques reduce the body diode direction to recover the charge, and at the same time, the stability of the device is often reduced or the specific on-resistance and the leakage current of the device are often increased.
Therefore, a MOSFET capable of greatly reducing the reverse recovery charge of the device without increasing the specific on-resistance and the leakage current of the device and ensuring the stability of the device is needed.
Disclosure of Invention
In view of the above, the present invention provides a super junction power MOSFET with an integrated tunneling diode, that is, a manufacturing technique of a power MOSFET device with a novel structure is provided, which can greatly reduce the reverse recovery charge of the device without increasing the specific on-resistance and the leakage current of the device; and does not increase the difficulty of the process.
In order to achieve the purpose, the invention provides the following technical scheme:
a super junction power MOSFET with an integrated tunneling diode is formed by mutually splicing a plurality of repeated cell structures and specifically comprises: the field effect transistor comprises a drain terminal electrode (01), an N-type substrate (02), an N-type doped region (03), an insulating layer I (04), a P-type doped region I (05), a P-type doped region II (06), an N + doped region I (07), a P + doped region I (08), a gate oxide layer (09), a polysilicon gate (10), a source terminal electrode (11), a P + doped region II (12), an N + doped region II (13), an insulating layer II (14) and a floating electrode (15);
the N-type substrate (02) is arranged above the drain electrode (01); the N-type doped region (03), the insulating layer I (04) and the P-type doped region I (05) are arranged above the N-type substrate (02); the P-type doped region II (06) is arranged above the N-type doped region (03); the N + doped region I (07), the P + doped region I (08) and the N + doped region II (13) are arranged above the P type doped region II (06);
the gate oxide layer (09) is surrounded by an N-type doped region (03), a P-type doped region II (06) and an N + doped region I (07); the polysilicon gate (10) is surrounded by the gate oxide layer (09);
the source electrode (11) is arranged above the N + doped region I (07) and the P + doped region I (08); the P + doped region II (12) is arranged above the P type doped region I (05); the floating electrode (15) is arranged above the P + doped region II (12); the insulating layer II (14) is arranged above the P + doping area I (08) and the N + doping area II (13);
the insulating layer I (04) isolates the N-type doped region (03), the P-type doped region II (06) and the N + doped region II (13) from the P-type doped region I (05) and the P + doped region II (12); the source end electrode (11) is isolated from the floating electrode (15) by an insulating layer II (14);
the N + doped region I (07) and the P + doped region I (08) are connected with the source end electrode (11); the N + doped region II (13) and the P + doped region II (12) are connected with a floating electrode (15); the N-type doped region (03), the P-type doped region II (06), the N + doped region I (07), the gate oxide layer (09) and the polysilicon gate (10) are respectively used as a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of an nMOS; the N-type doped region (03), the insulating layer I (04) and the P-type doped region I (05) are jointly used as a super junction body region;
the P + doped region I (08) and the N + doped region II (13) form a tunneling diode which is connected with a source electrode (11) and a floating electrode (15).
Further, the tunneling diode is connected in series with a diode formed by the P + doped region II (12), the P type doped region I (05) and the N type substrate (02), and when the super junction power MOSFET body diode is conducted, the turn-on voltage of the two serially connected diodes is about 1.4V.
Further, when the body diode of the super-junction power MOSFET is conducted, the turn-on voltage of the diode formed by the P + doped region I (08), the P type doped region II (06), the N type doped region (03) and the N type substrate (02) is about 0.7V.
Further, semiconductor materials include, but are not limited to, silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride. Insulating layer materials include, but are not limited to, silicon dioxide, silicon nitride, or barium strontium titanate.
The invention has the beneficial effects that: the invention can greatly reduce the reverse recovery charge of the device under the condition of not increasing the specific on-resistance and the leakage current of the device; and does not increase the difficulty of the process.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of a super junction power MOSFET according to the present invention;
FIG. 2 is an equivalent circuit diagram of the structure of FIG. 1;
fig. 3 is an equivalent circuit diagram of a conventional super junction power MOSFET device structure;
FIG. 4 is a graph comparing the reverse recovery characteristics of the structure of the present invention with a conventional structure;
fig. 5 is a schematic structural diagram of a super junction power MOSFET corresponding to example 2;
fig. 6 is a schematic structural diagram of a super junction power MOSFET corresponding to example 3;
reference numerals: 01-a drain terminal electrode, 02-an N-type substrate, 03-an N-type doped region, 04-an insulating layer I, 05-a P-type doped region I, 06-a P-type doped region II, 07-an N + doped region I, 08-a P + doped region I, 09-a gate oxide layer, 10-a polysilicon gate, 11-a source terminal electrode and 12-a P + doped region II; 13-N + doping area II, 14-insulating layer II, 15 floating electrode, 16-P + polysilicon I, 17-insulating layer III, 18-insulating layer IV, 19-N + polysilicon and 20-P + polysilicon II.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1: fig. 1 is a super junction power MOSFET with an integrated tunneling diode, which is formed by mutually splicing a plurality of repeating cell structures, and specifically includes: the field effect transistor comprises a drain electrode 01, an N-type substrate 02, an N-type doped region 03, an insulating layer I04, a P-type doped region I05, a P-type doped region II 06, an N + doped region I07, a P + doped region I08, a gate oxide layer 09, a polysilicon gate 10, a source electrode 11, a P + doped region II 12, an N + doped region II 13, an insulating layer II 14 and a floating electrode 15;
the N-type substrate 02 is arranged above the drain electrode 01; the N-type doped region 03, the insulating layer I04 and the P-type doped region I05 are arranged above the N-type substrate 02; the P-type doped region II 06 is above the N-type doped region 03; the N + doped region I07, the P + doped region I08 and the N + doped region II 13 are arranged above the P type doped region II 06;
the gate oxide layer 09 is surrounded by an N-type doped region 03, a P-type doped region II 06 and an N + doped region I07; the polysilicon gate 10 is surrounded by the gate oxide 09;
the source electrode 11 is arranged above the N + doped region I07 and the P + doped region I08; the P + doped region II 12 is arranged above the P type doped region I05; the floating electrode 15 is arranged above the P + doped region II 12; the insulating layer II 14 is arranged above the P + doping area I08 and the N + doping area II 13;
the insulating layer I04 isolates the N-type doped region 03, the P-type doped region II 06 and the N + doped region II 13 from the P-type doped region I05 and the P + doped region II 12; the source electrode 11 is isolated from the floating electrode 15 by an insulating layer II 14;
the N + doped region I07 and the P + doped region I08 are connected with the source electrode 11; the N + doping area II 13 and the P + doping area II 12 are connected with a floating electrode 15; the N-type doped region 03, the P-type doped region II 06, the N + doped region I07, the gate oxide layer 09 and the polysilicon gate 10 are respectively used as a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of an nMOS; the N-type doped region 03, the insulating layer I04 and the P-type doped region I05 are jointly used as a super junction body region.
Fig. 2 is an equivalent circuit diagram of the structure of fig. 1, and as shown in fig. 2, the diode 1 is composed of a P + doped region i 08, a P-type doped region ii 06, an N-type doped region 03, and an N-type substrate 02. The diode 2 is composed of a P + doped region II 12, a P type doped region I05 and an N type substrate 02. The diode 3 is a tunneling diode and is composed of an N + doping area II 13 and a P + doping area I08, the P + doping area I08 is connected with the source section electrode 11, the N + doping area II 13 is connected with the floating electrode 15, the floating electrode 15 is connected with the P + doping area II 12, and therefore the N + doping area II 13 is electrically connected with the P + doping area II 12.
FIG. 3 is an equivalent circuit diagram of a conventional super junction power MOSFET device structure, which is compared with the super junction MOSFET with an integrated tunneling diode shown in FIG. 1 of the present invention by simulation with the help of MEDICI simulation software, the two structures are the only difference that an N + doped region II 13, an insulating layer II 14 and a floating electrode 15 are introduced in FIG. 1, and in simulation, the doping concentration of an N-type substrate 02 is 5 × 1019cm-3The doping concentration of the N-type doped region 03 and the P-type doped region 05 are both 6 × 1015cm-32 μm in width and 40 μm in thickness, the insulating layer 04 is made of silicon dioxide, the gate oxide layer 09 is 80nm in width and 100nm in thickness, and the doping concentration of the p-type doped region ii 06 is 1 × 1017cm-3The doping concentrations of the N + doping region I07, the P + doping region I08, the P + doping region II 12 and the N + doping region II 13 are all 5 × 1019cm-3The thickness was 0.4. mu.m. FIG. 4 illustrates the structure of the present invention and the conventional structureThe comparison of the reverse recovery characteristics of the present invention shows that the reverse recovery charge of the structure of the present invention is lower at the same rate of current change.
In summary, the super junction MOSFET with the integrated tunneling diode provided by the present invention has an extremely low reverse recovery charge.
Example 2: the tunnel diode may also be formed of polysilicon within the trench gate as shown in figure 5. The polysilicon gate 10 is heavily doped N-type in this embodiment, and a heavily doped P + polysilicon i 16 is introduced into the polysilicon gate 10 to form a tunneling diode. The floating electrode 15 is connected to the polysilicon gate 10, and the P + polysilicon is connected to the source terminal electrode 11.
Example 3: as shown in example 3 of fig. 6, this polysilicon diode may also be formed of a planar gate polysilicon. The N + polysilicon 19 and the P + polysilicon II 20 jointly form a tunneling diode. The P + doping area II 12 is connected to the N + polysilicon 19 through the floating electrode 15, and the P + polysilicon II 20 is connected with the source end electrode 11.
In the above embodiments, the semiconductor material includes, but is not limited to, silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride; insulating layer materials include, but are not limited to, silicon dioxide, silicon nitride, or barium strontium titanate.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (5)
1. A super junction power MOSFET with an integrated tunneling diode, comprising: the field effect transistor comprises a drain terminal electrode (01), an N-type substrate (02), an N-type doped region (03), an insulating layer I (04), a P-type doped region I (05), a P-type doped region II (06), an N + doped region I (07), a P + doped region I (08), a gate oxide layer (09), a polysilicon gate (10), a source terminal electrode (11), a P + doped region II (12), an N + doped region II (13), an insulating layer II (14) and a floating electrode (15);
the N-type substrate (02) is arranged above the drain electrode (01); the N-type doped region (03), the insulating layer I (04) and the P-type doped region I (05) are arranged above the N-type substrate (02); the P-type doped region II (06) is arranged above the N-type doped region (03); the N + doped region I (07), the P + doped region I (08) and the N + doped region II (13) are arranged above the P type doped region II (06);
the gate oxide layer (09) is surrounded by an N-type doped region (03), a P-type doped region II (06) and an N + doped region I (07); the polysilicon gate (10) is surrounded by the gate oxide layer (09);
the source electrode (11) is arranged above the N + doped region I (07) and the P + doped region I (08); the P + doped region II (12) is arranged above the P type doped region I (05); the floating electrode (15) is arranged above the P + doped region II (12); the insulating layer II (14) is arranged above the P + doping area I (08) and the N + doping area II (13);
the insulating layer I (04) isolates the N-type doped region (03), the P-type doped region II (06) and the N + doped region II (13) from the P-type doped region I (05) and the P + doped region II (12); the source end electrode (11) is isolated from the floating electrode (15) by an insulating layer II (14);
the N + doped region I (07) and the P + doped region I (08) are connected with the source end electrode (11); the N + doped region II (13) and the P + doped region II (12) are connected with a floating electrode (15); the N-type doped region (03), the P-type doped region II (06), the N + doped region I (07), the gate oxide layer (09) and the polysilicon gate (10) are respectively used as a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of an nMOS; the N-type doped region (03), the insulating layer I (04) and the P-type doped region I (05) are jointly used as a super junction body region;
the P + doped region I (08) and the N + doped region II (13) form a tunneling diode which is connected with a source electrode (11) and a floating electrode (15).
2. The super-junction power MOSFET with the integrated tunneling diode of claim 1, wherein the tunneling diode is connected in series with a diode consisting of a P + doped region II (12), a P-doped region I (05) and an N-type substrate (02), and the turn-on voltage of the two diodes connected in series is 1.4V when the body diode of the super-junction power MOSFET is turned on.
3. The super-junction power MOSFET with the integrated tunneling diode of claim 2, wherein the turn-on voltage of the diode formed by the P + doped region I (08), the P type doped region II (06), the N type doped region (03) and the N type substrate (02) is 0.7V when the body diode of the super-junction power MOSFET is turned on.
4. The super-junction power MOSFET of claim 1 wherein the semiconductor material comprises silicon, germanium, gallium arsenide, silicon carbide or gallium nitride.
5. The super-junction power MOSFET of claim 1 wherein the insulating layer material comprises silicon dioxide, silicon nitride or barium strontium titanate.
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| CN112864222B (en) * | 2019-11-27 | 2022-04-12 | 苏州东微半导体股份有限公司 | Semiconductor power device |
| CN112864150B (en) * | 2019-11-27 | 2022-04-15 | 苏州东微半导体股份有限公司 | Super junction power device |
| CN111816697A (en) * | 2020-07-14 | 2020-10-23 | 重庆大学 | IGBT with integrated tunneling diode |
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