CN116013970A - Semiconductor device, method for manufacturing the same, and method for optimizing turn-on voltage rebound - Google Patents
Semiconductor device, method for manufacturing the same, and method for optimizing turn-on voltage rebound Download PDFInfo
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Abstract
The invention provides a semiconductor device, a manufacturing method thereof and an optimization method of turn-on voltage rebound. The semiconductor device includes: a first element portion on the substrate, the first element portion being a working region of an insulated gate bipolar transistor; and a second element portion on the substrate, the second element portion being a working region of a diode; the first element portion includes: a first collector region, a first drift region, a first base region, a second base region, at least one first contact region, and a plurality of first trenches; the second element portion includes: a second collector region, a second drift region, a third base region, and a plurality of second trenches; the semiconductor device further includes: a first contact electrode and a second contact electrode. By adjusting the doping type of the polysilicon gate in the FRD region on the reverse conducting IGBT chip, the FRD anode can generate hole injection faster, so that the FRD can enter a bipolar conducting state as soon as possible, the conducting voltage drop is reduced, and the rebound is eliminated.
Description
Technical Field
The present invention relates to the field of semiconductor technology, and in particular, to a semiconductor device, a method for manufacturing the same, and a method for optimizing turn-on voltage bounce.
Background
IGBT (InsulatedGate Bipolar Transistor ) has high voltage resistant, easy drive control, strong through-current capability, etc. is known as "CPU" in the electric energy conversion system, its rated current grade can reach thousands amperes, and it is widely used in fields such as new energy automobile, rail transit, electric wire netting, etc.. The trench IGBT has a structure including a p+ collector region 1, an n+ buffer layer 7, an N-drift layer 2, an N base region 3, a P base region 4, an n+ emitter region 5, a trench 6, a gate oxide layer 6a, a first extraction electrode 8, and a second extraction electrode 9, as shown in fig. 1. Referring to fig. 1, a gate is formed by backfilling polysilicon in the trench 6 and doping the polysilicon with an N-type impurity such as phosphorus or arsenic. When a positive voltage is applied to the driving end, electrons in the polysilicon gate rapidly flow out of the gate, so that the gate is positively charged, an N-type inversion layer is formed in a channel outside the gate, and the circulation of electrons in the channel is realized, which is the working principle of an IGBT forward trench-type MOS (Metal-Oxide-Semiconductor Field-Effect Transistor, short term of MOSFET, field effect transistor) structure.
To further increase the power density of the device, an anti-parallel diode FRD (Fast Recovery Diode ) may be integrated into the IGBT chip to form a reverse conducting IGBT (Reverse Conducting IGBT, RC-IGBT) having a structure as shown in fig. 2, on which the IGBT region 10 and the FRD region 20 are separated by a dividing line P-P, wherein the IGBT region 10 may include a p+ collector region 11, an n+ buffer layer 17, an N-drift layer 12, an N base region 13, a P base region 14, an n+ emitter region 15, a trench 16 and a gate oxide layer 16a, and the FRD region 20 may include an n+ collector region 21, an n+ buffer layer 27, an N-drift layer 22, an N base region 23, a P base region 24, a trench 26 and a gate oxide layer 26a, and the reverse conducting IGBT further includes a first extraction electrode 80 and a second extraction electrode 90. The reverse conducting IGBT has the capability of forward conduction and reverse conduction, and when in forward conduction, the RC-IGBT works in an IGBT mode, and when in reverse conduction, the RC-IGBT works in an FRD mode.
Reverse conducting IGBTs have a series of outstanding advantages: firstly, the cost of the chip is saved, and compared with the traditional structure with the area ratio of IGBT to FRD chip being 2:1, the IGBT and the FRD in the reverse conducting IGBT can share a terminal area, so that the chip area of 1/3 can be saved; secondly, the high-temperature leakage current is low, and because the main source of the high-temperature leakage current of the chip is a terminal part, and the reverse conducting IGBT shares the terminal and has a back anode short circuit effect, the high-temperature leakage current is greatly reduced compared with the traditional IGBT chip; and thirdly, the chip area is larger, the thermal resistance is lower, the usable working junction temperature is higher, and the anti-surge capacity is greatly improved.
However, the reverse conducting IGBT also introduces some drawbacks due to its structural features. The static performance is mainly represented by forward and reverse conduction voltage rebound (Snap-back) phenomenon. The test curve of the forward conduction voltage rebound phenomenon is shown in fig. 3. When a forward voltage is applied to the anode of the IGBT, the conduction voltage drop of the IGBT is increased firstly and then suddenly rebounded and reduced, and a secondary rebounded phenomenon sometimes exists, so that a conduction voltage drop curve is not smooth, voltage abrupt change is generated when the device is applied, the stability of a circuit system is not facilitated, and the usability of the reverse-conduction IGBT is reduced. Referring to fig. 4A and 4B, the principle of the voltage bounce phenomenon is as follows: because the reverse-conduction IGBT has a back anode short-circuit area, electrons can be conducted from a back N+ area to flow out of an anode after a front MOS channel is opened, and only one carrier works in a MOS working mode at the moment; when the current is large enough, the lateral voltage difference between the n+ region and the p+ region of the back anode is larger than 0.7V, PN junction is conducted, positive holes of the anode are injected into the n-drift region to generate a conductivity modulation effect, the anode is switched from unipolar conduction to bipolar conduction, and the anode is switched from MOS operation mode to IGTB operation mode, so that the conduction voltage drop is reduced, and voltage rebound is generated. Similarly, when the reverse conducting IGBT is in the reverse conducting mode, reverse conducting voltage rebound phenomenon can be generated, the forming principle is similar to that of front rebound, when a front MOS channel is opened, the FRD region is equivalent to that of an anode which is short-circuited, holes cannot be injected, at the moment, the conducting voltage drop is larger, when the current is enough, PN junctions of the anodes of the FRD region are opened, the hole injection forms a conducting modulation effect, the conducting voltage drop is suddenly reduced, and voltage rebound is generated. The stability of the circuit is also affected, and extra electric stress impact is brought to the circuit element, so that the application performance of the device is reduced.
Therefore, a solution is needed to solve the voltage bounce problem of the reverse conducting IGBT.
Disclosure of Invention
The invention mainly aims to provide a semiconductor device, a manufacturing method thereof and an optimization method of turn-on voltage rebound, so as to solve the problem of voltage rebound of a reverse conducting IGBT.
The present invention provides a semiconductor device including: a first element portion on the substrate, the first element portion being a working region of the insulated gate bipolar transistor; and a second element portion on the substrate, the second element portion being a working region of the diode; wherein the first element portion comprises: a first collector region of a second conductivity type, the first collector region being located on the substrate; a first drift region of the first conductivity type, the first drift region being located above the first collector region; a first base region of the first conductivity type, the first base region being located above the first drift region; a second base region of a second conductivity type, the second base region being located above the first drift region; at least one first contact region of the first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region; a plurality of first trenches, each first trench extending from a surface of the first element portion remote from the first collector region through the second base region to the first drift region, each first trench being filled with a filler material of the first conductivity type, wherein at least one first contact region adjoins at least one first trench to form a conductive channel in the second base region along the first trench when the insulated gate bipolar transistor is in operation; wherein the second element portion comprises: a second collector region of the first conductivity type, the second collector region being located on the substrate; a second drift region of the first conductivity type over the second collector region; a third base region of the second conductivity type, the third base region being located above the second drift region; a plurality of second trenches, each second trench extending from a surface of the second element portion remote from the second collector region through the third base region to the second drift region, a filler material in at least one second trench being different from a filler material in the first trench such that the second trench has a lower potential than the first trench; wherein the semiconductor device further comprises: the first contact electrode is electrically connected with at least one first contact region and the second base region; and a second contact electrode electrically connected to the first collector region and the second collector region.
In an embodiment, the second element portion further comprises: and a fourth base region of the first conductivity type, the fourth base region being located above the second drift region.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, comprising: the filling material in the at least one second trench is undoped.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, comprising: the fill material in the at least one second trench is of a second conductivity type.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, comprising: the filler material in the at least one second trench is undoped and the filler material in the at least one second trench is of the second conductivity type.
The invention provides a method for manufacturing a semiconductor device, which comprises the following steps: forming a first element portion on a substrate, the first element portion being a working region of an igbt; and forming a second element portion on the substrate, the second element portion being a working region of the diode; wherein forming a first element portion on a substrate comprises: forming a first collector region of a second conductivity type, the first collector region being located on the substrate; forming a first drift region of the first conductivity type, the first drift region being located above the first collector region; forming a first base region of a first conductivity type, wherein the first base region is positioned above the first drift region; forming a second base region of a second conductivity type, the second base region being located above the first drift region; forming at least one first contact region of the first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region; forming a plurality of first trenches, each first trench extending from a surface of the first element portion remote from the first collector region through the second base region to the first drift region, each first trench being filled with a filler material of the first conductivity type, wherein at least one first contact region adjoins at least one first trench to form a conductive channel in the second base region along the first trench when the insulated gate bipolar transistor is in operation; wherein forming the second element portion on the substrate includes: forming a second collector region of the first conductivity type, the second collector region being located on the substrate; forming a second drift region of the first conductivity type, the second drift region being located above the second collector region; forming a third base region of the second conductivity type, wherein the third base region is positioned above the second drift region; forming a plurality of second trenches, each second trench extending from a surface of the second element portion remote from the second collector region through the third base region to the second drift region, a filler material in at least one second trench being different from a filler material in the first trench such that the second trench has a lower potential than the first trench; wherein the method further comprises: forming a first contact electrode, wherein the first contact electrode is electrically connected with at least one first contact region and a second base region; a second contact electrode is formed, the second contact electrode being electrically connected to the first collector region and the second collector region.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, the method comprising: a mask is provided over the at least one second trench of the second element portion prior to doping the first trench of the first element portion to undoped the filler material in the at least one second trench.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, the method comprising: providing a mask over at least one second trench of the second element portion prior to doping the first trench of the first element portion; a mask is provided over the first trench of the first element portion and over the remaining second trenches of the second element portion before doping the at least one second trench of the second element portion to dope the filling material in the at least one second trench of the second element portion to the second conductivity type.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, the method comprising: providing a mask over at least two second trenches of the second element portion prior to doping the first trenches of the first element portion to undoped filler material in the at least two second trenches; a mask is provided over the first trench of the first element portion and over the remaining second trenches of the at least two second trenches to dope the at least one second trench of the at least two second trenches to the second conductivity type before doping the at least one second trench of the at least two second trenches.
The invention provides an optimization method for conducting voltage rebound of a reverse conducting IGBT chip, which comprises the following steps: and when a first potential is applied to the grid electrode of the IGBT working area of the reverse-conduction IGBT chip, a second potential is applied to the grid electrode of the diode of the reverse-conduction IGBT chip, wherein the second potential is lower than the first potential.
In one embodiment, the first potential is a positive potential and the second potential is a negative potential.
According to the invention, the doping type and potential connection of the polysilicon gate in the FRD area on the reverse conducting IGBT chip are regulated, so that the FRD anode short circuit condition of the chip in the early stage of reverse conduction is improved, and hole injection is generated by the FRD anode faster, so that the FRD enters a bipolar conduction state as soon as possible, the conduction voltage drop is reduced, rebound is eliminated, the conduction voltage drop curve is smoothed, the performance of the chip is close to that of a common IGBT chip, and the comprehensive performance of the chip is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a undue limitation on the invention, wherein:
fig. 1 is a schematic cross-sectional structure of a trench IGBT in the related art;
fig. 2 is a schematic cross-sectional structure of a reverse conducting IGBT according to the related art;
FIG. 3 is a graph showing a voltage rebound phenomenon during forward conduction of a reverse conducting IGBT in the related art;
fig. 4A and fig. 4B are schematic diagrams of voltage rebound phenomenon during forward conduction of the reverse conducting IGBT in the related art;
FIG. 5 is a graph showing the relationship between the gate potential and the flyback voltage of a diode in a reverse-conducting IGBT;
fig. 6 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application;
fig. 7 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application;
fig. 8 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application.
Detailed Description
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The invention will be described in detail below with reference to the drawings in connection with embodiments.
From the above analysis, it is known that the voltage rebound is generated because the unipolar operation phase exists at the early stage of reverse conduction, the drift region has few hole injection, the conductance modulation effect is weak, and the anode PN junction reaches the turn-on voltage later. Therefore, the potential difference at two ends of the anode PN junction of the FRD can be increased as much as possible, the turn-on voltage is reached earlier, and the reverse conducting IGBT can be enabled to enter a bipolar conducting state faster.
Referring to fig. 5, a simulation result curve between the gate polysilicon potential and the rebound voltage of the diode in the reverse conducting IGBT is shown, and as can be seen from fig. 5, when the IGBT structure parameters such as the N-well dosage, the trench spacing, etc. are fixed, the rebound voltage and the gate polysilicon potential form a significant positive correlation. From the simulation result, it can be also verified that the phenomenon of the rebound of the turn-on voltage can be effectively restrained by reducing the grid polysilicon potential of the diode.
The principle of the invention is to increase the potential difference at two ends of the anode PN junction of the FRD area on the reverse-conduction IGBT, so that the PN junction is opened as soon as possible to enter a bipolar conduction mode. The specific measures can be to change the potential of the polysilicon in the FRD region trench gate, undoped or P-type doped treatment can be carried out on the polysilicon in the FRD region trench gate, or the FRD region trench gate is connected to negative potential, so that the potential of the polysilicon in the FRD trench gate is reduced, an electron inversion layer in a channel is correspondingly more difficult to form, the channel short-circuit effect is reduced, the potential difference at the two ends of a PN junction of an anode of the FRD region is larger, hole injection is generated by earlier opening, voltage rebound when FRD is reduced or even eliminated, the turn-on voltage curve is smoothly increased, and the availability of the reverse-conduction IGBT and the stability of the circuit are improved.
Fig. 6 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application; fig. 7 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application; fig. 8 is a schematic cross-sectional structure of a semiconductor device according to an exemplary embodiment of the present application. In fig. 6 to 8, the reverse conducting IGBT is divided into two cross sections bybase:Sub>A vertical cut linebase:Sub>A-base:Sub>A. Although in the present embodiment, they are in the same plane, the two cross sections may not necessarily be placed in the same plane. Region 100 may be referred to as a first element portion, which is an IGBT operating region, and region 200 may be referred to as a second element portion, which is an FRD operating region. The IGBT and the FRD are integrated in parallel on the same silicon chip.
Referring to fig. 6, the present embodiment provides a semiconductor device, which may include: a first element portion 100, the first element portion 100 being located on the substrate, the first element portion 100 being an active region of an insulated gate bipolar transistor; and a second element portion 200, the second element portion 200 being located on the substrate, the second element portion 200 being the active region of the diode.
Wherein the first element portion 100 may comprise: a first collector region 110 of a second conductivity type, the first collector region 110 being located on the substrate; a first drift region 120 of the first conductivity type, the first drift region 120 being located above the first collector region 110; a first base region 130 of the first conductivity type, the first base region 130 being located above the first drift region 120; a second base region 140 of the second conductivity type, the second base region 140 being located over the first drift region 120; at least one first contact region 150 of the first conductivity type, the first contact region 150 being located above the second base region 140, the first contact region 150 having a higher doping concentration than the first base region 130; a plurality of first trenches 160, each first trench 160 extending from a surface of the first element portion 100 remote from the first collector region 110 through the second base region 140 to the first drift region 120, each first trench 160 being filled with a filling material of the first conductivity type, wherein at least one first contact region 150 adjoins at least one first trench 160 to form a conductive channel in the second base region 140 along the first trench 160 when the insulated gate bipolar transistor is in operation;
wherein the second element portion 200 may comprise: a second collector region 210 of the first conductivity type, the second collector region 210 being located on the substrate; a second drift region 220 of the first conductivity type, the second drift region 220 being located above the second collector region 210; a third base region 240 of the second conductivity type, the third base region 240 being located over the second drift region 220; a plurality of second trenches 260, each second trench 260 extending from a surface of the second element portion 200 remote from the second collector region 210 through the third base region 240 to the second drift region 220, a filling material in at least one second trench 260 being different from a filling material in the first trench 160 such that the second trench 260 has a lower potential than the first trench 160;
wherein the semiconductor device may further include: the first contact electrode 800, the first contact electrode 800 is electrically connected with at least one first contact region 150 and the second base region 140; and a second contact electrode 900, the second contact electrode 900 being electrically connected to the first collector region 110 and the second collector region 210.
In this embodiment, the first conductivity type may be N-type, and the second conductivity type may be P-type.
In this embodiment, the first collector region 110 may be a p+ collector region (located in the IGBT region 100), and the second collector region 210 may be an n+ collector region (located in the FRD region 200). The p+ collector region may supply holes for bipolar conduction in the on state and the n+ collector region may supply electrons for bipolar conduction in the on state.
In this embodiment, the first drift region 120 and the second drift region 220 may be the same N-drift region.
In this embodiment, the first base region 130 may provide an N-well, which may serve as a charge storage layer.
In this embodiment, a dielectric layer 160a may be further included between the first trench 160 and the filling material thereof, and a dielectric layer 260a may be further included between the second trench and the filling material thereof, and the dielectric layer may be, for example, an oxide layer or the like. The first trench 160 in the IGBT region 100 is an active trench serving as a trench gate along which a MOS channel is formed by applying a positive voltage in an on state.
In an embodiment, the semiconductor device may further include n+ buffer layers 170 and 270, the n+ buffer layers 170 and 270 being located between the first and second collector regions and the first and second drift regions. The first and second drift regions, the n+ buffer layers 170 and 270, and the second contact electrode may span the IGBT region 100 and the FRD region 200.
In an embodiment, the second element portion 200 may further include: a fourth base region 230 of the first conductivity type, the fourth base region 230 being located above the second drift region 220.
In an embodiment, referring to fig. 6, the filling material in the at least one second trench 260, which is different from the filling material in the first trench 160, may include: the fill material in the at least one second trench 260 is undoped.
In an embodiment, referring to fig. 6, the polysilicon of the IGBT region trench gate may be N-doped and the polysilicon of the FRD region trench gate may be undoped. When a forward voltage signal is applied to the driving end, for example, a 15V positive voltage signal is applied, because the trench gate of the FRD region is not doped, electrons flow out less, so that the potential of the trench gate is far lower than that of the trench gate of the IGBT region, an electron conduction channel is difficult to induce in a third base region on the outer side of the trench gate, PN short circuit effect of an anode is weakened, and therefore an anode PN junction of the FRD region can be opened earlier and hole injection is generated to the first drift region, and the conduction voltage drop of the FRD is reduced. The implementation method of the undoped polysilicon of the trench gate of the FRD region can be that a mask is formed on the surface of the FRD region when the polysilicon in the trench gate of the IGBT region is doped in the manufacturing process of the chip, so that the polysilicon of the trench gate of the IGBT region is doped only.
In an embodiment, referring to fig. 7, the filling material in the at least one second trench 260, which is different from the filling material in the first trench 160, may include: the fill material in the at least one second trench 260 is of the second conductivity type.
In an embodiment, referring to fig. 7, the polysilicon of the trench gate of the IGBT region may be N-doped and the polysilicon of the trench gate of the FRD region may be P-doped. When a forward voltage signal is applied to the driving end, for example, a 15V positive voltage signal is applied, because the trench gate of the FRD region is doped only in a P type mode and free electrons are few, electrons flow out of the trench gate less, so that the potential of the trench gate is far lower than that of the trench gate of the IGBT region, an electron conduction channel is difficult to induce in a third base region on the outer side of the trench gate, PN short circuit effect of an anode is weakened, and therefore, an anode PN junction of the FRD region can be opened earlier and hole injection is generated, and the conduction voltage drop of the FRD is reduced. The implementation method of the process for P-type doping of polysilicon of the FRD region trench gate can comprise the following steps: in the manufacturing process of the chip, when the polysilicon of the trench gate of the IGBT region is doped, a mask is formed on the surface of the FRD region, so that the polysilicon of the trench gate of the IGBT region is doped with N type; and then removing a mask on the surface of the FRD region, forming a mask on the surface of the IGBT region, and carrying out P-type doping on the polysilicon of the trench gate of the FRD region, thereby forming two trench gates with opposite conductivity types. The scheme of the embodiment can make the short-circuit effect of the anode of the FRD zone weaker, the PN junction is opened earlier, and the conduction voltage drop curve is smoother.
In an embodiment, referring to fig. 8, the filling material in the at least one second trench 260, which is different from the filling material in the first trench 160, may include: the filler material in the at least one second trench 260 is undoped and the filler material in the at least one second trench 260 is of the second conductivity type.
In one embodiment, referring to fig. 8, the polysilicon of the trench gate of the FRD region may be doped mixedly, for example, the polysilicon of a portion of the trench gate may be undoped, the polysilicon of a portion of the trench gate may be N-doped, and the polysilicon of a portion of the trench gate may be P-doped, the sequence of the mixedly doping including but not limited to that shown in fig. 8. The process method for implementing the hybrid doping of the embodiment may include: the polysilicon is doped twice for the trench gate of the FRD. The scheme of the embodiment can adjust the electric potential of the FRD trench gate in a larger range according to the requirement, and realize the device performance meeting the design requirement.
The embodiment provides a manufacturing method of a semiconductor device, which may include: forming a first element portion on a substrate, the first element portion being a working region of an igbt; and forming a second element portion on the substrate, the second element portion being a working region of the diode.
Wherein forming a first element portion on a substrate includes: forming a first collector region of a second conductivity type, the first collector region being located on the substrate; forming a first drift region of the first conductivity type, the first drift region being located above the first collector region; forming a first base region of a first conductivity type, wherein the first base region is positioned above the first drift region; forming a second base region of a second conductivity type, the second base region being located above the first drift region; forming at least one first contact region of the first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region; a plurality of first trenches are formed, each first trench extending from a surface of the first element portion remote from the first collector region through the second base region to the first drift region, each first trench being filled with a filler material of the first conductivity type, wherein at least one first contact region adjoins at least one first trench to form a conductive channel in the second base region along the first trench when the insulated gate bipolar transistor is in operation.
Wherein forming the second element portion on the substrate includes: forming a second collector region of the first conductivity type, the second collector region being located on the substrate; forming a second drift region of the first conductivity type, the second drift region being located above the second collector region; forming a third base region of the second conductivity type, wherein the third base region is positioned above the second drift region; a plurality of second trenches are formed, each second trench extending from a surface of the second element portion remote from the second collector region through the third base region to the second drift region, a filler material in at least one second trench being different from a filler material in the first trench such that the second trench has a lower potential than the first trench.
The method of the embodiment further comprises the following steps: forming a first contact electrode, wherein the first contact electrode is electrically connected with at least one first contact region and a second base region; a second contact electrode is formed, the second contact electrode being electrically connected to the first collector region and the second collector region.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method may include: a mask is provided over the at least one second trench of the second element portion prior to doping the first trench of the first element portion to undoped the filler material in the at least one second trench.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method may include: providing a mask over at least one second trench of the second element portion prior to doping the first trench of the first element portion; a mask is provided over the first trench of the first element portion and over the remaining second trenches of the second element portion before doping the at least one second trench of the second element portion to dope the filling material in the at least one second trench of the second element portion to the second conductivity type.
In an embodiment, the filling material in the at least one second trench is different from the filling material in the first trench, and the method may include: providing a mask over at least two second trenches of the second element portion prior to doping the first trenches of the first element portion to undoped filler material in the at least two second trenches; a mask is provided over the first trench of the first element portion and over the remaining second trenches of the at least two second trenches to dope the at least one second trench of the at least two second trenches to the second conductivity type before doping the at least one second trench of the at least two second trenches.
The embodiment provides an optimization method for conducting voltage rebound of a reverse conducting IGBT chip, which can comprise the following steps: and when a first potential is applied to the grid electrode of the IGBT working area of the reverse-conduction IGBT chip, a second potential is applied to the grid electrode of the diode of the reverse-conduction IGBT chip, wherein the second potential is lower than the first potential.
In one embodiment, the first potential is a positive potential and the second potential is a negative potential.
In one embodiment, referring to fig. 6, the polysilicon of the IGBT region trench gate may be N-doped while a negative potential is forced to be applied to the polysilicon of the FRD region trench gate. When the polysilicon of the trench gate of the FRD region is negative potential, a hole inversion layer is induced in the third base region outside the polysilicon, and PN short circuit effect of the anode is weakened, so that the PN junction of the anode of the FRD region can be opened earlier and hole injection is generated, and conduction voltage drop of the FRD is reduced. The implementation of the polysilicon of the trench gate of the FRD region being negative potential may be by connecting it to the negative terminal of the capacitor, etc.
The invention adjusts the doping type and the potential connection of the polysilicon gate of the FRD region on the reverse conducting IGBT chip,
the FRD anode short circuit condition of the chip in the reverse conduction initial stage is improved, and hole injection 5 is generated by the FRD anode faster, so that the FRD enters a bipolar conduction state as soon as possible, the conduction voltage drop is reduced, rebound is eliminated, the conduction voltage drop curve is smooth, the performance of the chip is close to that of a common IGBT chip, and the comprehensive performance of the chip is improved.
It is noted that the terms used herein are used merely to describe particular embodiments and are not intended to limit exemplary embodiments in accordance with the present application, when the terms "comprises" and/or "comprising" are used in this specification, 0 indicates the presence of a feature, step, operation, device, component, and/or combination thereof.
It is noted that the terms "first", "second" in the description and claims of the present application and the drawings "
Etc. are used to distinguish similar objects from each other and are not used to describe a particular order or precedence. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the application described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
It should be understood that the exemplary embodiments in this specification may be embodied in many different forms,
and should not be construed as being limited to the embodiments set forth herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of these exemplary embodiments to those skilled in the art, and should not be construed as limiting the invention.
Claims (11)
1. A semiconductor device, comprising:
a first element portion on the substrate, the first element portion being a working region of an insulated gate bipolar transistor; and
a second element portion on the substrate, the second element portion being a working region of a diode;
wherein the first element portion comprises:
a first collector region of a second conductivity type, the first collector region being located on a substrate;
a first drift region of a first conductivity type, the first drift region being located above the first collector region;
a first base region of a first conductivity type, the first base region being located above the first drift region;
a second base region of a second conductivity type, the second base region being located above the first drift region;
at least one first contact region of the first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region;
a plurality of first trenches, each of which extends from a surface of the first element portion remote from the first collector region through the second base region to the first drift region, each of which is filled with a filling material of a first conductivity type, wherein at least one of the first contact regions adjoins at least one of the first trenches to form a conductive channel in the second base region along the first trenches when the insulated gate bipolar transistor is in operation;
wherein the second element portion comprises:
a second collector region of the first conductivity type, the second collector region being located on the substrate;
a second drift region of the first conductivity type, the second drift region being located above the second collector region;
a third base region of the second conductivity type, the third base region being located above the second drift region;
a plurality of second trenches, each of the second trenches extending from a surface of the second element portion remote from the second collector region through the third base region to the second drift region, a filling material in at least one of the second trenches being different from a filling material in the first trench so that the second trench has a lower potential than the first trench;
wherein the semiconductor device further comprises:
the first contact electrode is electrically connected with at least one first contact region and the second base region;
and a second contact electrode electrically connected to the first collector region and the second collector region.
2. The semiconductor device according to claim 1, wherein the second element portion further includes:
and a fourth base region of the first conductivity type, the fourth base region being located above the second drift region.
3. The semiconductor device of claim 1, wherein the filler material in at least one of the second trenches is different from the filler material in the first trench, comprising:
the filling material in at least one of the second trenches is undoped.
4. The semiconductor device of claim 1, wherein the filler material in at least one of the second trenches is different from the filler material in the first trench, comprising:
the filling material in at least one of the second trenches is of a second conductivity type.
5. The semiconductor device of claim 1, wherein the filler material in at least one of the second trenches is different from the filler material in the first trench, comprising:
the filling material in at least one of the second trenches is undoped and the filling material in at least one of the second trenches is of the second conductivity type.
6. A method of manufacturing a semiconductor device, comprising:
forming a first element portion on a substrate, the first element portion being a working region of an igbt; and
forming a second element portion on the substrate, the second element portion being a working region of a diode; wherein the method comprises the steps of
Forming a first element portion on a substrate, comprising:
forming a first collector region of a second conductivity type, the first collector region being located on a substrate;
forming a first drift region of a first conductivity type, the first drift region being located above the first collector region;
forming a first base region of a first conductivity type, wherein the first base region is positioned above the first drift region;
forming a second base region of a second conductivity type, wherein the second base region is positioned above the first drift region;
forming at least one first contact region of a first conductivity type, the first contact region being located above the second base region, the first contact region having a higher doping concentration than the first base region;
forming a plurality of first trenches, each extending from a surface of the first element portion remote from the first collector region through the second base region to the first drift region, each first trench being filled with a filling material of a first conductivity type, wherein at least one of the first contact regions adjoins at least one of the first trenches to form a conductive channel in the second base region along the first trenches when the insulated gate bipolar transistor is in operation;
wherein forming a second element portion on the substrate includes:
forming a second collector region of the first conductivity type, the second collector region being located on the substrate;
forming a second drift region of the first conductivity type, the second drift region being located above the second collector region;
forming a third base region of a second conductivity type, wherein the third base region is positioned above the second drift region;
forming a plurality of second trenches, each of the second trenches extending from a surface of the second element portion remote from the second collector region through the third base region to the second drift region, a filling material in at least one of the second trenches being different from a filling material in the first trench so that the second trench has a lower potential than the first trench;
wherein the method further comprises:
forming a first contact electrode, wherein the first contact electrode is electrically connected with at least one first contact region and the second base region;
a second contact electrode is formed, the second contact electrode being electrically connected to the first collector region and the second collector region.
7. The method of manufacturing a semiconductor device according to claim 6, wherein a filling material in at least one of the second trenches is different from a filling material in the first trench, the method comprising:
a mask is provided over at least one second trench of the second element portion prior to doping the first trench of the first element portion to undoped filler material in the at least one second trench.
8. The method of manufacturing a semiconductor device according to claim 6, wherein a filling material in at least one of the second trenches is different from a filling material in the first trench, the method comprising:
providing a mask over at least one second trench of the second element portion prior to doping the first trench of the first element portion;
a mask is provided over both the first trench of the first element portion and over the remaining second trenches of the second element portion prior to doping the at least one second trench of the second element portion to dope the filler material in the at least one second trench of the second element portion to a second conductivity type.
9. The method of manufacturing a semiconductor device according to claim 6, wherein a filling material in at least one of the second trenches is different from a filling material in the first trench, the method comprising:
providing a mask over at least two second trenches of the second element portion prior to doping the first trenches of the first element portion to undoped filler material in the at least two second trenches;
a mask is provided over the first trench of the first element portion and over the remaining second trenches of the at least two second trenches of the second element portion prior to doping the at least one of the at least two second trenches to dope the at least one of the at least two second trenches to the second conductivity type.
10. The optimization method of the turn-on voltage rebound of the reverse conducting IGBT chip is characterized by comprising the following steps of:
and when a first potential is applied to the grid electrode of the IGBT working area of the reverse-conduction IGBT chip, a second potential is applied to the grid electrode of the diode of the reverse-conduction IGBT chip, wherein the second potential is lower than the first potential.
11. The optimization method of claim 10, wherein the first potential is a positive potential and the second potential is a negative potential.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116435354A (en) * | 2023-06-12 | 2023-07-14 | 广东巨风半导体有限公司 | Reverse-conduction type insulated gate bipolar transistor, manufacturing method and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN116435354A (en) * | 2023-06-12 | 2023-07-14 | 广东巨风半导体有限公司 | Reverse-conduction type insulated gate bipolar transistor, manufacturing method and device |
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