CN111816697A - IGBT with integrated tunneling diode - Google Patents
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- 229910052732 germanium Inorganic materials 0.000 claims description 3
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
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Abstract
The invention relates to an IGBT device with an integrated tunneling diode, and belongs to the field of semiconductor power devices. The IGBT device includes: the device comprises collector metal, a P-type collector region, an N-type field termination layer, an N-type drift region, a P-type buried layer, an N-type carrier storage layer, a P-type body region, a P + source region, an N + source region, emitter metal, a dielectric isolation region, a gate oxide layer, a polysilicon gate, a floating electrode, a P-type well region and an N + tunneling region. According to the invention, under the conditions that the breakdown voltage of the device is not reduced and the process difficulty of the device is hardly increased, the on-state voltage drop of the device can be reduced by increasing the concentration of the N-type carrier storage layer, and the Miller capacitance and the saturation current of the device can also be reduced.
Description
Technical Field
The invention belongs to the field of semiconductor power devices, and relates to an IGBT with an integrated tunneling diode.
Background
Insulated Gate Bipolar Transistors (IGBTs) are one of the important core devices in the field of power electronics, and are widely used in various fields such as energy conversion, locomotive traction, industrial frequency conversion, automotive electronics, and consumer electronics. Trench gate IGBTs have a lower cell pitch and a lower turn-on voltage drop than planar gate IGBTs. The conduction voltage drop of the device can be further reduced by adding a carrier storage layer below a P type body region of the trench gate IGBT, and the higher the concentration of the carrier storage layer is, the lower the conduction voltage drop of the IGBT is, however, the breakdown voltage of the device is also lower. On the other hand, the carrier storage layer with higher concentration can also increase the saturation current of the device, which is not beneficial to the short-circuit safe operation of the device, and further limits the application of the IGBT device to the fields of higher power, higher efficiency and higher reliability.
Introducing a floating region in an IGBT can also reduce the on-state voltage drop of the device, but this increases the miller capacitance of the device. The larger miller capacitance can seriously degrade the turn-on characteristics of the device. In extreme cases, it causes uncontrollable electromagnetic interference noise and continuous oscillation of the resulting voltage current.
Therefore, there is a need for an IGBT device with low on-state voltage drop, low miller capacitance, and low saturation current, but with higher breakdown voltage and lower process manufacturing difficulty.
Disclosure of Invention
In view of the above, the present invention provides an IGBT with a tunneling diode, that is, a new structure of an IGBT device manufacturing technology is proposed, which can reduce the on-state voltage drop of the device by increasing the concentration of the N-type carrier storage layer, and also can reduce the miller capacitance and saturation current of the device, while keeping the breakdown voltage of the device unchanged. The method achieves the purposes of improving the working efficiency, the power range and the stability of the device while hardly increasing the process manufacturing difficulty of the device.
In order to achieve the purpose, the invention provides the following technical scheme:
an IGBT with an integrated tunneling diode is formed by mutually splicing a plurality of repeated cellular structures and specifically comprises: the field effect transistor comprises a collector metal (01), a P-type collector region (02), an N-type field stop layer (03), an N-type drift region (04), a P-type buried layer (05), an N-type carrier storage layer (06), a P-type body region (07), a P + source region (08), an N + source region (09), an emitter metal (10), a dielectric isolation layer (11), a gate oxide layer (12), a polysilicon gate (13), a floating electrode (14), a P-type well region (15) and an N + tunneling region (16);
the P-type collector region (02) is above the collector metal (01); the N-type field termination layer (03) is arranged above the P-type collector region (02); the N-type drift region (04) is above the N-type field stop layer (03); the P-type buried layer (05), the N-type carrier storage layer (06) and the P-type well region (15) are arranged above the N-type drift region (04); the P-type body region (07) is above the N-type carrier storage layer (06); the P + source region (08), the N + source region (09) and the N + tunneling region (16) are arranged above the P-type body region (07);
the gate oxide layer (12) is surrounded by an N + source region (09), a P-type body region (07), an N-type carrier storage layer (06), a P-type buried layer (05) and a P-type well region (15); the polysilicon gate (13) is surrounded by the gate oxide layer (12);
the emitter metal (10) is above a P + source region (08) and an N + source region (09); the floating electrode (14) is arranged above the P-type well region (15) and the N + tunneling region (16); the dielectric isolation layer (11) is arranged above the N + tunneling region (16), the P + source region (08) and the gate oxide layer (12);
the dielectric isolation layer (11) isolates the emitter metal (10) from the floating electrode (14);
the P + source region (08) and the N + source region (09) are connected with an emitter metal (10); the P-type well region (15) and the N + tunneling region (16) are connected with the floating electrode (14); the N-type carrier storage layer (06), the P-type body region (07), the N + source region (09), the gate oxide layer (12) and the polysilicon gate (13) respectively form a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of the nMOS;
the P + source region (08) and the N + tunneling region (16) form a tunneling diode which is connected with the emitter metal (10) and the floating electrode (14); the N + tunneling region (16) is connected with the P-type well region (15) through a floating electrode (14); the P-type buried layer (05) is connected with an N + tunneling region (16) of the tunneling diode through a P-type well region (15) and a floating electrode (14).
Further, the threshold voltage of tunneling of the tunneling diode is determined by the doping concentrations of the N + tunneling region (16) and the P + source region (08). The higher the doping concentration of the N + tunneling region (16) and the P + source region (08), the lower the threshold voltage at which tunneling occurs, and vice versa.
Further, the tunneling diode clamps the P-type buried layer (05), and the clamping voltage can be adjusted by adjusting the doping concentration of the N + tunneling region (16). Generally, the clamp voltage ranges from 1.4V to 5V.
Further, when the IGBT is blocked, the P-type buried layer (05) is clamped, the N-type carrier storage layer (06) is clamped by the adjacent P-type buried layer (05), and blocking voltage is borne by a PN junction formed by the P-type buried layer (05) and the N-type drift region (04).
Further, when the IGBT is conducted, the potential of the P type buried layer (05) is 0.7V higher than that of the N type carrier storage layer (06), the N type carrier storage layer (06) is clamped, and the clamping voltage ranges from 0.7V to 4.3V.
Further, semiconductor materials include, but are not limited to, silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride.
The invention has the beneficial effects that: according to the invention, under the conditions that the breakdown voltage of the device is not reduced and the process difficulty of the device is hardly increased, the on-state voltage drop of the device can be reduced by increasing the concentration of the N-type carrier storage layer, and the Miller capacitance and the saturation current of the device can also be reduced.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the means of the instrumentalities and combinations particularly pointed out hereinafter.
Drawings
For the purposes of promoting a better understanding of the objects, aspects and advantages of the invention, reference will now be made to the following detailed description taken in conjunction with the accompanying drawings in which:
fig. 1 is a schematic structural diagram of an IGBT device with a tunneling diode according to the present invention;
fig. 2 is a schematic structural diagram of an IGBT device with a tunneling diode corresponding to example 2;
fig. 3 is a schematic structural diagram of an IGBT device with a tunneling diode corresponding to example 3;
fig. 4 is a schematic structural diagram of an IGBT device with a tunneling diode corresponding to example 4;
fig. 5 is a schematic structural diagram of a reverse conducting IGBT device with a tunneling diode corresponding to example 5;
fig. 6 is a schematic structural diagram of a super junction IGBT device with a tunneling diode corresponding to example 6;
FIG. 7 is a graph showing the relationship between the dose of the carrier storage layer (06) and the breakdown voltage and the turn-on voltage drop according to the present invention.
Reference numerals: 01-collector metal, 02-P type collector region, 03-N type field stop layer, 04-N type drift region, 05-P type buried layer, 06-N type carrier storage layer, 07-P type body region, 08-P + source region, 09-N + source region, 10-emitter metal, 11-dielectric isolation region, 12-gate oxide layer, 13-polysilicon gate, 14-floating electrode, 15-P type well region, 16-N + tunneling region, 17-N type collector region, 18-N column drift region and 19-P column drift region.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It should be noted that the drawings provided in the following embodiments are only for illustrating the basic idea of the present invention in a schematic way, and the features in the following embodiments and examples may be combined with each other without conflict.
Wherein the showings are for the purpose of illustrating the invention only and not for the purpose of limiting the same, and in which there is shown by way of illustration only and not in the drawings in which there is no intention to limit the invention thereto; to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
The same or similar reference numerals in the drawings of the embodiments of the present invention correspond to the same or similar components; in the description of the present invention, it should be understood that if there is an orientation or positional relationship indicated by terms such as "upper", "lower", "left", "right", "front", "rear", etc., based on the orientation or positional relationship shown in the drawings, it is only for convenience of description and simplification of description, but it is not an indication or suggestion that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and therefore, the terms describing the positional relationship in the drawings are only used for illustrative purposes, and are not to be construed as limiting the present invention, and the specific meaning of the terms may be understood by those skilled in the art according to specific situations.
Example 1: fig. 1 is a schematic structural diagram of an IGBT device with a tunneling diode, which is formed by mutually splicing a plurality of repeated cell structures, and specifically includes: the field effect transistor comprises a collector metal (01), a P-type collector region (02), an N-type field stop layer (03), an N-type drift region (04), a P-type buried layer (05), an N-type carrier storage layer (06), a P-type body region (07), a P + source region (08), an N + source region (09), an emitter metal (10), a dielectric isolation layer (11), a gate oxide layer (12), a polysilicon gate (13), a floating electrode (14), a P-type well region (15) and an N + tunneling region (16);
the P-type collector region (02) is above the collector metal (01); the N-type field termination layer (03) is arranged above the P-type collector region (02); the N-type drift region (04) is above the N-type field stop layer (03); the P-type buried layer (05), the N-type carrier storage layer (06) and the P-type well region (15) are arranged above the N-type drift region (04); the P-type body region (07) is arranged above the N-type carrier storage layer (06); the P + source region (08), the N + source region (09) and the N + tunneling region (16) are arranged above the P-type body region (07);
the gate oxide layer (12) is surrounded by an N + source region (09), a P-type body region (07), an N-type carrier storage layer (06), a P-type buried layer (05) and a P-type well region (15); the polysilicon gate (13) is surrounded by the gate oxide layer (12);
the emitter metal (10) is above a P + source region (08) and an N + source region (09); the floating electrode (14) is arranged above the P-type well region (15) and the N + tunneling region (16); the dielectric isolation layer (11) is arranged above the N + tunneling region (16), the P + source region (08) and the gate oxide layer (12);
the dielectric isolation layer (11) isolates the emitter metal (10) from the floating electrode (14);
the P + source region (08) and the N + source region (09) are connected with an emitter metal (10); the P-type well region (15) and the N + tunneling region (16) are connected with the floating electrode (14); the N-type carrier storage layer (06), the P-type body region (07), the N + source region (09), the gate oxide layer (12) and the polysilicon gate (13) are respectively used as a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of an nMOS;
the P + source region (08) and the N + tunneling region (16) form a tunneling diode which is connected with the emitter metal (10) and the floating electrode (14); the N + tunneling region (16) is connected with the P-type well region (15) through a floating electrode (14); the P-type buried layer (05) is connected with the tunneling diode through the P-type well region (15) and the floating electrode (14).
Example 2: the invention can also utilize the P-well region (15) to act as a P-buried layer (05), as shown in fig. 2, which further reduces the process difficulty. In this example, the P-type well region (15) surrounds the N-type carrier storage layer (06), and the floating electrode (14) connects the P-type well region (15) with the N + tunneling region (16) of the tunneling diode.
Example 3: the invention can also use only one P-type buried layer (05), and the N-type carrier storage layer (06) close to one side of the N + tunneling region (16) isolates the P-type body region (07) from the P-type well region (15).
Example 4: the invention can also be used only to reduce the device's miller capacitance, as shown in fig. 4. And a P-type body region (07) between the groove gates is connected with an N + tunneling region (16) of the tunneling diode through a floating electrode (14).
Example 5: the present invention can also be applied to a reverse IGBT structure, and an N-type collector region (17) is formed on the P-type collector region (02) side, as shown in fig. 5, and the rest of the structure is the same as that of example 1.
Example 6: the invention can also be used on a super junction IGBT structure, as shown in FIG. 6, wherein a super junction body region composed of an N-column drift region (18) and a P-column drift region (19) replaces the N-type drift region (04) in embodiment 1.
Simulation comparisons were made with the conventional IGBT shown in fig. 4 and the IGBT device with integrated tunneling diode of the present invention shown in fig. 1 using the piece of medical simulation software. In simulation, the floating electrode (14) in the structure shown in fig. 4 is replaced by a dielectric isolation layer (11), so that the integrated tunneling diode can not play a role any more. In the simulation, P typeThe doping concentration of the collector region (02) is 2 x 1017cm-3The thickness was 2 μm. The doping concentration of the N-type field stop layer (03) is 1 multiplied by 1016cm-3The thickness was 5 μm. The doping concentration of the N-type drift region (04) is 6 multiplied by 1013cm-3The thickness was 100. mu.m. The P-type buried layer (05) has a doping concentration of 5 × 1016cm-3The thickness was 2 μm and the width was 3 μm. The doping concentration of the P-type body region (07) is 2 x 1017cm-3The thickness was 3 μm. The doping concentration of the P + source region (08) is 5 multiplied by 1019cm-3The thickness was 0.4. mu.m. The doping concentration of the N + source region (09) is 5 multiplied by 1019cm-3The thickness was 0.4. mu.m. The dielectric isolation layer (11) is made of silicon dioxide and has the thickness of 1 mu m. The thickness of the gate oxide layer (12) is set to 100 nm. The doping concentration of the P-type well region (15) is 1 multiplied by 1019cm-3The thickness was 6 μm and the width was 4 μm. The N + tunneling region (16) has a doping concentration of 5 × 1018cm-3The thickness was 0.4. mu.m. Fig. 7 is a relationship between the dose (doping concentration multiplied by thickness) of the N-type carrier storage layer (06) and the breakdown voltage and the on-voltage drop. It can be seen that as the dosage of the N-type carrier storage layer (06) is increased, the turn-on voltage drop and the breakdown voltage of the conventional IGBT are reduced correspondingly. The conduction voltage drop of the structure provided by the invention is greatly reduced along with the increase of the dosage of the N-type carrier storage layer (06), and the breakdown voltage is kept unchanged.
In the above embodiments, the semiconductor material includes, but is not limited to, silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride.
Finally, the above embodiments are only intended to illustrate the technical solutions of the present invention and not to limit the present invention, and although the present invention has been described in detail with reference to the preferred embodiments, it will be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions, and all of them should be covered by the claims of the present invention.
Claims (5)
1. An IGBT device with an integrated tunneling diode, comprising: the field effect transistor comprises a collector metal (01), a P-type collector region (02), an N-type field stop layer (03), an N-type drift region (04), a P-type buried layer (05), an N-type carrier storage layer (06), a P-type body region (07), a P + source region (08), an N + source region (09), an emitter metal (10), a dielectric isolation layer (11), a gate oxide layer (12), a polysilicon gate (13), a floating electrode (14), a P-type well region (15) and an N + tunneling region (16);
the P-type collector region (02) is above the collector metal (01); the N-type field termination layer (03) is arranged above the P-type collector region (02); the N-type drift region (04) is above the N-type field stop layer (03); the P-type buried layer (05), the N-type carrier storage layer (06) and the P-type well region (15) are arranged above the N-type drift region (04); the P-type body region (07) is arranged above the N-type carrier storage layer (06); the P + source region (08), the N + source region (09) and the N + tunneling region (16) are arranged above the P-type body region (07);
the gate oxide layer (12) is surrounded by an N + source region (09), a P-type body region (07), an N-type carrier storage layer (06), a P-type buried layer (05) and a P-type well region (15); the polysilicon gate (13) is surrounded by the gate oxide layer (12);
the emitter metal (10) is above a P + source region (08) and an N + source region (09); the floating electrode (14) is arranged above the P-type well region (15) and the N + tunneling region (16); the dielectric isolation layer (11) is arranged above the N + tunneling region (16), the P + source region (08) and the gate oxide layer (12);
the dielectric isolation layer (11) isolates the emitter metal (10) from the floating electrode (14);
the P + source region (08) and the N + source region (09) are connected with an emitter metal (10); the P-type well region (15) and the N + tunneling region (16) are connected with the floating electrode (14); the N-type carrier storage layer (06), the P-type body region (07), the N + source region (09), the gate oxide layer (12) and the polysilicon gate (13) are respectively used as a drain terminal, a substrate, a source terminal, an oxide layer and a gate electrode of an nMOS;
the P + source region (08) and the N + tunneling region (16) form a tunneling diode which is connected with the emitter metal (10) and the floating electrode (14); the N + tunneling region (16) is connected with the P-type well region (15) through a floating electrode (14); the P-type buried layer (05) is connected with an N + tunneling region (16) of the tunneling diode through a P-type well region (15) and a floating electrode (14).
2. The IGBT with integrated tunneling diode according to claim 1, wherein the tunneling diode clamps the P-type buried layer (05), the clamping voltage can be adjusted by adjusting the doping concentration of the N + tunneling region (16), and the clamping voltage ranges from 1.4V to 5V.
3. The IGBT with integrated tunneling diode according to claim 2, wherein when the IGBT is blocked, the P-type buried layer (05) is clamped, the N-type carrier storage layer (06) is clamped by the adjacent P-type buried layer (05), and the blocking voltage is borne by a PN junction formed by the P-type buried layer (05) and the N-type drift region (04). The doping concentration of the N-type carrier storage layer (06) can be increased without sacrificing the breakdown voltage of the device.
4. The IGBT with an integrated tunneling diode according to claim 2, wherein when the IGBT is turned on, the potential of the P-type buried layer (05) is 0.7V higher than that of the N-type carrier storage layer (06), and the N-type carrier storage layer (06) is also clamped, with a clamping voltage ranging from 0.7V to 4.3V.
5. The IGBT with an integrated tunneling diode according to claim 1, wherein the semiconductor material comprises silicon, germanium, gallium arsenide, silicon carbide, or gallium nitride.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114256330A (en) * | 2021-12-22 | 2022-03-29 | 电子科技大学 | Super junction IGBT terminal structure |
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| CN114256330A (en) * | 2021-12-22 | 2022-03-29 | 电子科技大学 | Super junction IGBT terminal structure |
| CN114256330B (en) * | 2021-12-22 | 2023-05-26 | 电子科技大学 | Super-junction IGBT terminal structure |
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