CN108365007B - Insulated gate bipolar transistor - Google Patents
Insulated gate bipolar transistor Download PDFInfo
- Publication number
- CN108365007B CN108365007B CN201810368483.9A CN201810368483A CN108365007B CN 108365007 B CN108365007 B CN 108365007B CN 201810368483 A CN201810368483 A CN 201810368483A CN 108365007 B CN108365007 B CN 108365007B
- Authority
- CN
- China
- Prior art keywords
- drift region
- drift
- region
- gate
- igbt
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 229920005591 polysilicon Polymers 0.000 claims abstract description 18
- 239000000463 material Substances 0.000 claims description 21
- 238000000034 method Methods 0.000 claims description 10
- 230000003071 parasitic effect Effects 0.000 abstract description 14
- 230000003647 oxidation Effects 0.000 abstract description 2
- 238000007254 oxidation reaction Methods 0.000 abstract description 2
- 230000003068 static effect Effects 0.000 description 6
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 5
- 229910010271 silicon carbide Inorganic materials 0.000 description 5
- 238000005215 recombination Methods 0.000 description 4
- 230000006798 recombination Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000004904 shortening Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
- H01L29/4925—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention provides an insulated gate bipolar transistor, comprising: a drift region; the P well region is arranged on one side of the drift region; n is a radical of+The emitter is arranged on one side, far away from the drift region, of the P well region; two grooves, each groove is arranged at N+The emitter, the P well region and the drift region penetrate through N+An emitter and a P well region; the groove oxidation layer is arranged in the two grooves and covers the surface of each groove; and each polysilicon gate is filled at one side of the trench oxide layer far away from the drift region and comprises an N-type sub-gate and a P-type sub-gate which are sequentially stacked. The grid electrode of the IGBT provided by the invention is set as a PN junction, so that the parasitic capacitance Cgc between the grid electrode and the collector electrode can be reduced, the turn-on time is shortened, and the turn-on loss is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to an insulated gate bipolar transistor.
Background
At present, an Insulated Gate Bipolar Transistor (IGBT) is a composite fully-controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET), and has the advantages of both high input impedance of the MOSFET device and low conduction voltage drop of a power transistor (i.e., a giant transistor, GTR for short), and because the IGBT has the advantages of small driving power and low saturation voltage drop, the IGBT is widely applied to various fields as a novel power electronic device.
At present, fig. 1 is a cross-sectional structure diagram of a conventional insulated gate bipolar transistor, when an IGBT is turned on, electrons are injected into a drift region 100 from an emitter 300, holes are injected into the drift region 100 from a collector 600, and the electrons and the holes generate a conductance modulation effect in the drift region 100, so that the turn-on voltage drop of the IGBT is low; while when the IGBT is turned off, the holes in the drift region 100 are mainly annihilated by recombination with electrons in the drift region, thereby achieving turn-off of the IGBT.
Disclosure of Invention
The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.
The present invention has been completed based on the following findings of the inventors:
during research, the inventors find that the performance of the IGBT can be divided into dynamic characteristics and static characteristics. The dynamic characteristic is mainly reflected in the switching time of the IGBT, namely the shorter the switching time is, the smaller the switching power consumption of the IGBT is, and the better the dynamic characteristic of the IGBT is; the static characteristic is mainly reflected in the turn-on voltage drop of the IGBT, that is, the lower the turn-on voltage drop is, the lower the on-state power consumption of the IGBT is, and the better the static characteristic of the IGBT is. The switching time of the IGBT is closely related to parasitic capacitance Cge (parasitic capacitance between the gate and the emitter) and Cgc (parasitic capacitance between the gate and the collector), and the smaller the parasitic capacitance, the shorter the on-time of the IGBT. The parasitic capacitance of the IGBT can be reduced by increasing the thickness of the trench oxide layer, but the increase of the thickness of the trench oxide layer causes the threshold voltage of the IGBT to increase, which in turn causes the increase of the turn-on voltage drop and the deterioration of the static characteristics.
The inventors of the present invention have found through intensive research that the gate of the IGBT can be set to a PN junction, and thus, the parasitic capacitance Cgc between the gate and the collector can be reduced, thereby shortening the turn-on time of the IGBT and further reducing the turn-on loss of the IGBT. In addition, the drift region can be designed into a common drift region and a low mobility drift region, so that when the IGBT is switched on, the common drift region provides a channel with smaller resistance for drift of electrons and holes, and the conduction voltage drop of the IGBT cannot be influenced; when the IGBT is turned off, the low mobility drift region can accelerate the recombination speed of electrons and holes, so that the turn-off time of the IGBT is shortened, and the turn-off power consumption of the IGBT is further reduced.
In view of the above, an object of the present invention is to provide an insulated gate bipolar transistor with reduced parasitic capacitance, reduced switching time or no influence on the turn-on voltage.
In a first aspect of the invention, an insulated gate bipolar transistor is presented.
According to an embodiment of the invention, the insulated gate bipolar transistor comprises: a drift region; the P well region is arranged on one side of the drift region; n is a radical of+Emitter, said N+An emitter is arranged on one side, far away from the drift region, of the P well region; two grooves, each groove is arranged on the N+An emitter, the P well region and the drift region, and penetrates through the N+An emitter and the P well region; the trench oxide layer is arranged in the two trenches and covers the surface of each trench; and each polysilicon gate is filled at one side of the groove oxide layer far away from the drift region and comprises an N-type sub-gate and a P-type sub-gate which are sequentially stacked.
The inventor finds that the gate of the insulated gate bipolar transistor in the embodiment of the invention is a PN junction composed of an N-type sub-gate and a P-type sub-gate, so that the parasitic capacitance Cgc between the gate and the collector can be reduced, the turn-on time of the IGBT is shortened on the premise of not increasing the conduction voltage drop, and the turn-on loss of the IGBT is further reduced.
In addition, the insulated gate bipolar transistor according to the above embodiment of the present invention may further have the following additional technical features:
according to an embodiment of the invention, the insulated gate bipolar transistor further comprises: the insulating layer is arranged on the surface, far away from the drift region, of the polysilicon gate, and the orthographic projection of the insulating layer on the drift region covers the orthographic projection of the polysilicon gate on the drift region; p+A collector layer of P+The collector layer is arranged on one side of the drift region far away from the P well region.
According to an embodiment of the present invention, the drift region, the P-well region, and the N are formed+Emitter and said P+The material of the collector layer includes at least one selected from Si and SiC.
According to the embodiment of the invention, the distance from the surface of the N-type sub-gate close to the P-type sub-gate to the bottom wall of the trench is smaller than the distance from the surface of the P-well region close to the drift region to the bottom wall of the trench.
According to the embodiment of the invention, the doping concentration of the N-type sub-gateGreater than 1 x 1018/cm3The doping concentration of the P-type sub-grid is less than 5 x 1017/cm3。
According to an embodiment of the invention, the drift region comprises: two first drift regions in contact with the trenches; a second drift region disposed between the two first drift regions, and a material forming the second drift region is obtained by a low mobility treatment on the material of the first drift regions.
According to an embodiment of the invention, the method of low mobility treatment comprises electron irradiation and ion bombardment.
According to an embodiment of the present invention, a width of the trench is 1.5 micrometers, and a width of the first drift region is 5 micrometers and a width of the second drift region is 2 micrometers.
According to an embodiment of the present invention, the drift region includes a plurality of the second drift regions and a plurality of third drift regions, the plurality of second drift regions and the plurality of third drift regions are distributed between the two first drift regions, and a material of the third drift regions is the same as a material of the first drift regions.
According to an embodiment of the present invention, a width of the trench is 1.5 micrometers, a width of the first drift region is 5 micrometers, and widths of the second drift region and the third drift region are both 0.3 micrometers.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic cross-sectional structure of a prior art IGBT;
fig. 2 is a schematic cross-sectional structure of an insulated gate bipolar transistor according to an embodiment of the present invention;
fig. 3 is a schematic cross-sectional structure of an igbt according to another embodiment of the present invention;
fig. 4 is a schematic cross-sectional structure of an igbt according to another embodiment of the present invention.
Reference numerals
100 drift region
110 first drift region
120 second drift region
130 third drift region
200P well region
300 N+Emitter electrode
410 groove
420 trench oxide layer
431N type sub-gate
432P type sub-gate
440 insulating layer
500 P+Collector electrode
Detailed Description
The following examples of the present invention are described in detail, and it will be understood by those skilled in the art that the following examples are intended to illustrate the present invention, but should not be construed as limiting the present invention. Unless otherwise indicated, specific techniques or conditions are not explicitly described in the following examples, and those skilled in the art may follow techniques or conditions commonly employed in the art or in accordance with the product specifications.
In one aspect of the invention, an insulated gate bipolar transistor is presented.
According to an embodiment of the present invention, referring to fig. 2, the insulated gate bipolar transistor includes: drift region 100, P-well region 200, N+An emitter 300, two trenches 410, a trench oxide layer 420 and two polysilicon gates; wherein, the P-well region 200 is disposed at one side of the drift region 100; n is a radical of+The emitter 300 is arranged on one side of the P-well region 200 far away from the drift region 100; each trench 410 opens at N+Emitter 300, P-well 200, and drift region 100, and through N+An emitter 300 and a P-well region 200; the trench oxide layer 420 is disposed in the two trenches 410 and covers a surface of each trench 410; each polysiliconThe gates are filled on the side of the trench oxide layer 420 far away from the drift region 100, and each polysilicon gate includes an N-type sub-gate 431 and a P-type sub-gate 432 which are sequentially stacked.
The inventor of the present invention has found that the gate of the IGBT can be configured as a PN junction, so that when a gate voltage is applied, the PN junction of the gate is reversely biased, and a capacitor C1 is formed between the N-type polysilicon gate and the P-type polysilicon gate, and a capacitor C2 is formed between the P-type polysilicon gate and the collector. Therefore, the parasitic capacitance Cgc 'between the gate and the collector of the IGBT is equal to the series capacitance of the capacitance C1 to C2, i.e., Cgc' ═ C1 × C2/(C1+ C2). It can be seen that the parasitic capacitance Cgc' of the IGBT is smaller than C2 (i.e., the parasitic capacitance Cgc of the prior art) when the gate of the IGBT is set to the PN junction. Therefore, the polysilicon gate of the IGBT is set as a PN junction, so that the parasitic capacitance Cgc between the gate and the collector of the IGBT can be effectively reduced, the turn-on time of the IGBT is shortened on the premise of not influencing the turn-on voltage, and the turn-on loss of the IGBT is further reduced.
According to an embodiment of the present invention, referring to fig. 3, the insulated gate bipolar transistor may further include an insulation layer 440 and P+A collector layer 500; the insulating layer 440 is disposed on the surface of the polysilicon gate away from the drift region 100, and an orthographic projection of the insulating layer 440 on the drift region 100 covers an orthographic projection of the polysilicon gate on the drift region 100; and P is+ Collector layer 500 is disposed on a side of drift region 100 away from P-well region 200. Therefore, the IGBT with more complete structure and function can be obtained, and the insulating layer 440 can fully protect the polysilicon gate in the manufacturing process or the using process, so that the device stability of the heterojunction silicon carbide insulated gate transistor is better.
According to the embodiment of the present invention, the specific material type for forming the insulated gate bipolar transistor is not particularly limited, and any IGBT substrate commonly used in the art may be used, and those skilled in the art may select the material type according to the specific electrical property requirement of the insulated gate bipolar transistor. In some embodiments of the present invention, drift region 100, P-well region 200, N are formed+ Emitter electrode 300 and P+The collector layer 500 can be made of Si, and thus, a Si-based igbtThe tube has better stability in long-term use, lower voltage and strong adaptability. In other embodiments of the present invention, drift region 100, P-well region 200, N are formed+ Emitter electrode 300 and P+The material of the collector layer 500 may be SiC, so that the voltage resistance of the silicon carbide igbt is better, the current is larger, and the voltage is higher.
According to an embodiment of the present invention, referring to fig. 3, a distance from a surface a of the N-type sub-gate 431 close to the P-type sub-gate 432 to a bottom wall B of the trench 410 is smaller than a distance from a surface C of the P-well region 200 close to the drift region 100 to the bottom wall B of the trench 410, so that the P-type sub-gate 432 is ensured to be lower than the P-well region 200, and thus the conductivity modulation effect can be better controlled by the polysilicon gate composed of the N-type sub-gate 431 and the P-type sub-gate 432.
According to the embodiment of the present invention, the specific doping concentrations of the N-type sub-gate 431 and the P-type sub-gate 432 are not particularly limited as long as the doping concentrations are such that the polysilicon gate forms a PN junction, and those skilled in the art can adjust accordingly according to the actual effect of the PN junction to shorten the turn-on time. In some embodiments of the present invention, the doping concentration of the N-type sub-gate may be greater than 1 x 1018/cm3The doping concentration of the P-type sub-grid can be less than 5 x 1017/cm3Thus, the depletion region between the N-type sub-gate 431 and the P-type sub-gate 432 can be expanded more toward the P-type sub-gate 432, and the depletion region is lower than the P-well region 200, thereby ensuring the turn-on reliability of the IGBT.
According to an embodiment of the present invention, referring to fig. 3, the drift region 100 (not labeled) may include two first drift regions 110 and a second drift region 120, wherein the first drift region 110 is in contact with the trench 410, the second drift region 120 is disposed between the two first drift regions 110, and a material forming the second drift region 120 is obtained by a low mobility process on a material of the first drift region 110. It should be noted that the term "low mobility treatment" herein specifically refers to a treatment that reduces the mobility of electrons and holes in the semiconductor material, and the term "contact" specifically refers to the fact that there is no other structure between the first drift region 110 and the trench 410 and the contact is direct.
The inventor of the present invention finds, through intensive research, that the drift region 100 can be further divided into a first drift region 110 and a second drift region 120, so that when the IGBT is turned on, the first drift region 110 serving as a common drift region can provide a channel with a smaller resistance for drift of electrons and holes, and the turn-on voltage drop of the IGBT is not affected; when the IGBT is turned off, the second drift region 120, which is a drift region with low mobility (i.e., short lifetime of holes and electrons), can accelerate the recombination velocity of electrons and holes, thereby shortening the turn-off time of the IGBT and further reducing the turn-off power consumption of the IGBT.
According to the embodiment of the present invention, the specific method of the low mobility treatment is not particularly limited, and those skilled in the art can select the method accordingly according to the specific substrate type of the igbt. In some embodiments of the present invention, for Si-based or SiC materials, electron irradiation or ion bombardment may be selected as the method of low mobility treatment, and thus, the mobility of electrons and holes in the second drift region 120 may be rapidly and efficiently reduced using the above-described low mobility treatment method.
According to the embodiment of the present invention, the specific width of each of the trench 410, the first drift region 110 and the second drift region 120 in the igbt is not particularly limited as long as the first drift region 110 can contact the trench 410 and the second drift region 120 does not contact the trench 410, and those skilled in the art can adjust accordingly according to the actual turn-off time of the igbt. In some embodiments of the present invention, the width of the trench 410 may be 1.5 microns, the width of the first drift region 110 may be 5 microns, and the width of the second drift region 120 may be 2 microns, so that good dynamic performance and static performance may be obtained simultaneously for a 10 micron size igbt.
According to an embodiment of the present invention, referring to fig. 4, the drift region 100 (not shown) may further include a plurality of second drift regions 120 and a plurality of third drift regions 130, wherein the plurality of second drift regions 120 and the plurality of third drift regions 130 are alternately distributed between two first drift regions 100, and the material of the third drift regions 130 is the same as that of the first drift regions 110, so that the low mobility drift regions distributed at intervals may also accelerate the recombination speed of electrons and holes when being turned off, and the third drift regions 130 between the second drift regions 120 may further ensure the overall stability of the on-state voltage drop when being turned on. It should be noted that "a plurality" herein specifically means two or more.
According to the embodiment of the present invention, the specific width ratio of the second drift region 120 to the third drift region 130 in the igbt is not particularly limited, and those skilled in the art can adjust the width ratio accordingly according to the actual turn-off time of the igbt. In some embodiments of the present invention, for the case that the width of the trench is 1.5 micrometers and the width of the first drift region 110 is 5 micrometers, the widths of the second drift region 120 and the third drift region 130 can both be 0.3 micrometers, so that better dynamic performance and static performance can be obtained for 0 micrometer size insulated gate bipolar transistors at the same time.
According to an embodiment of the present invention, a specific depth of each trench 410 is not particularly limited, for example, 6.5 microns, and the like, and those skilled in the art can design accordingly according to the specific thickness of the P-well region 200, and details thereof are not repeated herein. According to the embodiment of the present invention, the specific distance between the two trenches 410 is also not particularly limited, specifically, for example, 5.5 micrometers, and the like, and those skilled in the art can design the corresponding trench according to the specific electrical performance requirement of the igbt, and details thereof are not described herein.
According to an embodiment of the present invention, the specific thickness of the trench oxide layer 420 is not particularly limited, specifically, for example, 0.15 μm, and the like, and those skilled in the art can design the trench oxide layer accordingly according to the specific electrical performance requirement of the igbt, and details thereof are not described herein again. According to an embodiment of the present invention, a specific material of the trench oxide layer 420 is not particularly limited, such as silicon dioxide, and a person skilled in the art may perform oxidation formation according to a specific type of the substrate, which is not described herein again.
According to the embodiment of the present invention, the specific thickness of the P-well region 200 is not particularly limited, and may be, for example, 2.8 microns, etc., which can be performed by one skilled in the artDesigned accordingly and will not be described in detail herein. According to an embodiment of the present invention, N+The specific thickness of the emitter 300 is also not particularly limited, and specifically, for example, 0.5 μm, etc., and those skilled in the art can design accordingly according to the specific thickness of the P-well region, which is not described herein again. According to an embodiment of the present invention, a specific thickness of the drift region 100 is also not particularly limited, for example, 70 μm, and the like, and those skilled in the art can design the drift region accordingly according to specific electrical performance requirements of the igbt, and details thereof are not described herein again. According to an embodiment of the invention, P+The specific thickness of the collector layer 500 is not particularly limited, and specifically, for example, 0.5 μm, etc., and those skilled in the art can design the collector layer accordingly according to the specific electrical performance requirements of the igbt, which will not be described herein again.
According to an embodiment of the invention, the drift region 100, the P-well region 200, the N+Emitter electrode 300 and P+The specific doping concentration of the collector layer 500 is not particularly limited, and for example, the doping concentration of the drift region 100 may be 1.5 × 1014/cm3The doping concentration of the P well region 200 may be 4 x 1016/cm3、N+The doping concentration of the emitter 300 may be 5 x 1019/cm3Or P+The doping concentration of the clusters may be 1.5 x 1014/cm3The doping concentration of the electrode layer 500 may be 8 x 1017/cm3And so on, those skilled in the art can adjust accordingly according to the actual electrical performance of the igbt, and details thereof are not described herein.
In summary, according to the embodiments of the present invention, the present invention provides an insulated gate bipolar transistor, wherein a gate of the insulated gate bipolar transistor is a PN junction composed of an N-type sub-gate and a P-type sub-gate, so that a parasitic capacitance Cgc between the gate and a collector can be reduced, thereby shortening an on-time of an IGBT without increasing a turn-on voltage drop, and further reducing an on-loss of the IGBT.
In the description of the present invention, it is to be understood that the terms "central," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," "circumferential," and the like are used in the orientations and positional relationships indicated in the drawings for convenience in describing the invention and to simplify the description, and are not intended to indicate or imply that the referenced device or element must have a particular orientation, be constructed and operated in a particular orientation, and are not to be considered limiting of the invention.
Furthermore, the terms "first", "second", "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of the feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.
Claims (5)
1. An insulated gate bipolar transistor, comprising:
a drift region;
the P well region is arranged on one side of the drift region;
N+emitter, said N+An emitter is arranged on one side, far away from the drift region, of the P well region;
two grooves, each groove is arranged on the N+An emitter, the P well region and the drift region, and penetrates through the N+An emitter and the P well region;
the trench oxide layer is arranged in the two trenches and covers the surface of each trench;
each polysilicon gate is filled at one side of the trench oxide layer far away from the drift region, and comprises an N-type sub-gate and a P-type sub-gate which are sequentially stacked;
wherein the drift region includes two first drift regions, a plurality of second drift regions and a plurality of third drift regions, the first drift regions are in contact with the trenches, the plurality of second drift regions and the plurality of third drift regions are distributed between the two first drift regions, and a material forming the second drift regions is obtained by low mobility processing on a material of the first drift regions, a material forming the third drift regions is the same as a material of the first drift regions, and a method of the low mobility processing is electron irradiation;
moreover, the width of the trench is 1.5 micrometers, the width of the first drift region is 5 micrometers, and the widths of the second drift region and the third drift region are both 0.3 micrometers.
2. The insulated gate bipolar transistor of claim 1, further comprising:
the insulating layer is arranged on the surface, far away from the drift region, of the polysilicon gate, and the orthographic projection of the insulating layer on the drift region covers the orthographic projection of the polysilicon gate on the drift region;
P+a collector layer of P+The collector layer is arranged on one side of the drift region far away from the P well region.
3. The igbt of claim 2, wherein the drift region, the P-well region, and the N-well region are formed+Emitter and said P+The material of the collector layer includes at least one selected from Si and SiC.
4. The igbt of claim 1, wherein a distance from a surface of the N-type sub-gate near the P-type sub-gate to a bottom wall of the trench is less than a distance from a surface of the P-well region near the drift region to the bottom wall of the trench.
5. The igbt of claim 1, wherein the N-type sub-gate has a doping concentration greater than 1 x 1018/cm3The doping concentration of the P-type sub-grid is less than 5 x 1017/cm3。
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810368483.9A CN108365007B (en) | 2018-04-23 | 2018-04-23 | Insulated gate bipolar transistor |
| PCT/CN2018/112046 WO2019205539A1 (en) | 2018-04-23 | 2018-10-26 | Insulated gate bipolar transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810368483.9A CN108365007B (en) | 2018-04-23 | 2018-04-23 | Insulated gate bipolar transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108365007A CN108365007A (en) | 2018-08-03 |
| CN108365007B true CN108365007B (en) | 2020-02-28 |
Family
ID=63008944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810368483.9A Expired - Fee Related CN108365007B (en) | 2018-04-23 | 2018-04-23 | Insulated gate bipolar transistor |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN108365007B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2019205539A1 (en) * | 2018-04-23 | 2019-10-31 | 广东美的制冷设备有限公司 | Insulated gate bipolar transistor |
| CN112067967A (en) * | 2020-09-25 | 2020-12-11 | 上海大学 | Device switching loss-based power electronic online reliability state detection device and method |
| CN113571575B (en) * | 2021-06-09 | 2023-01-10 | 松山湖材料实验室 | Silicon carbide power semiconductor device and field effect transistor |
| CN113437141A (en) * | 2021-06-24 | 2021-09-24 | 电子科技大学 | Floating P-region CSTBT device with polysilicon diode grid structure |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102011079747A1 (en) * | 2010-07-27 | 2012-02-02 | Denso Corporation | Semiconductor device with switching element and freewheeling diode, and control method therefor |
| US9041120B2 (en) * | 2013-07-25 | 2015-05-26 | Infineon Technologies Ag | Power MOS transistor with integrated gate-resistor |
| JP6164201B2 (en) * | 2014-11-17 | 2017-07-19 | トヨタ自動車株式会社 | Semiconductor device |
| CN106486538A (en) * | 2015-08-31 | 2017-03-08 | 上海联星电子有限公司 | A kind of reverse blocking IGBT and preparation method thereof |
| CN208077982U (en) * | 2018-04-23 | 2018-11-09 | 广东美的制冷设备有限公司 | insulated gate bipolar transistor |
-
2018
- 2018-04-23 CN CN201810368483.9A patent/CN108365007B/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN108365007A (en) | 2018-08-03 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10170607B2 (en) | Semiconductor device | |
| CN108365007B (en) | Insulated gate bipolar transistor | |
| US9196702B2 (en) | Power semiconductor device and method of manufacturing the same | |
| JP5865618B2 (en) | Semiconductor device | |
| US20150008481A1 (en) | Lateral power semiconductor transistors | |
| TWI575736B (en) | Dual trench-gate igbt structure | |
| US20150187877A1 (en) | Power semiconductor device | |
| US9263560B2 (en) | Power semiconductor device having reduced gate-collector capacitance | |
| WO2022252654A1 (en) | Reverse conducting lateral insulated-gate bipolar transistor | |
| KR101422953B1 (en) | Power semiconductor device and method for manufacturing the same | |
| WO2020054446A1 (en) | Semiconductor device | |
| US20150144989A1 (en) | Power semiconductor device and method of manufacturing the same | |
| US8921945B2 (en) | High-voltage power transistor using SOI technology | |
| US9252212B2 (en) | Power semiconductor device | |
| US20140159104A1 (en) | Semiconductor device | |
| KR20150061201A (en) | Power semiconductor device and method of fabricating the same | |
| US9245986B2 (en) | Power semiconductor device and method of manufacturing the same | |
| US20150187922A1 (en) | Power semiconductor device | |
| US20150144993A1 (en) | Power semiconductor device | |
| CN208077982U (en) | insulated gate bipolar transistor | |
| CN112018172A (en) | Insulated gate bipolar transistor, intelligent power device and electronic product | |
| JP5292157B2 (en) | Horizontal insulated gate bipolar transistor and method of manufacturing the same | |
| JP2017045874A (en) | Semiconductor device | |
| WO2019205539A1 (en) | Insulated gate bipolar transistor | |
| CN113838915B (en) | Trench gate charge storage type IGBT and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20200228 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |