WO2019205539A1

WO2019205539A1 - Insulated gate bipolar transistor

Info

Publication number: WO2019205539A1
Application number: PCT/CN2018/112046
Authority: WO
Inventors: 冯宇翔; 甘弟
Original assignee: 广东美的制冷设备有限公司; 美的集团股份有限公司
Priority date: 2018-04-23
Filing date: 2018-10-26
Publication date: 2019-10-31

Abstract

Provided is an insulated gate bipolar transistor. The insulated gate bipolar transistor comprises: a drift region; a P well region provided at one side of the drift region; an N+ emitter provided at the side of the P well region distant from the drift region; two trenches, each of which is provided in an N+ emitter, the P well region, and the drift region, and penetrates through an N+ emitter and the P well region; a trench oxide layer provided in the two trenches and covering the surface of each trench; two polysilicon gates, each of which is provided at the side of the trench oxide layer distant from the drift region, and comprises an N-type sub-gate and a P-type sub-gate that are sequentially stacked.

Description

Insulated gate bipolar transistor

Priority information

The present application claims priority to and the benefit of the patent application of the Inventions and Utility Models of the Patent Application Nos. 201810368483.9 and 201820585100.9, filed on Apr. 23, 2018, the entire contents of .

Technical field

The present application relates to the field of semiconductor technology, and in particular, the present application relates to an insulated gate bipolar transistor.

Background technique

At present, Insulated Gate Bipolar Transistor (IGBT) is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor (BJT) and an insulated gate field effect transistor (MOSFET). There are advantages of high input impedance of MOSFET devices and low on-voltage drop of power transistors (ie giant transistors, GTR for short). Since IGBT has the advantages of small driving power and reduced saturation voltage, IGBT is a new type of power. Electronic devices are widely used in various fields.

At present, FIG. 1 is a cross-sectional structural view of a conventional insulated gate bipolar transistor. When an IGBT is turned on, electrons are injected from the emitter 300 into the drift region 100, holes are injected from the collector 600 into the drift region 100, electrons and holes. The conductance modulation effect occurs in the drift region 100, so that the on-voltage drop of the IGBT is low; and when the IGBT is turned off, the holes in the drift region 100 are mainly eliminated by recombining electrons in the drift region, thereby achieving the IGBT off. Broken.

Summary of the invention

The present application aims to solve at least one of the technical problems in the related art to some extent.

This application is based on the following findings of the inventors:

The applicant discovered during the research that the performance of the IGBT can be divided into dynamic characteristics and static characteristics. The dynamic characteristics are mainly reflected in the switching time of the IGBT, that is, the shorter the switching time, the smaller the switching power consumption of the IGBT and the better the dynamic characteristics of the IGBT; and the static characteristics are mainly reflected in the conduction voltage drop of the IGBT, that is, the conduction voltage The lower the drop, the lower the on-state power consumption of the IGBT and the better the static characteristics of the IGBT. Among them, the switching time of the IGBT is closely related to the parasitic capacitance Cge (parasitic capacitance between the gate and the emitter) and Cgc (the parasitic capacitance between the gate and the collector), and the smaller the parasitic capacitance, the shorter the turn-on time of the IGBT. . The parasitic capacitance of the IGBT can be reduced by increasing the thickness of the trench oxide layer. However, as the thickness of the trench oxide layer increases, the threshold voltage of the IGBT rises, which causes the on-state voltage drop to rise and the static characteristics to deteriorate.

The inventors of the present application have found through intensive research that the gate of the IGBT can be set as a PN junction, so that the parasitic capacitance Cgc between the gate and the collector can be reduced, thereby shortening the turn-on time of the IGBT, thereby reducing the IGBT. Turn-on loss. Moreover, the drift region can also be designed as a normal drift region and a low mobility drift region. Thus, when the IGBT is turned on, the normal drift region provides a smaller resistance channel for the drift of electrons and holes without affecting the IGBT. The conduction voltage drop; when the IGBT is turned off, the low mobility drift region can accelerate the recombination speed of electrons and holes, thereby shortening the turn-off time of the IGBT, thereby reducing the turn-off power consumption of the IGBT.

In view of the above, it is an object of the present application to provide an insulated gate bipolar transistor that reduces parasitic capacitance, shortens switching time, or does not affect turn-on voltage.

In a first aspect of the present application, the present application proposes an insulated gate bipolar transistor.

According to an embodiment of the present application, the insulated gate bipolar transistor includes: a drift region; a P well region, the P well region is disposed at one side of the drift region; an N ⁺ emitter, the N ⁺ emitter Provided on a side of the P-well region away from the drift region; two trenches, each of the trenches being opened in the N ⁺ emitter, the P-well region, and the drift region, and extending through The N ⁺ emitter and the P well region; a trench oxide layer disposed in the two trenches and covering a surface of each of the trenches; two polysilicon gates Each of the polysilicon gates is filled on a side of the trench oxide layer away from the drift region, and each of the polysilicon gates includes an N-type sub-gate and a P-type sub-gate sequentially stacked .

The inventors have found through research that the gate of the insulated gate bipolar transistor of the embodiment of the present application has a PN junction composed of an N-type sub-gate and a P-type sub-gate, so that the gate and the collector can be reduced. The parasitic capacitance Cgc shortens the turn-on time of the IGBT without increasing the turn-on voltage drop, thereby reducing the turn-on loss of the IGBT.

In addition, the insulated gate bipolar transistor according to the above embodiment of the present application may further have the following additional technical features:

According to an embodiment of the present application, the insulated gate bipolar transistor further includes: an insulating layer disposed on a surface of the polysilicon gate away from the drift region, and the insulating layer is in the drift region orthogonal projection on said polysilicon gate covering orthographic projection on said drift region; P ⁺ collector layer, the P ⁺ collector layer disposed on a side of the drift region away from the P-well region.

According to an embodiment of the present application, a material forming the drift region, the P well region, the N ⁺ emitter, and the P ⁺ collector layer includes at least one selected from the group consisting of Si and SiC.

According to an embodiment of the present application, a material forming the drift region, the P well region, the N ⁺ emitter, and the P ⁺ collector layer is Si.

According to an embodiment of the present application, a material forming the drift region, the P well region, the N ⁺ emitter, and the P ⁺ collector layer is SiC.

According to an embodiment of the present application, a distance of the N-type sub-gate close to a surface of the P-type sub-gate to a bottom wall of the trench is smaller than a surface of the P-well region near the drift region to the The distance from the bottom wall of the trench.

According to an embodiment of the present application, the doping concentration of the N-type sub-gate is greater than 1*10 ¹⁸ /cm ³ , and the doping concentration of the P-type sub-gate is less than 5*10 ¹⁷ /cm ³ .

According to an embodiment of the present application, the drift region includes: two first drift regions, the first drift region is in contact with the trench; and a second drift region, the second drift region is disposed on the two The material between the first drift regions and forming the second drift region is obtained by low mobility processing of the material of the first drift region.

According to an embodiment of the present application, the method of low mobility processing includes electron radiation and ion bombardment.

According to an embodiment of the present application, the width of the trench is 1.5 microns, and the width of the first drift region is 5 microns, and the width of the second drift region is 2 microns.

According to an embodiment of the present application, the drift region includes a plurality of the second drift region and a plurality of third drift regions, and the plurality of second drift regions and the plurality of third drift regions are in the two The first drift regions are spaced apart from each other, and the material of the third drift region is the same as the material of the first drift region.

According to an embodiment of the present application, the groove has a width of 1.5 μm, the first drift region has a width of 5 μm, and the second drift region and the third drift region have a width of 0.3 μm.

According to an embodiment of the present application, the depth of the trench is 6.5 microns and the spacing between the two trenches is 5.5 microns.

According to an embodiment of the present application, the trench oxide layer has a thickness of 0.15 micrometers.

According to an embodiment of the present application, the material forming the trench oxide layer is silicon dioxide.

According to an embodiment of the present application, the P well region has a thickness of 2.8 microns, and the P well region has a doping concentration of 4*10 ¹⁶ /cm ³ .

According to an embodiment of the present application, the N ⁺ emitter has a thickness of 0.5 μm and the N ⁺ emitter has a doping concentration of 5*10 ¹⁹ /cm ³ .

According to an embodiment of the present application, the drift region has a thickness of 70 μm, and the drift region has a doping concentration of 1.5*10 ¹⁴ /cm ³ .

According to an embodiment of the present application, the P ⁺ collector layer has a thickness of 0.5 μm, and the P ⁺ collector layer has a doping concentration of 8*10 ¹⁷ /cm ³ .

DRAWINGS

1 is a schematic cross-sectional structural view of a prior art insulated gate bipolar transistor;

2 is a schematic cross-sectional structural view of an insulated gate bipolar transistor according to an embodiment of the present application;

3 is a schematic cross-sectional structural view of an insulated gate bipolar transistor according to another embodiment of the present application;

4 is a schematic cross-sectional view showing an insulated gate bipolar transistor of another embodiment of the present application.

Reference numeral

100 drift zone

110 first drift zone

120 second drift zone

130 third drift zone

200 P well zone

300 N ⁺ emitter

410 groove

420 groove oxide layer

431 N-type subgate

432 P-type sub-gate

440 insulation

500 P ⁺ collector

detailed description

The embodiments of the present application are described in detail below, and those skilled in the art will understand that the following examples are intended to be illustrative of the present application and should not be construed as limiting. Unless specifically stated otherwise, specific techniques or conditions are not explicitly described in the following examples, and those skilled in the art can carry out according to commonly used techniques or conditions in the art or according to product specifications.

In one aspect of the present application, the present application proposes an insulated gate bipolar transistor.

According to an embodiment of the present application, referring to FIG. 2, the insulated gate bipolar transistor includes a drift region 100, a P well region 200, an N ⁺ emitter 300, two trenches 410, a trench oxide layer 420, and two polysilicon layers. a gate; wherein the P well region 200 is disposed on one side of the drift region 100; the N ⁺ emitter 300 is disposed on a side of the P well region 200 away from the drift region 100; each trench 410 is disposed at the N ⁺ emitter 300, P well region 200 and drift region 100, and through N ⁺ emitter 300 and P well region 200; trench oxide layer 420 is disposed in two trenches 410, and covers the surface of each trench 410; each polysilicon The gate is filled on a side of the trench oxide layer 420 away from the drift region 100, and each of the polysilicon gates includes an N-type sub-gate 431 and a P-type sub-gate 432 which are sequentially stacked.

The inventors of the present application have found through research that the gate of the IGBT can be set to a PN junction. Thus, when a gate voltage is applied, the gate PN junction is reverse biased, and between the N-type polysilicon gate and the P-type polysilicon gate. Corresponding to form a capacitor C1, a capacitance C2 is formed between the P-type polysilicon gate and the collector. Therefore, the parasitic capacitance Cgc' between the gate and the collector of the IGBT is equal to the series capacitance of the capacitor C1 at C2, that is, Cgc' = C1 * C2 / (C1 + C2). It can be seen that after the gate of the IGBT is set to the PN junction, its parasitic capacitance Cgc' is smaller than C2 (i.e., the parasitic capacitance Cgc of the prior art). Therefore, by setting the polysilicon gate of the IGBT as a PN junction, the parasitic capacitance Cgc between the gate and the collector of the IGBT can be effectively reduced, thereby shortening the turn-on time of the IGBT without affecting the on-voltage, and thereby reducing Turn-on loss of small IGBTs.

According to an embodiment of the present application, referring to FIG. 3, the insulated gate bipolar transistor may further include an insulating layer 440 and a P ⁺ collector layer 500; wherein the insulating layer 440 is disposed on a surface of the polysilicon gate away from the drift region 100, and is insulated The orthographic projection of layer 440 on drift region 100 covers the orthographic projection of the polysilicon gate on drift region 100; and P ⁺ collector layer 500 is disposed on the side of drift region 100 away from P-well region 200. In this way, an IGBT with better structure and function can be obtained, and the insulating layer 440 can fully protect the polysilicon gate during the manufacturing process or during use, thereby making the device stability of the heterojunction silicon carbide insulated gate transistor better. .

According to the embodiment of the present application, the specific material type of forming the insulated gate bipolar transistor is not particularly limited, and the IGBT substrate commonly used in the art may be, and those skilled in the art may according to the specific electricity of the insulated gate bipolar transistor. Performance requirements are selected accordingly. In some embodiments of the present application, the material forming the drift region 100, the P well region 200, the N ⁺ emitter 300, and the P ⁺ collector layer 500 may be Si, and thus, the long-term of the silicon-based insulated gate bipolar transistor Better stability, lower voltage and adaptability. In other embodiments of the present application, the material forming the drift region 100, the P well region 200, the N ⁺ emitter 300, and the P ⁺ collector layer 500 may be SiC, such as an insulated gate bipolar transistor of silicon carbide. Better withstand voltage, higher current and higher voltage.

According to an embodiment of the present application, referring to FIG. 3, the distance of the N-type sub-gate 431 near the surface A of the P-type sub-gate 432 to the bottom wall B of the trench 410 is smaller than the surface C of the P-well region 200 near the drift region 100 to The distance of the bottom wall B of the trench 410 is such that the P-type sub-gate 432 is lower than the p-well region 200, so that the polysilicon gate composed of the N-type sub-gate 431 and the P-type sub-gate 432 can be further Good control of the conductance modulation effect.

According to the embodiment of the present application, the specific doping concentration of the N-type sub-gate 431 and the P-type sub-gate 432 is not particularly limited as long as the doping concentration of the concentration enables the polysilicon gate to form a PN junction. Those skilled in the art can adjust accordingly according to the actual effect of shortening the turn-on time of the PN junction. In some embodiments of the present application, the doping concentration of the N-type sub-gate may be greater than 1*10 ¹⁸ /cm ³ , and the doping concentration of the P-type sub-gate may be less than 5*10 ¹⁷ /cm ³ , thus, The depletion region between the N-type sub-gate 431 and the P-type sub-gate 432 is expanded more toward the P-type sub-gate 432, and the depletion region is ensured to be lower than the p-well region 200, thereby ensuring the turn-on of the IGBT. reliability.

According to an embodiment of the present application, referring to FIG. 3, the drift region 100 (not shown) may include two first drift regions 110 and a second drift region 120, wherein the first drift region 110 is in contact with the trench 410, The second drift region 120 is disposed between the two first drift regions 110, and the material forming the second drift region 120 is obtained by low mobility processing of the material of the first drift region 110. It should be noted that “low mobility processing” herein specifically refers to a processing method for reducing the mobility of electrons and holes in the semiconductor material, and “contacting” specifically refers to the first drift region 110 and the trench 410 . There are no other structures and they are directly connected.

The inventors of the present application have found through intensive research that the drift region 100 can also be divided into a first drift region 110 and a second drift region 120. Thus, when the IGBT is turned on, the first drift region 110 as a normal drift region can be an electron. The drift of the hole provides a channel with a small resistance without affecting the on-voltage drop of the IGBT; when the IGBT is turned off, it is the second drift region of the drift region with low mobility (ie, short hole and electron lifetime) 120 can speed up the recombination speed of electrons and holes, thereby shortening the turn-off time of the IGBT, thereby reducing the turn-off power consumption of the IGBT.

According to the embodiment of the present application, the specific method of the low mobility processing is not particularly limited, and those skilled in the art can select accordingly according to the specific substrate type of the insulated gate bipolar transistor. In some embodiments of the present application, for Si-based or SiC materials, the method of low mobility processing may select an electron irradiation method or an ion bombardment method, and thus, the above-described low mobility processing method can quickly and efficiently reduce the second drift. The mobility of electrons and holes in region 120.

According to the embodiment of the present application, the specific width of each of the trenches 410, the first drift region 110, and the second drift region 120 in the insulated gate bipolar transistor is not particularly limited as long as the first drift region 110 can be grooved. The slot 410 is in contact and the second drift region 120 is not in contact with the trench 410. Those skilled in the art can adjust accordingly according to the actual off time of the insulated gate bipolar transistor. In some embodiments of the present application, the width of the trench 410 may be 1.5 microns, and the width of the first drift region 110 may be 5 microns, and the width of the second drift region 120 may be 2 microns, thus, for a size of 10 microns The insulated gate bipolar transistor achieves both good dynamic performance and static performance.

According to an embodiment of the present application, referring to FIG. 4, the drift region 100 (not shown) may further include a plurality of second drift regions 120 and a plurality of third drift regions 130, wherein the plurality of second drift regions 120 are The plurality of third drift regions 130 are phase-distributed between the two first drift regions 100, and the material of the third drift region 130 is the same as the material of the first drift region 110, such that the low mobility drift of the interval distribution The region can also speed up the recombination velocity of electrons and holes during turn-off, and the third drift region 130 between the second drift regions 120 can further ensure the overall stability of the turn-on voltage drop during turn-on. It should be noted that “multiple” in this context specifically refers to two or more.

According to the embodiment of the present application, the specific width ratio of the second drift region 120 and the third drift region 130 in the insulated gate bipolar transistor is not particularly limited, and those skilled in the art can actually according to the actual situation of the insulated gate bipolar transistor. Turn off the time and adjust accordingly. In some embodiments of the present application, for a case where the width of the trench is 1.5 micrometers and the width of the first drift region 110 is 5 micrometers, the widths of the second drift region 120 and the third drift region 130 may both be 0.3 micrometers. In this way, a 10 micron size insulated gate bipolar transistor can achieve better dynamic performance and static performance at the same time.

According to the embodiment of the present application, the specific depth of each trench 410 is not particularly limited, specifically, for example, 6.5 micrometers, etc., and those skilled in the art can accordingly design according to the specific thickness of the P well region 200, and no longer Narration. According to the embodiment of the present application, the specific spacing between the two trenches 410 is also not particularly limited, specifically, for example, 5.5 micrometers, etc., and those skilled in the art can perform corresponding electrical performance requirements according to the insulated gate bipolar transistor. Ground design, no longer repeat here.

According to the embodiment of the present application, the specific thickness of the trench oxide layer 420 is not particularly limited, specifically, for example, 0.15 micrometers, etc., and those skilled in the art can accordingly design according to the specific electrical performance requirements of the insulated gate bipolar transistor. I will not repeat them here. According to the embodiment of the present application, the specific material of the trench oxide layer 420 is also not particularly limited, and specifically, for example, silicon dioxide or the like, the person skilled in the art can perform corresponding oxidation according to the specific kind of the substrate, and no longer Narration.

According to the embodiment of the present application, the specific thickness of the P-well region 200 is not particularly limited, and specifically, for example, 2.8 micrometers or the like, and a person skilled in the art can design correspondingly according to the specific thickness of the P-well region, and details are not described herein again. According to the embodiment of the present application, the specific thickness of the N ⁺ emitter 300 is also not particularly limited, specifically, for example, 0.5 micron, etc., and those skilled in the art can accordingly design according to the specific thickness of the P-well region, and no longer Narration. According to the embodiment of the present application, the specific thickness of the drift region 100 is also not particularly limited, specifically, for example, 70 micrometers, etc., and those skilled in the art can accordingly design according to the specific electrical performance requirements of the insulated gate bipolar transistor. This will not be repeated here. According to the embodiment of the present application, the specific thickness of the P ⁺ collector layer 500 is also not particularly limited, specifically, for example, 0.5 micron, etc., and those skilled in the art can accordingly perform specific electrical performance requirements of the insulated gate bipolar transistor. Design, no longer repeat here.

According to the embodiment of the present application, the specific doping concentration of the drift region 100, the P well region 200, the N ⁺ emitter 300, and the P ⁺ collector layer 500 is not particularly limited. For example, the doping concentration of the drift region 100 may be 1.5*10 ¹⁴ /cm ³ , the doping concentration of the P well region 200 may be 4*10 ¹⁶ /cm ³ , and the doping concentration of the N ⁺ emitter 300 may be 5*10 ¹⁹ /cm ³ or P ⁺ collector The doping concentration of the layer 500 may be 8*10 ¹⁷ /cm ³ , etc., and those skilled in the art may adjust accordingly according to the actual electrical performance of the insulated gate bipolar transistor, and details are not described herein again.

In summary, according to an embodiment of the present application, the present application proposes an insulated gate bipolar transistor whose gate is a PN junction composed of an N-type sub-gate and a P-type sub-gate, thus reducing The parasitic capacitance Cgc between the gate and the collector shortens the turn-on time of the IGBT without increasing the turn-on voltage drop, thereby reducing the turn-on loss of the IGBT.

In the description of the present application, it is to be understood that the terms "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", " Rear, Left, Right, Vertical, Horizontal, Top, Bottom, Inner, Out, Clockwise, Counterclockwise, Axial The orientation or positional relationship of the "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is merely for the convenience of describing the present application and the simplified description, and does not indicate or imply the indicated device or The elements must have a particular orientation, are constructed and operated in a particular orientation, and are therefore not to be construed as limiting.

Moreover, the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, features defining "first", "second", and "third" may include at least one of the features, either explicitly or implicitly. In the description of the present application, the meaning of "a plurality" is at least two, such as two, three, etc., unless specifically defined otherwise.

In the description of the present specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" and the like means a specific feature described in connection with the embodiment or example. A structure, material or feature is included in at least one embodiment or example of the application. In the present specification, the schematic representation of the above terms is not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, various embodiments or examples described in the specification, as well as features of various embodiments or examples, may be combined and combined.

While the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are illustrative and are not to be construed as limiting the scope of the present application. The embodiments are subject to variations, modifications, substitutions and variations.

Claims

An insulated gate bipolar transistor comprising:

Drift zone

a P well region, the P well region being disposed at one side of the drift region;

An N + emitter, the N + emitter being disposed on a side of the P well region away from the drift region;

Two trenches, each of the trenches being open in the N + emitter, the P well region, and the drift region, and extending through the N + emitter and the P well region;

a trench oxide layer, the trench oxide layer being disposed in the two trenches and covering a surface of each of the trenches;

Two polysilicon gates, each of which is filled on a side of the trench oxide layer away from the drift region, and each of the polysilicon gates includes an N-type sub-gate and a stack of N-type gates arranged in sequence P-type sub-gate.
The insulated gate bipolar transistor of claim 1 further comprising:

An insulating layer disposed on a surface of the polysilicon gate away from the drift region, and an orthographic projection of the insulating layer on the drift region covers a positive of the polysilicon gate on the drift region projection;

a P + collector layer, the P + collector layer being disposed on a side of the drift region away from the P well region.
The insulated gate bipolar transistor according to claim 2, wherein a material forming the drift region, the P well region, the N + emitter, and the P + collector layer comprises a material selected from the group consisting of Si and SiC. At least one.
The insulated gate bipolar transistor according to claim 2, wherein a material forming the drift region, the P well region, the N + emitter, and the P + collector layer is Si.
The insulated gate bipolar transistor according to claim 2, wherein a material forming the drift region, the P well region, the N + emitter, and the P + collector layer is SiC.
The insulated gate bipolar transistor according to claim 1, wherein a distance of the N-type sub-gate close to a surface of the P-type sub-gate to a bottom wall of the trench is smaller than the P-well region is closer to the The distance from the surface of the drift region to the bottom wall of the trench.
The insulated gate bipolar transistor according to claim 1, wherein a doping concentration of the N-type sub-gate is greater than 1*10 18 /cm 3 , and a doping concentration of the P-type sub-gate is less than 5*10 17 /cm 3 .
The insulated gate bipolar transistor according to any one of claims 1 to 7, wherein the drift region comprises:

Two first drift regions, the first drift region being in contact with the trench;

a second drift region, the second drift region being disposed between the two first drift regions, and a material forming the second drift region is obtained by processing a material of the first drift region by low mobility of.
The insulated gate bipolar transistor of claim 8, the method of low mobility processing comprising electron radiation and ion bombardment.
The insulated gate bipolar transistor of claim 8, wherein the trench has a width of 1.5 μm, and the first drift region has a width of 5 μm and the second drift region has a width of 2 μm.
The insulated gate bipolar transistor according to claim 8, wherein the drift region includes a plurality of the second drift regions and a plurality of third drift regions, the plurality of second drift regions and the plurality of third regions A drift region is spaced between the two first drift regions, and a material of the third drift region is the same as a material of the first drift region.
The insulated gate bipolar transistor according to claim 11, wherein said trench has a width of 1.5 μm, said first drift region has a width of 5 μm, and said second drift region and said third drift region The width is 0.3 microns.
The insulated gate bipolar transistor of claim 1, wherein the trench has a depth of 6.5 μm and a pitch between the two trenches is 5.5 μm.
The insulated gate bipolar transistor of claim 1, wherein the trench oxide layer has a thickness of 0.15 micrometers.
The insulated gate bipolar transistor according to claim 1, wherein a material for forming the trench oxide layer is silicon dioxide.
The insulated gate bipolar transistor according to claim 1, wherein the P well region has a thickness of 2.8 μm, and the P well region has a doping concentration of 4*10 16 /cm 3 .
The insulated gate bipolar transistor of claim 1, wherein the N + emitter has a thickness of 0.5 μm and the N + emitter has a doping concentration of 5*10 19 /cm 3 .
The insulated gate bipolar transistor of claim 1, wherein the drift region has a thickness of 70 μm and the drift region has a doping concentration of 1.5*10 14 /cm 3 .
The insulated gate bipolar transistor according to claim 2, wherein the P + collector layer has a thickness of 0.5 μm, and the P + collector layer has a doping concentration of 8*10 17 /cm 3 .