JP2020039001A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide a technology capable of reducing a recovery current.SOLUTION: A semiconductor device comprises a semiconductor substrate that has a first principal surface and a second principal surface, and on which a first region where a reflux diode is arranged, a second region where an IGBT is arranged, and a withstanding voltage holding region surrounding the first region and the second region in a plan view are prescribed. The semiconductor substrate comprises: an anode layer having a first conductivity type arranged on the first principal surface in the first region; and a diffusion layer having the first conductivity type arranged on the first principal surface in the withstanding voltage holding region so as to be adjacent to the anode layer. A surface electrode is not in contact with the diffusion layer.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor device such as a power semiconductor device and a method for manufacturing the same.

  Power devices, which are power semiconductor devices, are widely used in fields such as home electric appliances, electric vehicles, and railways, as well as in fields of solar power generation and wind power generation, which are attracting attention as power generation of renewable energy. In these fields, an inductive load such as an induction motor is often driven by an inverter circuit constructed with a power device. In the configuration for driving the inductive load, a return diode (hereinafter, referred to as “FWD”) for returning a current generated by the back electromotive force of the inductive load is provided. Note that a normal inverter circuit includes a plurality of insulated gate bipolar transistors (hereinafter, referred to as “IGBTs”) and a plurality of FWDs.

  However, in the inverter circuit, reduction in size and weight and reduction in cost are strongly desired, and it is not desirable to individually mount a plurality of IGBTs and a plurality of FWDs in the inverter circuit. As one of the solutions, a reverse conducting IGBT (hereinafter, referred to as “RC-IGBT”) in which an IGBT and an FWD are integrated is being developed. Reduction and cost reduction are possible.

  In the RC-IGBT, a p-type collector layer serving as an IGBT and an n-type cathode layer serving as an FWD are provided on a surface of a normal IGBT having no reverse conduction performance where only a p-type collector layer is provided. I have. On the surface of the RC-IGBT opposite to the surface, a p-type base layer as an IGBT, a p-type anode layer as an FWD, and a p-type diffusion layer in a breakdown voltage holding region surrounding these in plan view are arranged. Has been established. The RC-IGBT is disclosed in, for example, Non-Patent Document 1, Patent Documents 1 to 3, and the like.

JP 2008-53648 A JP 2008-103590 A JP 2008-109028 A

Takahashi H, et al, "1200V Reverse Conducting IGBT", Proceeding of ISPSD, 2004, p. 133-136

  However, in the RC-IGBT, when the FWD changes from the on state to the off state, a recovery current flows in a direction opposite to a current (forward current) that normally flows as a diode, and this recovery current causes energy loss. There was a problem that it becomes.

  Therefore, the present invention has been made in view of the above problems, and has as its object to provide a technique capable of reducing a recovery current.

  A semiconductor device according to the present invention includes a first region having a first main surface and a second main surface, in which a return diode is provided, and a second region in which an IGBT (Insulated Gate Bipolar Transistor) is provided; A semiconductor substrate in which a breakdown voltage holding region surrounding the first region and the second region is defined in a plan view; and a surface electrode provided on the first main surface of the first region and the second region. And a back electrode disposed on the second main surface of the first region, the second region, and the breakdown voltage holding region, wherein the semiconductor substrate is disposed on the first main surface of the first region. An anode layer having a first conductivity type, a diffusion layer having the first conductivity type disposed on the first main surface of the breakdown voltage holding region adjacent to the anode layer, and A cathode layer having a second conductivity type, the cathode layer being disposed on the second main surface of one region; Electrode is a non-contact with the diffusion layer.

  According to the present invention, the surface electrode is not in contact with the diffusion layer. Thereby, the recovery current can be reduced.

FIG. 2 is a cross-sectional view illustrating a configuration of the semiconductor device according to the first embodiment; FIG. 14 is a plan view showing a configuration of a semiconductor device according to a second embodiment. FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device according to a third embodiment. FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device according to a fourth embodiment. FIG. 15 is a cross-sectional view illustrating a configuration of a semiconductor device according to a fifth embodiment. FIG. 15 is a cross-sectional view illustrating a configuration of a semiconductor device according to a sixth embodiment. FIG. 21 is a plan view showing a configuration of a semiconductor device according to a seventh embodiment. FIG. 14 is a cross-sectional view illustrating a configuration of a semiconductor device according to a seventh embodiment. FIG. 4 is a plan view illustrating a configuration of a related semiconductor device. FIG. 3 is a cross-sectional view illustrating a configuration of a related semiconductor device.

<Related semiconductor devices>
First, before describing a semiconductor device according to an embodiment of the present invention, a power semiconductor device related thereto (hereinafter, referred to as a “related semiconductor device”) will be described.

  9 is a plan view illustrating a configuration of the related semiconductor device, and FIG. 10 is a cross-sectional view illustrating the configuration along line A1-A2 in FIG.

  As shown in FIG. 9, the related semiconductor device includes an FWD region 1 as a first region in which the FWD is provided, an IGBT region 2 as a second region in which the IGBT is provided, and a breakdown voltage holding region 3. A semiconductor substrate 11 is provided. The two IGBT regions 2 sandwich the FWD region 1 in plan view, and the breakdown voltage holding region 3 surrounds the FWD region 1 and the two IGBT regions 2 in plan view. Further, the related semiconductor device includes a gate pad 51 provided in the IGBT region 2.

  Hereinafter, the first conductivity type is described as n-type, and the second conductivity type is described as p-type. In the following, the first main surface of semiconductor substrate 11 is defined as the upper surface of semiconductor substrate 11 in FIG. 10, and thus the upper surfaces of FWD region 1, IGBT region 2 and breakdown voltage holding region 3. Will be described as the lower surface of the semiconductor substrate 11 in FIG.

  As shown in FIG. 10, the semiconductor substrate 11 of the related semiconductor device includes an n-type drift layer 12, a p-type anode layer 13, a first p-type diffusion layer 14 as a diffusion layer, an n-type buffer layer 15, and an n-type buffer layer 15. A cathode layer 16 and a second p-type diffusion layer 17. Although not shown, the semiconductor substrate 11 includes IGBT components such as an n-type emitter layer, a p-type base layer, and a p-type collector layer.

  The n-type drift layer 12 has a relatively low n-type impurity concentration and is disposed over the FWD region 1, the IGBT region 2 and the breakdown voltage holding region 3.

  The FWD p-type anode layer 13 is provided on the upper surface of the FWD region 1 and is provided on the upper surface of the n-type drift layer 12.

  The n-type emitter layer and the p-type base layer of the IGBT (not shown) are provided on the upper surface of the IGBT region 2 and are provided on the upper surface of the n-type drift layer 12. The n-type emitter layer and the p-type base layer constitute a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) which is a part of the IGBT. The IGBT p-type base layer is adjacent to the FWD p-type anode layer 13.

  The first p-type diffusion layer 14 is provided on the upper surface of the breakdown voltage holding region 3, and is provided on the upper surface of the n-type drift layer 12. The first p-type diffusion layer 14 is adjacent to the p-type anode layer 13 of FWD. The p-type impurity concentration of the first p-type diffusion layer 14 is higher than the impurity concentration of the p-type anode layer 13, and the first p-type diffusion layer 14 is deeper than the impurity of the p-type anode layer 13. . Note that the boundary between the first p-type diffusion layer 14 and the p-type anode layer 13 corresponds to the boundary between the breakdown voltage holding region 3 and the FWD region 1, and the vertically extending dotted line shown in FIG. This shows the boundary of the implantation region when forming the 1p type diffusion layer 14, in other words, the boundary between the mask and the opening region.

  N-type buffer layer 15 is provided on the lower surface of FWD region 1, IGBT region 2 and breakdown voltage holding region 3, and is provided on the lower surface of n-type drift layer 12. The n-type impurity concentration of the n-type buffer layer 15 is higher than the impurity concentration of the n-type drift layer 12.

  The FWD n-type cathode layer 16 is provided on the lower surface of the FWD region 1 and is provided on the lower surface of the n-type buffer layer 15. The n-type cathode layer 16 has an n-type impurity concentration higher than that of the n-type buffer layer 15.

  The p-type collector layer of the IGBT is provided on the lower surface of IGBT region 2 and is provided on the lower surface of n-type buffer layer 15. The p-type collector layer of the IGBT is adjacent to the n-type cathode layer 16 of FWD.

  The second p-type diffusion layer 17 is provided on the lower surface of the breakdown voltage holding region 3, and is provided on the lower surface of the n-type buffer layer 15. The second p-type diffusion layer 17 is adjacent to the FWD n-type cathode layer 16. In the related semiconductor device, an end of the second p-type diffusion layer 17 on the FWD region 1 side projects into the FWD region 1. The length PW between the end of the second p-type diffusion layer 17 on the FWD region 1 side and the vertically extending dotted line shown in FIG. 10 is lower than the first p-type diffusion layer 14 in the n-type drift layer 12. It is larger than the thickness of the part. Thereby, it is possible to suppress carriers from reaching the n-type cathode layer 16 from the first p-type diffusion layer 14 through the n-type drift layer 12. The second p-type diffusion layer 17 has a FLR (Field Limiting Ring) structure, a RESURF (Reduced SURface Field) structure, or the like, but a detailed description of the structure is omitted here.

  The related semiconductor device includes not only the semiconductor substrate 11 described above, but also interlayer insulating films 21 and 23, a gate electrode layer 22 made of polysilicon, a front electrode 24, and a back electrode 25.

  The interlayer insulating film 21 is provided at an end of the semiconductor substrate 11. Gate electrode layer 22 is provided on interlayer insulating film 21, and interlayer insulating film 23 covers gate electrode layer 22.

  Surface electrode 24 is provided on the upper surfaces of FWD region 1, IGBT region 2 and breakdown voltage holding region 3, and is electrically connected to gate pad 51 of FIG. The back surface electrode 25 is provided on the lower surface of the FWD region 1, the IGBT region 2, and the breakdown voltage holding region 3.

  The related semiconductor device configured as described above functions as an RC-IGBT. Specifically, when the IGBT is in the ON state, a current flows from the p-type collector layer to the n-type emitter layer (current from the bottom to the top in FIG. 10). When the IGBT changes from the on state to the off state, a reverse voltage is applied to the RC-IGBT by an inductive load (not shown) connected to the RC-IGBT. As a result, the surface electrode 24 becomes high potential and the FWD is turned on, and the current flowing from the p-type anode layer 13 to the n-type cathode layer 16 (current flowing from top to bottom in FIG. 10), that is, the IGBT is turned on A current flows in the opposite direction to the case. By releasing the reverse voltage in this way, failure due to the reverse voltage is suppressed, and the reverse voltage is effectively used in the inductive load.

  Next, when the IGBT is switched from the off state to the on state, when the FWD is switched from the on state to the off state, carriers such as holes in the p-type anode layer 13 that have been injected up to that point are not removed. For this reason, the recovery current continues to flow for a while in the direction opposite to the current in which the FWD was flowing in the ON state. This recovery current has the same direction as the current to flow in the RC-IGBT when the IGBT is in the ON state, and thus causes an energy loss.

  In particular, in the related semiconductor device described above, the first p-type diffusion layer 14 having a relatively high concentration is adjacent to the p-type anode layer 13. In such a configuration, when the IGBT is switched from the off state to the on state and the FWD is switched from the on state to the off state, holes are injected from the first p-type diffusion layer 14 into the p-type anode layer 13. As a result, the number of holes to be discharged increases, and the current in the direction opposite to the moving direction of the holes, that is, the recovery current indicated by the arrow Irr in FIG. 10 increases. On the other hand, the recovery current can be reduced by providing the second p-type diffusion layer 17 on the lower surface of the breakdown voltage holding region 3 or projecting the second p-type diffusion layer 17 into the FWD region 1. However, it is desired to further reduce the recovery current. Here, as described below, according to the semiconductor devices according to the first to seventh embodiments, the recovery current can be reduced.

<First Embodiment>
FIG. 1 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention. Hereinafter, among the components described in the first embodiment, the same or similar components as those described in the related semiconductor device are denoted by the same reference numerals, and different components will be mainly described.

  As shown in FIG. 1, in the semiconductor device according to the first embodiment, the upper surface of the semiconductor substrate 11 closer to the p-type anode layer 13 than the boundary between the p-type anode layer 13 and the first p-type diffusion layer 14 is formed. A first trench 31 is provided. That is, the first trench 31 is disposed in a portion of the p-type anode layer 13 on the first p-type diffusion layer 14 side without being in contact with the first p-type diffusion layer 14. In the first embodiment, the first trench 31 is formed in the same manner as at least a gate electrode structure (not shown) formed in the FWD region 1 and the IGBT region 2. Therefore, the same electrode layer as the gate electrode layer is provided in the first trench 31 via the same insulating film as the gate insulating film.

  According to the semiconductor device according to the first embodiment as described above, holes are injected from the first p-type diffusion layer 14 into the p-type anode layer 13 when the FWD is switched from the on state to the off state. Can be suppressed. As a result, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer 16 via the p-type anode layer 13 can be reduced.

  In the first embodiment, semiconductor substrate 11 may be made of a semiconductor such as silicon (Si) or a wide band gap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. You may. This is the same in the second and subsequent embodiments.

<Embodiment 2>
FIG. 2 is a plan view showing a configuration of the semiconductor device according to the second embodiment of the present invention. Hereinafter, among the components described in the second embodiment, the same or similar components as those described in the related semiconductor device are denoted by the same reference numerals, and different components will be mainly described.

  As shown in FIG. 2, in the semiconductor device according to the second embodiment, a second trench 32 intersecting with the first trench 31 is provided in the p-type anode layer 13. In the second trench 32, the same electrode layer as the gate electrode layer is provided via the same insulating film as the gate insulating film, similarly to the first trench 31.

  According to the semiconductor device according to the second embodiment as described above, the electric field concentrated below the first trench 31 is dispersed below the second trench 32. As a result, the concentration of the electric field in the trench can be suppressed, so that the breakdown voltage can be increased and the disadvantage of the trench can be suppressed.

<Embodiment 3>
FIG. 3 is a sectional view showing a configuration of the semiconductor device according to the third embodiment of the present invention. Hereinafter, among the components described in the third embodiment, the same or similar components as those described in the related semiconductor device are denoted by the same reference numerals, and different components will be mainly described.

  In the semiconductor device according to the third embodiment, the p-type impurity concentration of p-type anode layer 13 decreases as approaching first p-type diffusion layer 14. As a method of forming an impurity layer having a concentration gradient as the p-type anode layer 13, for example, a generally known VLD (Variation of Lateral Doping) may be used, or other methods may be used. You may.

  According to the semiconductor device according to the third embodiment as described above, the gradient between the p-type anode layer 13 and the first p-type diffusion layer 14 The resistance 33 indicated by the imaginary line 3 can be increased. Thereby, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer via the p-type anode layer 13 can be reduced.

<Embodiment 4>
FIG. 4 is a sectional view showing a configuration of the semiconductor device according to the fourth embodiment of the present invention. Hereinafter, among the components described in the fourth embodiment, the same or similar components as those described in the related semiconductor device are denoted by the same reference numerals, and different components will be mainly described.

  As shown in FIG. 4, in the semiconductor device according to the fourth embodiment, surface electrode 24 is provided above breakdown voltage holding region 3 and is not in contact with first p-type diffusion layer 14. Here, the end on the FWD region 1 side of the interlayer insulating film 23 protrudes into the FWD region 1, and the protruding portion separates the surface electrode 24 from the first p-type diffusion layer 14. The surface electrode 24 is provided on the FWD region 1 and the IGBT region 2, and is in contact with the p-type anode layer 13, the p-type base layer, and the n-type emitter layer.

  According to the semiconductor device according to the fourth embodiment as described above, generation of holes as carriers in first p-type diffusion layer 14 can be suppressed when FWD is on. For this reason, when the FWD is switched from the ON state to the OFF state, it is possible to suppress the injection of holes from the first p-type diffusion layer 14 to the p-type anode layer 13, thereby reducing the recovery current. Can be.

<Embodiment 5>
FIG. 5 is a sectional view showing a configuration of the semiconductor device according to the fifth embodiment of the present invention. Hereinafter, among the components described in the fifth embodiment, the same or similar components as those described in the semiconductor device according to the fourth embodiment are denoted by the same reference numerals, and different components are mainly described. explain.

  As shown in FIG. 5, in the semiconductor device according to the fifth embodiment, the p-type anode layer 13 and the first p-type diffusion layer 14 are separated by a part of the n-type drift layer 12, and the n-type drift layer 12 is separated from the surface electrode 24 by a protruding portion of the interlayer insulating film 23.

  According to the semiconductor device according to the fifth embodiment as described above, the resistance 34 between the p-type anode layer 13 and the first p-type diffusion layer 14 indicated by the imaginary line in FIG. 5 can be increased. . Thereby, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer via the p-type anode layer 13 can be reduced.

<Embodiment 6>
FIG. 6 is a sectional view showing the configuration of the semiconductor device according to the sixth embodiment of the present invention. Hereinafter, among the components described in the sixth embodiment, the same or similar components as those described in the semiconductor device according to the fourth embodiment are denoted by the same reference numerals, and different components are mainly described. explain.

  As shown in FIG. 6, the semiconductor substrate 11 according to the sixth embodiment further includes an n-type isolation region 35, and the isolation region 35 includes a p-type anode layer 13, a first p-type diffusion layer 14, The upper surface of the isolation region 35 is separated from the surface electrode 24 by a protruding portion of the interlayer insulating film 23. In the sixth embodiment, the n-type impurity concentration of the isolation region 35 is higher than that of the n-type drift layer 12.

  According to the semiconductor device according to the sixth embodiment as described above, the number of manufacturing steps is increased by the amount corresponding to the formation of the isolation region 35 as compared with the fifth embodiment, but the p-type anode layer 13 and the first p-type diffusion layer 14 are formed. The resistance value of the resistor 36, which is partially shown by the imaginary line in FIG. 6, can be set to an intended value. Thus, the recovery current can be appropriately reduced.

<Embodiment 7>
FIG. 7 is a plan view illustrating a configuration of a semiconductor device according to a seventh embodiment of the present invention, and FIG. 8 is a cross-sectional view illustrating the configuration. Hereinafter, among the components described in the seventh embodiment, the same or similar components as those described in the related semiconductor device are denoted by the same reference numerals, and different components will be mainly described.

  As shown in FIGS. 7 and 8, in the semiconductor device according to the seventh embodiment, the first p-type diffusion layer 14 includes a plurality of selective injection layers 14a and a semiconductor layer in which the plurality of selective injection layers 14a are provided. 14b. As shown in FIG. 7, the plurality of rectangular selective injection layers 14a are arranged in a staggered pattern along the circumferential direction of the breakdown voltage holding region 3, and as shown in FIG. Is provided above the semiconductor layer 14b. However, the shapes, positions, and ranges of the plurality of selective injection layers 14a are not limited to those shown in FIGS.

  In the seventh embodiment, the first p-type diffusion layer 14 is formed by selectively implanting an impurity in a region where the first p-type diffusion layer 14 is to be formed. As a result, impurities are implanted into the plurality of selective implantation layers 14a, but no impurities are implanted into the semiconductor layer 14b. However, the impurities of the plurality of selective injection layers 14a diffuse into the semiconductor layer 14b by thermal diffusion or the like. Therefore, the impurity concentration of the semiconductor layer 14b is generally lower than the impurity concentration of the selective injection layer 14a. Note that the change in the impurity concentration of the selective injection layer 14a and the semiconductor layer 14b along the direction from one side to the other side may be steep or slow. In the seventh embodiment thus configured, the first p-type diffusion layer 14 has an uneven impurity concentration.

  According to the semiconductor device according to the seventh embodiment described above, the average impurity concentration of the entire first p-type diffusion layer 14 can be lower than the impurity concentration of the selective implantation layer 14a. This makes it possible to suppress the generation of holes in the first p-type diffusion layer 14 when the FWD is in the ON state, so that the recovery current can be reduced.

  In the present invention, each embodiment and each modified example can be freely combined, and each embodiment and each modified example can be appropriately modified or omitted within the scope of the invention.

  Reference Signs List 1 FWD region, 2 IGBT region, 3 breakdown voltage holding region, 11 semiconductor substrate, 13 p-type anode layer, 14 first p-type diffusion layer, 16 n-type cathode layer, 24 surface electrode, 25 back surface electrode, 31 first trench, 32 Second trench, 35 isolation region.

Claims (4)

A first region having a first main surface and a second main surface, in which a return diode is disposed; a second region in which an IGBT (Insulated Gate Bipolar Transistor) is disposed; A semiconductor substrate defining a breakdown voltage holding region surrounding the second region;
A surface electrode disposed on the first main surface of the first region and the second region;
A back electrode disposed on the second main surface of the first region, the second region, and the breakdown voltage holding region;
The semiconductor substrate,
An anode layer having a first conductivity type disposed on the first main surface of the first region;
A diffusion layer having the first conductivity type, the diffusion layer being disposed on the first main surface of the breakdown voltage holding region adjacent to the anode layer;
A cathode layer having a second conductivity type, the cathode layer being disposed on the second main surface of the first region.
The semiconductor device, wherein the surface electrode is not in contact with the diffusion layer. The semiconductor device according to claim 1, wherein:
The surface electrode is also provided on the first main surface of the withstand voltage holding region,
The semiconductor device, wherein an impurity concentration of the anode layer decreases as approaching the diffusion layer. The semiconductor device according to claim 1, wherein:
The surface electrode is also provided on the first main surface of the withstand voltage holding region,
The semiconductor substrate,
A semiconductor device further comprising an isolation region having a second conductivity type, which is disposed on the first main surface and sandwiched between the anode layer and the diffusion layer. A method for manufacturing a semiconductor device, comprising:
The semiconductor device includes:
A first region having a first main surface and a second main surface, in which a return diode is disposed; a second region in which an IGBT (Insulated Gate Bipolar Transistor) is disposed; A semiconductor substrate defining a breakdown voltage holding region surrounding the second region;
A surface electrode disposed on the first main surface of the first region, the second region, and the breakdown voltage holding region;
A back electrode disposed on the second main surface of the first region, the second region, and the breakdown voltage holding region;
The semiconductor substrate,
An anode layer having a first conductivity type disposed on the first main surface of the first region;
A diffusion layer having the first conductivity type, disposed on the first main surface of the breakdown voltage holding region adjacent to the anode layer;
A cathode layer having a second conductivity type, the cathode layer being disposed on the second main surface of the first region.
The diffusion layer is formed by selectively implanting impurities in a region where the diffusion layer is to be formed,
The method of manufacturing a semiconductor device, wherein the surface electrode is not in contact with the diffusion layer.

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