JP6843952B2 - Manufacturing method of semiconductor devices - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor equipment such as power semiconductor device.

Power devices, which are semiconductor devices for electric power, are widely used in fields such as home appliances, electric vehicles, and railways, as well as in the fields of photovoltaic power generation and wind power generation, which are attracting increasing attention as power generation of renewable energy. In these fields, an inverter circuit constructed by a power device often drives an inductive load such as an induction motor. In the configuration for driving the inductive load, a freewheeling diode (hereinafter referred to as “FWD”) for returning the current generated by the back electromotive force of the inductive load is provided. A normal inverter circuit is composed of a plurality of insulated gate bipolar transistors (hereinafter referred to as "IGBT") and a plurality of FWDs.

However, in the inverter circuit, it is strongly desired to reduce the size, weight and cost, and it is not desirable to individually mount a plurality of IGBTs and a plurality of FWDs in the inverter circuit. As one of the solutions, the development of a reverse conduction type IGBT (hereinafter referred to as "RC-IGBT") in which the IGBT and the FWD are integrated is underway, and in the configuration to which they are applied, the mounting area of the semiconductor device is being promoted. It is possible to reduce the cost and reduce the cost.

In RC-IGBT, a p-type collector layer as an IGBT and an n-type cathode layer as an FWD are arranged on a surface on which only the p-type collector layer in a normal IGBT having no reverse conduction performance is arranged. There is. A p-type base layer as an IGBT, a p-type anode layer as an FWD, and a p-type diffusion layer in a pressure-resistant holding region surrounding these are arranged on a surface opposite to the surface of the RC-IGBT. It is installed. The RC-IGBT is disclosed in, for example, Non-Patent Document 1, Patent Documents 1 to 3.

Japanese Unexamined Patent Publication No. 2008-53648 Japanese Unexamined Patent Publication No. 2008-103590 Japanese Unexamined Patent Publication No. 2008-109028

Takahashi H, et al, "1200V Reverse Conducting IGBT", Proceeding of ISPSD, 2004, p. 133-136

However, in RC-IGBT, when the FWD changes from the on state to the off state, a recovery current that is a current opposite to the current that should normally flow as a diode (forward current) flows, and this recovery current causes energy loss. There was a problem that it became.

Therefore, the present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of reducing the recovery current.

In the method for manufacturing a semiconductor device according to the present invention, the semiconductor device has a first main surface and a second main surface, and a first region in which a freewheeling diode is arranged and an IGBT (Insulated Gate Bipolar Transistor) are arranged. A semiconductor substrate in which a provided second region, a withstand voltage holding region surrounding the first region and the second region in a plan view is defined, and the first region , the second region, and the withstand voltage holding region . The semiconductor substrate includes a front surface electrode arranged on the first main surface and a back surface electrode arranged on the second main surface of the first region, the second region, and the withstand voltage holding region. An anode layer having a first conductive type, which is arranged on the first main surface of the first region, and an anode layer which is adjacent to the anode layer and is arranged on the first main surface of the pressure resistance holding region. The diffusion layer having the first conductive type and the cathode layer having the second conductive type arranged on the second main surface of the first region are provided, and one said diffusion layer comprises the diffusion layer. It is formed by injecting impurities into a plurality of regions arranged in a staggered pattern in the region to be formed and thermally diffusing the surface electrode, and the surface electrode is in non-contact with the diffusion layer.

According to the present invention, the surface electrode is in non-contact with the diffusion layer. Thereby, the recovery current can be reduced.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 1. FIG. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 3. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 4. FIG. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 5. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 6. It is a top view which shows the structure of the semiconductor device which concerns on Embodiment 7. It is sectional drawing which shows the structure of the semiconductor device which concerns on Embodiment 7. It is a top view which shows the structure of the related semiconductor device. It is sectional drawing which shows the structure of the related semiconductor device.

<Related semiconductor devices>
First, before explaining the semiconductor device according to the embodiment of the present invention, a power semiconductor device (hereinafter, referred to as “related semiconductor device”) related thereto will be described.

FIG. 9 is a plan view showing the configuration of the related semiconductor device, and FIG. 10 is a cross-sectional view showing the configuration along the lines A1-A2 of FIG.

As shown in FIG. 9, in the related semiconductor device, the FWD region 1 which is the first region in which the FWD is arranged, the IGBT region 2 which is the second region in which the IGBT is arranged, and the withstand voltage holding region 3 are provided. The specified semiconductor substrate 11 is provided. The two IGBT regions 2 sandwich the FWD region 1 in a plan view, and the withstand voltage holding region 3 surrounds the FWD region 1 and the two IGBT regions 2 in a plan view. Further, the related semiconductor device includes a gate pad 51 arranged in the IGBT region 2.

Hereinafter, the first conductive type will be referred to as an n-type, and the second conductive type will be referred to as a p-type. In the following, the first main surface of the semiconductor substrate 11 will be the upper surface of the semiconductor substrate 11 in FIG. 10, and thus the upper surfaces of the FWD region 1, the IGBT region 2 and the withstand voltage holding region 3, respectively, and the second main surface of the semiconductor substrate 11 Will be described as the lower surface of the semiconductor substrate 11 in FIG. 10, and by extension, the lower surfaces of the FWD region 1, the IGBT region 2, and the withstand voltage holding region 3.

As shown in FIG. 10, the semiconductor substrate 11 of the related semiconductor device includes an n-type drift layer 12, a p-type anode layer 13, a first p-type diffusion layer 14 which is a diffusion layer, an n-type buffer layer 15, and n. A mold cathode layer 16 and a second p-type diffusion layer 17 are provided. Although not shown, the semiconductor substrate 11 includes IGBT components such as an n-type emitter layer, a p-type base layer, and a p-type collector layer.

The n-type drift layer 12 has a relatively low concentration of n-type impurities, and is arranged so as to straddle the FWD region 1, the IGBT region 2, and the withstand voltage holding region 3.

The p-type anode layer 13 of the FWD is arranged on the upper surface of the FWD region 1 and is arranged on the upper surface of the n-type drift layer 12.

The n-type emitter layer and p-type base layer of the IGBT (not shown) are arranged on the upper surface of the IGBT region 2 and on the upper surface of the n-type drift layer 12. These n-type emitter layer and p-type base layer constitute a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) that is a part of the IGBT. Further, the p-type base layer of the IGBT is adjacent to the p-type anode layer 13 of the FWD.

The first p-type diffusion layer 14 is arranged on the upper surface of the pressure resistance holding region 3, and is arranged on the upper surface of the n-type drift layer 12. Further, the first p-type diffusion layer 14 is adjacent to the p-type anode layer 13 of the FWD. The p-type impurity concentration of the first p-type diffusion layer 14 is higher than the impurity concentration of the p-type anode layer 13, and the first p-type diffusion layer 14 is deeper than the impurities of the p-type anode layer 13. .. The boundary between the first p-type diffusion layer 14 and the p-type anode layer 13 corresponds to the boundary between the pressure-resistant holding region 3 and the FWD region 1, and the vertically extending dotted lines shown in FIG. 10 are the first. It shows the boundary of the injection region when forming the 1p type diffusion layer 14, in other words, the boundary between the mask and the opening region.

The n-type buffer layer 15 is arranged on the lower surfaces of the FWD region 1, the IGBT region 2, and the withstand voltage holding region 3, and is disposed on the lower surface of the n-type drift layer 12. The concentration of n-type impurities in the n-type buffer layer 15 is higher than the concentration of the impurities in the n-type drift layer 12.

The N-type cathode layer 16 of the FWD is arranged on the lower surface of the FWD region 1 and is arranged on the lower surface of the n-type buffer layer 15. The concentration of n-type impurities in the n-type cathode layer 16 is higher than the concentration of the impurities in the n-type buffer layer 15.

The p-type collector layer of the IGBT is disposed on the lower surface of the IGBT region 2, and is disposed on the lower surface of the n-type buffer layer 15. Further, the p-type collector layer of the IGBT is adjacent to the n-type cathode layer 16 of the FWD.

The second p-type diffusion layer 17 is arranged on the lower surface of the pressure resistance holding region 3, and is arranged on the lower surface of the n-type buffer layer 15. Further, the second p-type diffusion layer 17 is adjacent to the n-type cathode layer 16 of the FWD. In the related semiconductor device, the end portion of the second p-type diffusion layer 17 on the FWD region 1 side protrudes into the FWD region 1. The length PW between the end of the second p-type diffusion layer 17 on the FWD region 1 side and the vertically extending dotted line shown in FIG. 10 is the lower side of the first p-type diffusion layer 14 of the n-type drift layer 12. It is made larger than the thickness of the part. This makes it possible to prevent carriers from reaching the n-type cathode layer 16 from the first p-type diffusion layer 14 through the n-type drift layer 12. The second p-type diffusion layer 17 constitutes a FLR (Field Limiting Ring) structure, a RESURF (REduced SURface Field) structure, or the like, but detailed description of the configuration will be omitted here.

The related semiconductor device includes not only the semiconductor substrate 11 described above, but also interlayer insulating films 21 and 23, a gate electrode layer 22 made of polysilicon, a front electrode 24, and a back electrode 25.

The interlayer insulating film 21 is arranged at the end of the semiconductor substrate 11. The gate electrode layer 22 is arranged on the interlayer insulating film 21, and the interlayer insulating film 23 covers the gate electrode layer 22.

The surface electrode 24 is arranged on the upper surface of the FWD region 1, the IGBT region 2, and the withstand voltage holding region 3, and is electrically connected to the gate pad 51 of FIG. The back surface electrode 25 is arranged on the lower surfaces of the FWD region 1, the IGBT region 2, and the withstand voltage holding region 3.

The related semiconductor device configured as described above functions as an RC-IGBT. Specifically, when the IGBT is in the ON state, a current flowing from the p-type collector layer to the n-type emitter layer (current from the bottom to the top in FIG. 10) flows. When the IGBT goes from the on state to the off state, a reverse voltage is applied to the RC-IGBT by an inductive load (not shown) connected to the RC-IGBT. As a result, the surface electrode 24 side becomes a high potential, the FWD is turned on, and the current from the p-type anode layer 13 to the n-type cathode layer 16 (current from top to bottom in FIG. 10), that is, the IGBT is on. The current flows in the opposite direction to the case. By releasing the reverse voltage in this way, the failure due to the reverse voltage is suppressed, and the reverse voltage is effectively used in the inductive load.

Next, when the IGBT is switched from the off state to the on state and the FWD is switched from the on state to the off state, carriers such as holes of the p-type anode layer 13 that have been injected up to that point are released. Due to this, the recovery current continues to flow for a while in the direction opposite to the current that was flowing when the FWD was in the ON state. This recovery current causes energy loss because it is in the same direction as the current that should flow in the RC-IGBT when the IGBT is in the ON state.

In particular, in the related semiconductor device described above, the first p-type diffusion layer 14 having a relatively high concentration is adjacent to the p-type anode layer 13. In such a configuration, when the IGBT is switched from the off state to the on state and the FWD is switched from the on state to the off state, holes are injected from the first p-type diffusion layer 14 into the p-type anode layer 13. As a result, the number of holes to be discharged increases, so that the current in the direction opposite to the moving direction of the holes, that is, the recovery current shown by the arrow Irr in FIG. 10 increases. On the other hand, it is possible to reduce the recovery current by providing the second p-type diffusion layer 17 on the lower surface of the withstand voltage holding region 3 or by projecting the second p-type diffusion layer 17 into the FWD region 1. However, it is desired to further reduce the recovery current. Here, as described below, the semiconductor device according to the first to seventh embodiments can reduce the recovery current.

<Embodiment 1>
FIG. 1 is a cross-sectional view showing the configuration of the semiconductor device according to the first embodiment of the present invention. Hereinafter, among the components described in the first embodiment, the same or similar components as those described in the related semiconductor device will be designated by the same reference numerals, and different components will be mainly described.

As shown in FIG. 1, in the semiconductor device according to the first embodiment, the upper surface of the semiconductor substrate 11 on the p-type anode layer 13 side of the boundary between the p-type anode layer 13 and the first p-type diffusion layer 14 The first trench 31 is arranged. That is, the first trench 31 is arranged in the portion of the p-type anode layer 13 on the side of the first p-type diffusion layer 14 without being in contact with the first p-type diffusion layer 14. In the first embodiment, the first trench 31 is formed in the same manner as the gate electrode structure (not shown) formed in at least the FWD region 1 and the IGBT region 2. Therefore, the same electrode layer as the gate electrode layer is arranged in the first trench 31 via the same insulating film as the gate insulating film.

According to the semiconductor device according to the first embodiment as described above, when the FWD is switched from the on state to the off state, holes are injected from the first p-type diffusion layer 14 into the p-type anode layer 13. Can be suppressed. As a result, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer 16 via the p-type anode layer 13 can be reduced.

In the first embodiment, the semiconductor substrate 11 may be composed of a semiconductor such as silicon (Si), or may be composed of a wide bandgap semiconductor such as silicon carbide (SiC), gallium nitride (GaN), or diamond. You may. This also applies to the second and subsequent embodiments.

<Embodiment 2>
FIG. 2 is a plan view showing the configuration of the semiconductor device according to the second embodiment of the present invention. Hereinafter, among the components described in the second embodiment, the same or similar components as those described in the related semiconductor device will be designated by the same reference numerals, and different components will be mainly described.

As shown in FIG. 2, in the semiconductor device according to the second embodiment, the p-type anode layer 13 is provided with a second trench 32 that intersects with the first trench 31. In the second trench 32, the same electrode layer as the gate electrode layer is arranged through the same insulating film as the gate insulating film, as in the first trench 31.

According to the semiconductor device according to the second embodiment as described above, the electric field concentrated on the lower side of the first trench 31 is dispersed on the lower side of the second trench 32. As a result, it is possible to suppress the concentration of the electric field in the trench, so that the pressure resistance can be enhanced and the demerit of the trench can be suppressed.

<Embodiment 3>
FIG. 3 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. Hereinafter, among the components described in the third embodiment, the same or similar components as those described in the related semiconductor device will be designated by the same reference numerals, and different components will be mainly described.

In the semiconductor device according to the third embodiment, the concentration of p-type impurities in the p-type anode layer 13 decreases as it approaches the first p-type diffusion layer 14. As a method for forming an impurity layer having a concentration gradient as the p-type anode layer 13, for example, a generally known VLD (Variation of Lateral Doping) may be used, or other methods may be used. You may.

According to the semiconductor device according to the third embodiment as described above, the figure between the p-type anode layer 13 and the first p-type diffusion layer 14 is provided by providing a gradient in the concentration of the p-type anode layer 13. The resistance 33 indicated by the imaginary line of 3 can be increased. As a result, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer via the p-type anode layer 13 can be reduced.

<Embodiment 4>
FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the fourth embodiment of the present invention. Hereinafter, among the components described in the fourth embodiment, the same or similar components as those described in the related semiconductor device will be designated by the same reference numerals, and different components will be mainly described.

As shown in FIG. 4, in the semiconductor device according to the fourth embodiment, the surface electrode 24 is arranged above the withstand voltage holding region 3 and is not in contact with the first p-type diffusion layer 14. Here, the end of the interlayer insulating film 23 on the FWD region 1 side protrudes into the FWD region 1, and the surface electrode 24 and the first p-type diffusion layer 14 are separated by the protruding portion. The surface electrode 24 is arranged on the FWD region 1 and the IGBT region 2, and is in contact with the p-type anode layer 13, the p-type base layer, and the n-type emitter layer.

According to the semiconductor device according to the fourth embodiment as described above, it is possible to suppress the generation of holes as carriers in the first p-type diffusion layer 14 when the FWD is in the ON state. Therefore, when the FWD is switched from the on state to the off state, it is possible to suppress the injection of holes from the first p-type diffusion layer 14 into the p-type anode layer 13, so that the recovery current can be reduced. Can be done.

<Embodiment 5>
FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the fifth embodiment of the present invention. Hereinafter, among the components described in the fifth embodiment, the same or similar components as those described in the semiconductor device according to the fourth embodiment are designated by the same reference numerals, and different components are mainly referred to. explain.

As shown in FIG. 5, in the semiconductor device according to the fifth embodiment, the p-type anode layer 13 and the first p-type diffusion layer 14 are separated by a part of the n-type drift layer 12, and the n-type drift layer The portion of 12 is separated from the surface electrode 24 by a protruding portion of the interlayer insulating film 23.

According to the semiconductor device according to the fifth embodiment as described above, the resistance 34 shown by the imaginary line in FIG. 5 between the p-type anode layer 13 and the first p-type diffusion layer 14 can be increased. .. As a result, the recovery current flowing from the first p-type diffusion layer 14 to the n-type cathode layer via the p-type anode layer 13 can be reduced.

<Embodiment 6>
FIG. 6 is a cross-sectional view showing the configuration of the semiconductor device according to the sixth embodiment of the present invention. Hereinafter, among the components described in the sixth embodiment, the same or similar components as those described in the semiconductor device according to the fourth embodiment are designated by the same reference numerals, and different components are mainly referred to. explain.

As shown in FIG. 6, the semiconductor substrate 11 according to the sixth embodiment further includes a separation region 35 having an n-type, and the separation region 35 includes a p-type anode layer 13 and a first p-type diffusion layer 14. It is arranged on the upper surface of the semiconductor substrate 11 so as to be sandwiched between the two, and the upper portion of the separation region 35 is separated from the surface electrode 24 by the protruding portion of the interlayer insulating film 23. In the sixth embodiment, the concentration of n-type impurities in the separation region 35 is higher than the concentration of the impurities in the n-type drift layer 12.

According to the semiconductor device according to the sixth embodiment as described above, the number of manufacturing steps is increased as compared with the fifth embodiment by the amount of forming the separation region 35, but the p-type anode layer 13 and the first p-type diffusion layer 14 The resistance value of the resistor 36, which is partially shown by the imaginary line in FIG. 6, can be set to the intended value. Thereby, the recovery current can be appropriately reduced.

<Embodiment 7>
FIG. 7 is a plan view showing the configuration of the semiconductor device according to the seventh embodiment of the present invention, and FIG. 8 is a cross-sectional view showing the configuration. Hereinafter, among the components described in the seventh embodiment, the same or similar components as those described in the related semiconductor device will be designated by the same reference numerals, and different components will be mainly described.

As shown in FIGS. 7 and 8, in the semiconductor device according to the seventh embodiment, the first p-type diffusion layer 14 is a semiconductor layer in which a plurality of selective injection layers 14a and a plurality of selective injection layers 14a are arranged. 14b and is included. As shown in FIG. 7, the plurality of rectangular selective injection layers 14a are arranged in a staggered pattern along the circumferential direction of the pressure resistance holding region 3, and as shown in FIG. 8, the selective injection layers 14a are arranged. Is disposed above the semiconductor layer 14b. However, the shapes, positions and ranges of the plurality of selective injection layers 14a are not limited to those shown in FIGS. 7 and 8.

In the seventh embodiment, the first p-type diffusion layer 14 is formed by selectively injecting impurities in the region where the first p-type diffusion layer 14 should be formed. As a result, impurities are injected into the plurality of selective injection layers 14a, but impurities are not injected into the semiconductor layer 14b. However, impurities in the plurality of selective injection layers 14a diffuse into the semiconductor layer 14b due to thermal diffusion or the like. Therefore, the impurity concentration of the semiconductor layer 14b is generally lower than the impurity concentration of the selective injection layer 14a. The change in impurity concentration in the direction from one to the other in the selective injection layer 14a and the semiconductor layer 14b may be steep or slow. In the seventh embodiment configured as described above, the impurity concentration of the first p-type diffusion layer 14 becomes non-uniform.

According to the semiconductor device according to the seventh embodiment as described above, the average impurity concentration of the entire first p-type diffusion layer 14 can be made lower than the impurity concentration of the selective injection layer 14a. As a result, the generation of holes in the first p-type diffusion layer 14 can be suppressed when the FWD is on, so that the recovery current can be reduced.

In the present invention, each embodiment and each modification can be freely combined, and each embodiment and each modification can be appropriately modified or omitted within the scope of the invention.

1 FWD region, 2 IGBT region, 3 breakdown voltage holding region, 11 semiconductor substrate, 13 p-type anode layer, 14 1st p-type diffusion layer, 16 n-type cathode layer, 24 front electrode, 25 back electrode, 31 first trench, 32 Second trench, 35 separation area.

Claims (1)

It is a manufacturing method of semiconductor devices.
The semiconductor device is
A first region having a first main surface and a second main surface and a freewheeling diode is arranged, a second region in which an IGBT (Insulated Gate Bipolar Transistor) is arranged, the first region and the first region in a plan view. A semiconductor substrate in which a withstand voltage holding region surrounding the second region is defined, and
A surface electrode disposed on the first main surface of the first region, the second region, and the pressure resistance holding region, and
A back surface electrode arranged on the second main surface of the first region, the second region, and the pressure resistance holding region is provided.
The semiconductor substrate is
An anode layer having a first conductive type, which is arranged on the first main surface of the first region, and
A diffusion layer having the first conductive type, which is arranged on the first main surface of the pressure-resistant holding region adjacent to the anode layer, and
A cathode layer having a second conductive type, which is arranged on the second main surface of the first region, is provided.
One of the diffusion layers is formed by injecting impurities into a plurality of regions arranged in a staggered pattern in the region where the diffusion layer should be formed and thermally diffusing the layers.
A method for manufacturing a semiconductor device, wherein the surface electrode is in non-contact with the diffusion layer.

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