JP2004363327A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve a thermal reliability of a semiconductor device having an insulation gate structure by reducing a temperature imbalance in the plane of a chip to raise the uniformity of temperature distribution. <P>SOLUTION: Unit cells 4 are spaced widely in a central portion 11 of the chip which has a large calorific value and a bad heat dissipation while they are arranged close to each other in the periphery 12 of the chip which has a small calorific value and a good heat dissipation. Thus, base layers are arranged at different intervals in the central portion 11 and the periphery 12 of the chip. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more particularly to a power semiconductor device having an insulated gate structure, for example, an insulated gate bipolar transistor (IGBT) and an insulated gate field effect transistor (MOSFET).
[0002]
[Prior art]
FIG. 13 is a plan view schematically showing the arrangement of one unit cell of an IGBT in a conventional semiconductor device. In FIG. 13, reference numeral 1 denotes a semiconductor chip, reference numeral 2 denotes an emitter pad, and reference numeral 3 denotes a gate pad. Each of the plurality of broken lines indicated by reference numeral 4 represents a unit cell 4. Reference numeral 5 denotes a pressure-resistant edge portion. In all the accompanying drawings, the same components are denoted by the same reference numerals.
[0003]
As shown in FIG. 13, the conventional unit cells 4 are regularly arranged over the entire surface of the chip 1. That is, in the case of, for example, a stripe-shaped arrangement, the unit cells 4 are arranged at equal intervals both in the central portion and in the peripheral portion of the chip 1. Such a regular arrangement is the same whether the emitter structure is a planar structure or a trench structure. The same applies to a power MOSFET.
[0004]
FIG. 14 is a diagram schematically showing a temperature distribution and a heat propagation path in the IGBT chip. In FIG. 14, reference numeral 6 denotes an active portion in which unit cells are arranged, reference numeral 7 denotes an IGBT, and reference numeral 8 denotes a solder layer that joins the chip 1 and the mounting board 9. As shown in FIG. 14, the temperature distribution in the chip has the highest temperature at the center of the chip, and has a mountain-like distribution in which the temperature decreases toward the periphery of the chip.
[0005]
Such a temperature difference occurs due to a balance between heat generation due to current flowing through the chip 1 and heat radiation from the collector electrode 7 to the mounting substrate 9 via the solder layer 8. The only heat path that contributes to heat dissipation in the center of the chip is a path (longitudinal path) through which heat is mainly transmitted toward the collector electrode 7 in the depth direction of the chip 1.
[0006]
On the other hand, in addition to the above-described vertical path, there is a path (lateral path) through which heat is transmitted from the active portion 6 to the pressure-resistant edge section 5 in addition to the above-described vertical path. Excellent. Therefore, a mountain-like temperature distribution as described above is obtained. Such a temperature distribution is the same for a power MOSFET.
[0007]
By the way, in an insulated gate semiconductor device, a technique for controlling a latch-up phenomenon or a latch-back phenomenon by making the distance between adjacent bases directly below a wire bonding portion smaller than the distance between adjacent bases other than the wire bonding portion is known. (For example, see Patent Document 1). Further, in an IGBT having a plurality of main current cells and one or more current detection cells, a technique for improving the temperature characteristics of current detection by making the base region of the current detection cell larger than the base region of the main current cell is known. (For example, see Patent Document 2).
[0008]
[Patent Document 1]
JP-A-3-96282 [Patent Document 2]
JP-A-9-219518
[Problems to be solved by the invention]
However, in a conventional semiconductor chip of an IGBT or a power MOSFET, when an aluminum wire is bonded to the center of the emitter pad and a test (heat cycle test) in which an energized state and a non-energized state are repeated is performed, heat at the center of the chip is found. Since the mechanical stress is large, problems such as peeling of the aluminum wire and breaking at the root occur. Therefore, there is a limitation that a wire cannot be bonded to the center of the chip. In other words, if a wire is bonded to the center of the chip, there is a problem that thermal reliability is reduced.
[0010]
The present invention has been made in view of the above problems, and provides a semiconductor device with high thermal reliability by relaxing temperature imbalance in a chip surface and improving uniformity of temperature distribution. With the goal.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides a first conductivity type drift layer, a second conductivity type base layer formed on the surface of the drift layer, and a first conductivity type impurity formed in the base layer. A diffusion region, an insulated gate structure provided in contact with a region serving as a channel between the impurity diffusion region and the drift layer, and an electrode electrically connected to both the impurity diffusion region and the base layer. A semiconductor device provided with a plurality of semiconductor elements, wherein the base layers are arranged at different intervals between a central portion and a peripheral portion of the chip.
[0012]
In the present invention, it is preferable that the base layer through which a current flows is densely arranged in the peripheral portion of the chip having a small amount of heat generation, and sparsely arranged in the central portion of the chip having a large amount of heat generation. Further, it is preferable that a breakdown voltage structure in which avalanche breakdown occurs before an avalanche breakdown occurs in the active region outside the active region in which the channel is formed.
[0013]
According to the present invention, the heat radiation at the central portion of the chip, which generates a large amount of heat, is improved, so that the temperature imbalance in the chip surface is reduced, and a uniform temperature distribution is obtained.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0015]
Embodiment 1 FIG.
FIG. 1 is a plan view schematically showing an arrangement of unit cells of the semiconductor device according to the first embodiment of the present invention. As shown in FIG. 1, the unit cells 4 having a stripe structure are arranged in parallel. The interval between the unit cells 4 is large in the central part 11 of the chip and small in the peripheral part 12 of the chip. That is, the unit cells 4 are arranged more sparsely in the chip central part 11 than in the chip peripheral part 12. In FIG. 1, two dashed lines parallel to the unit cell 4 represent boundaries between the chip central portion 11 and the chip peripheral portion 12.
[0016]
Embodiment 2 FIG.
FIG. 2 is a plan view schematically showing an arrangement of unit cells of the semiconductor device according to the second embodiment of the present invention. As shown in FIG. 2, unit cells 4 having a stripe structure are spirally arranged. The interval between the turns of the unit cell 4 is large at the chip central portion 11 and small at the chip peripheral portion 12. That is, the unit cells 4 are arranged more sparsely in the chip central part 11 than in the chip peripheral part 12. In FIG. 2, the two-dot chain lines in the shape of an ellipse represent the chip central portion 11 and the chip peripheral portion 12, respectively.
[0017]
Embodiment 3 FIG.
FIG. 3 is a plan view schematically showing an arrangement of unit cells of the semiconductor device according to the third embodiment of the present invention. As shown in FIG. 3, in the third embodiment, the unit cell 4 is not a simple stripe structure, but has a cell structure in which unit cells 4 having a stripe structure are connected in a square shape. The interval between the unit cells 4 is large in the central part 11 of the chip and small in the peripheral part 12 of the chip. That is, the unit cells 4 are arranged more sparsely in the chip central part 11 than in the chip peripheral part 12. In FIG. 3, the two-dot chain lines of the ellipse represent the chip central portion 11 and the chip peripheral portion 12, respectively.
[0018]
Embodiment 4 FIG.
FIG. 4 is a plan view schematically showing an arrangement of unit cells of the semiconductor device according to the fourth embodiment of the present invention. As shown in FIG. 4, in the fourth embodiment, in addition to the arrangement of the unit cells 4 in the first embodiment, the opposite side of the side on which the gate pad 3 is provided is parallel to the opposite side. In this example, unit cells 4 having a stripe structure are arranged. The interval between the newly arranged unit cells 4 arranged in parallel with the opposite side is the same as the interval in the chip peripheral portion 12. In FIG. 4, two two-dot chain lines parallel to the unit cell 4 indicate a boundary between the chip central portion 11 and the chip peripheral portion 12.
[0019]
Next, four configurations of the semiconductor element applied to the above-described first to fourth embodiments will be briefly described. In the following description, the first conductivity type is n-type and the second conductivity type is p-type, but the reverse is also true.
[0020]
FIG. 5 is a cross-sectional view illustrating a configuration of a non-punch-through IGBT having a trench structure. As shown in FIG. 5, p-base layer 22 is provided on the surface of n ⁻ drift layer 21. Trench 23 is formed to reach n ⁻ drift layer 21 from the surface of p base layer 22. Gate oxide film 24 is provided along the inner surface of trench 23.
[0021]
The inside of the gate oxide film 24 in the trench 23 is filled with conductive polysilicon to be the gate electrode 25. In each unit cell 4, an n source region 26 serving as an impurity diffusion region is provided on the surface layer of the p base layer 22 beside the trench 23. The p ⁺ diffusion layer 27 is provided on the surface layer of the p base layer 22 except for the n source region 26.
[0022]
Emitter pad (electrode) 2 is in contact with the n source region 26 and p ⁺ diffusion layer 27, are electrically connected to both the p base layer 22 through the n source region 26 and p ⁺ diffusion layer 27 I have. In a region between the unit cells 4, the emitter pad 2 is insulated from the p base layer 22 by the interlayer insulating film 28. On the back side of n ⁻ drift layer 21, p ⁺ collector layer 29 is provided.
[0023]
As an example, the dimensions of each part of the IGBT shown in FIG. 5 will be described. Note that the present invention is not limited to these dimensions.
[0024]
The distance W between the unit cells 4 is 40 μm at the chip central portion 11 and 20 μm at the chip peripheral portion 12. The width of the trench 23 is 1 μm. The distance between trenches 23 sandwiching n source region 26 and p ⁺ diffusion layer 27 is 4 μm. The depth of the trench 23 is 6 μm. The depth of p base layer 22 is 5 μm. The depth of n source region 26 and p ⁺ diffusion layer 27 is about 0.5 μm. Gate oxide film 24 has a thickness of 0.1 μm.
[0025]
Although not particularly limited, the p base layer 22, the n source region 26, and the p ⁺ diffusion layer 27 are all formed by ion implantation of impurities and thermal diffusion thereof. In order to form the p base layer 22, for example, boron may be implanted at a dose of about 1 × 10 ¹⁴ cm ⁻² . Further, in order to form the p ⁺ diffusion layer 27, for example, boron may be implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² . In order to form the n source region 26, for example, arsenic may be implanted at a dose of about 1 × 10 ¹⁵ cm ⁻² .
[0026]
FIG. 6 is a cross-sectional view showing a configuration of a non-punch-through IGBT having a planar structure. As shown in FIG. 6, p-base layer 22 is selectively provided on the surface of n ⁻ drift layer 21. On the surface layer of p base layer 22, an n source region 26 and ap ⁺ diffusion layer 27 serving as impurity diffusion regions are provided. A gate oxide film 24 is provided on a region of p base layer 22 interposed between source region 26 and n ⁻ drift layer 21, and a conductive polysilicon film serving as gate electrode 25 is further provided thereon. Is provided.
[0027]
Emitter pad 2 is in contact with the n source region 26 and p ⁺ diffusion layer 27 are electrically connected through the n source region 26 and p ⁺ diffusion layer 27 in both the p base layer 22. The emitter pad 2 is insulated from the gate electrode 25 by an interlayer insulating film 28. On the back side of n ⁻ drift layer 21, p ⁺ collector layer 29 is provided.
[0028]
As an example, the dimensions of each part of the IGBT shown in FIG. 6 will be described. Note that the present invention is not limited to these dimensions.
[0029]
The interval between the unit cells 4 is 40 μm in the central part 11 of the chip and 20 μm in the peripheral part 12 of the chip. The depth of p base layer 22 is 3 μm. The depth of n source region 26 and p ⁺ diffusion layer 27 is 1 μm. Although not particularly limited, the ion species and the dose when forming the p base layer 22, the n source region 26, and the p ⁺ diffusion layer 27 by ion implantation are the same as in the case of the non-punch-through IGBT shown in FIG. It is.
[0030]
FIG. 7 is a sectional view showing a configuration of a punch-through IGBT having a trench structure. As shown in FIG. 7, an n ⁺ buffer layer 31 is provided between n ⁻ drift layer 21 and p ⁺ collector layer 29. Other configurations are the same as those of the non-punch-through type IGBT shown in FIG. The dimensions of each part are the same as those of the non-punch-through type IGBT shown in FIG.
[0031]
FIG. 8 is a cross-sectional view illustrating a configuration of a field stop IGBT having a trench structure. As shown in FIG. 8, an n ⁺ field stop layer 32 is provided between the n ⁻ drift layer 21 and the p ⁺ collector layer 29. Other configurations are the same as those of the non-punch-through type IGBT shown in FIG. The dimensions of each part are the same as those of the non-punch-through type IGBT shown in FIG.
[0032]
FIG. 9 is a cross-sectional view illustrating a configuration of a vertical power MOSFET. As shown in FIG. 9, n ⁻ drift layer 21 is formed on the surface of n ⁺⁺ semiconductor substrate 33. A p base layer 22 is selectively provided on the surface of n ⁻ drift layer 21. On the surface layer of p base layer 22, an n source region 26 and ap ⁺ diffusion layer 27 serving as impurity diffusion regions are provided. A gate oxide film 24 is provided on a region of p base layer 22 interposed between source region 26 and n ⁻ drift layer 21.
[0033]
On the gate oxide film 24, conductive polysilicon serving as the gate electrode 25 is provided. Source pad (electrode) 34 is in contact with the n source region 26 and ^{p +} diffusion layer 27, are electrically connected to both the p base layer 22 through the n source region 26 and ^{p +} diffusion layer 27 I have. The source pad 34 is insulated from the gate electrode 25 by the interlayer insulating film 28.
[0034]
Next, a breakdown voltage structure applied to each of the semiconductor devices of the above-described first to fourth embodiments will be described. FIG. 10 is a cross-sectional view illustrating an example of the pressure resistance structure. As shown in FIG. 10, ap ⁺ well region 35 deeper than the depth of the trench 23 of the active portion 6 is formed immediately below the gate pad 3 by ion implantation and thermal diffusion. The p ⁺ well region 35 and the gate pad 3 are insulated by the interlayer insulating film 28. The gate pad 3 is connected to the gate electrode 25 and is insulated from the emitter pad 2 by an interlayer insulating film 36.
[0035]
By adopting such a breakdown voltage structure, when a voltage is applied to the collector, the pn junction between the p ⁺ well region 35 and the n ⁻ drift layer 21 is provided before the corner at the bottom of the trench 23. Avalanche break down occurs. That is, the element breakdown voltage is determined in the breakdown voltage structure immediately below the gate pad 3.
[0036]
FIG. 11 is a cross-sectional view illustrating another example of the withstand voltage structure. As shown in FIG. 11, a first guard ring 37, a second guard ring 38, and a third guard ring 39, all of which are made of a p-layer, are formed in the breakdown voltage edge portion 5 in order from the side closer to the active portion 6. I do. By appropriately designing the depths and intervals of the first to third guard rings 37, 38, and 39, when a voltage is applied to the collector, the first guard ring 37 has a lower voltage than the active portion 6. Avalanche break down occurs at the outer corner of the vehicle. That is, the element withstand voltage is determined in the withstand voltage edge portion 5.
[0037]
For example, assuming that the dimensions of each part of the IGBT are the dimensions exemplified in the description of the non-punch-through type IGBT shown in FIG. 5, the first to third guard rings 37, 38, and 39 have a depth of 5 μm and a first By separating the guard ring 37 and the second guard ring 38 by 3 μm or more, avalanche break down occurs at a corner outside the first guard ring 37 at a voltage lower than that of the active portion 6.
[0038]
Next, a description will be given of the result of actually producing a prototype IGBT chip and measuring the temperature distribution in the chip. The cell layout pattern of the prototype IGBT chip was the pattern shown in FIG. 1, and the cross-sectional configuration of the IGBT was the configuration shown in FIG. The dimensions and the like of each part are the dimensions exemplified in the description of FIG. 5 and are used as examples. For comparison, an IGBT chip having the same cross-sectional configuration as that of the example and having the cell arrangement pattern shown in FIG. 13 and a cell interval of 30 μm was manufactured, and this was used as a conventional example. However, the total channel length of the MOS was designed to be the same between the embodiment and the conventional example.
[0039]
In both the embodiment and the conventional example, an aluminum wire having a diameter of 350 μm was bonded to the emitter pad 2 at four places in the chip central part 11 and three places at the left and right chip peripheral parts 12 in FIG. In the temperature measurement, a rated current (current density: about 150 A / cm ² ) was applied to the example and the conventional example, and the element temperature Tj was set to 125 ° C.
[0040]
FIG. 12 shows the temperature measurement results. In the embodiment, the maximum temperature in the chip is 148 ° C. and the minimum temperature is 130 ° C. On the other hand, in the conventional example, the maximum temperature and the minimum temperature in the chip are 161 ° C. and 125 ° C., respectively, and the temperature difference in the chip is 36 ° C. Therefore, the temperature difference in the chip of the embodiment is の of that of the conventional example. Further, according to the example, it was confirmed that the maximum temperature in the chip can be reduced by 13 ° C. as compared with the conventional example. Further, the embodiment was not different from the conventional example in static characteristics and switching characteristics such as ON voltage, leakage current and threshold value.
[0041]
Also, for the MOSFET having the cross-sectional configuration shown in FIG. 9, a chip having the cell arrangement pattern shown in FIG. 1 was experimentally manufactured, and the temperature distribution in the chip was measured in the same manner as in the IGBT described above. However, the supplied current is a rated current having a current density of about 50 A / cm ² . As a result, in the MOSFET chip having the cell arrangement pattern shown in FIG. 1, the variation in the temperature distribution inside the chip was smaller than that of the chip having the cell arrangement pattern shown in FIG.
[0042]
According to each of the embodiments described above, the heat dissipation at the chip central portion 11 is improved, and the temperature imbalance in the chip surface is reduced, so that a uniform temperature distribution can be obtained. Therefore, an effect of improving thermal reliability can be obtained. Particularly, in the fourth embodiment, a more uniform temperature distribution can be obtained than in the first embodiment. Also, by providing a withstand voltage structure directly below the gate pad 3 or on the withstand voltage edge portion 5, even if the cell arrangement width of the active portion 6 is changed, avalanche breakdown occurs first in the withstand voltage structure portion. An element design independent of the cell arrangement pattern of the active portion 6 can be performed.
[0043]
Further, by improving the thermal reliability, wire bonding can be performed also at the center of the emitter pad 2 and the source pad 34, so that the number of wires can be increased. Thereby, the heat cycle performance is improved and the resistance component of the wire is reduced.
[0044]
【The invention's effect】
According to the present invention, the heat radiation at the central portion of the chip, which generates a large amount of heat, is improved, and the temperature imbalance in the chip surface is reduced, so that a uniform temperature distribution can be obtained. Therefore, an effect of improving thermal reliability can be obtained.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing an arrangement of unit cells of a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is a plan view schematically showing an arrangement of unit cells of a semiconductor device according to a second embodiment of the present invention;
FIG. 3 is a plan view schematically showing an arrangement of unit cells of a semiconductor device according to a third embodiment of the present invention;
FIG. 4 is a plan view schematically showing an arrangement of unit cells of a semiconductor device according to a fourth embodiment of the present invention.
FIG. 5 is a cross-sectional view showing a configuration of a non-punch-through IGBT having a trench structure.
FIG. 6 is a cross-sectional view illustrating a configuration of a non-punch-through IGBT having a planar structure.
FIG. 7 is a cross-sectional view showing a configuration of a punch-through IGBT having a trench structure.
FIG. 8 is a cross-sectional view illustrating a configuration of a field stop IGBT having a trench structure.
FIG. 9 is a cross-sectional view illustrating a configuration of a vertical power MOSFET.
FIG. 10 is a sectional view showing an example of a breakdown voltage structure of the semiconductor device according to the embodiment of the present invention;
FIG. 11 is a cross-sectional view showing another example of the breakdown voltage structure of the semiconductor device according to the embodiment of the present invention.
FIG. 12 is a characteristic diagram showing a result of measuring a temperature distribution in a chip for the IGBT according to the first embodiment and a conventional IGBT.
FIG. 13 is a plan view schematically showing an arrangement of one unit cell of an IGBT in a conventional semiconductor device.
FIG. 14 is a diagram schematically showing a temperature distribution and a heat propagation path in a conventional IGBT chip.
[Explanation of symbols]
1 chip 2, 34 electrodes (emitter pad, source pad)
11 chip central part 12 chip peripheral part 21 drift layer 22 base layer 24, 25 insulated gate structure (gate oxide film, gate electrode)
26 Impurity diffusion region (source region)
35, 37, 38, 39 Withstand voltage structure (p ⁺ well region, guard ring)

Claims (3)

A first conductivity type drift layer, a second conductivity type base layer formed on the surface of the drift layer, a first conductivity type impurity diffusion region formed in the base layer, the impurity diffusion region and the drift layer And a semiconductor device provided with a plurality of semiconductor elements each including an electrode electrically connected to both the impurity diffusion region and the base layer. hand,
The semiconductor device according to claim 1, wherein the base layer is arranged at different intervals between a central portion and a peripheral portion of the chip. 2. The chip according to claim 1, wherein the base layer is arranged more sparsely in a central portion of a chip where a large amount of heat is generated from the electrode than in a peripheral portion of a chip where a small amount of heat is generated from the electrode. 3. Semiconductor device. 3. The semiconductor device according to claim 1, further comprising a breakdown voltage structure in which avalanche breakdown occurs earlier than avalanche breakdown occurs in the active region, outside the active region in which the channel is formed. 13. The semiconductor device according to claim 1.

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