CN109166921B - Shielding gate MOSFET - Google Patents

Shielding gate MOSFET Download PDF

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Publication number
CN109166921B
CN109166921B CN201810990425.XA CN201810990425A CN109166921B CN 109166921 B CN109166921 B CN 109166921B CN 201810990425 A CN201810990425 A CN 201810990425A CN 109166921 B CN109166921 B CN 109166921B
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type semiconductor
region
gate electrode
conductive type
shielding
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CN109166921A (en
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任敏
杨梦琦
胡玉芳
李泽宏
高巍
张金平
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device

Abstract

A shielded gate MOSFET belongs to the technical field of semiconductor power devices. The device comprises a drain electrode, a substrate, a drift region and a metalized source electrode which are sequentially stacked from bottom to top, wherein a working cell region and a drain cell region are arranged in the drift region; the drain unit cell region is located beside the working unit cell, and because the drain unit cell region does not contain a source region and the side dielectric layer between the shielding gate electrode and the drift region is thicker, the lateral auxiliary depletion effect of the shielding gate on the N-type drift region is reduced, so that the static avalanche breakdown voltage of the drain unit cell is lower than that of the working unit cell, and an avalanche breakdown point is fixed at the drain unit cell, so that avalanche current flows out through a source electrode above the drain unit cell, and meanwhile, because no parasitic BJT exists, the possibility of conduction of the parasitic BJT is completely eradicated. Therefore, the invention can avoid secondary breakdown caused by starting the parasitic BJT and effectively improve the reliability of the device.

Description

Shielding gate MOSFET
Technical Field
The invention belongs to the technical field of power semiconductors, and particularly relates to a shielded gate MOSFET.
Background
DC/DC researchers have been challenged to improve efficiency and power density. And continued advances in power MOSFET technology have helped them achieve this goal. Of the on-resistance rds (on) and the gate charge Qg, one generally decreases and the other increases, so the power MOSFET designer must consider the trade-off between the two. And the shielded Gate MOSFET (shielded Gate MOSFET) is an improved MOSFET based on the traditional Trench MOSFET (U-MOSFET), and can reduce the rds (on) without influencing the Qg. Compared with a U-MOSFET, the shielding grid MOSFET has higher switching speed and lower switching loss; meanwhile, the shielded gate MOSFET uses the shielded gate polycrystalline layer thereof as an in-body field plate to reduce the electric field of the drift region, thereby obtaining higher breakdown voltage. However, shielded gate MOSFETs, which are members of the power MOSFET family, still need to be considered for their avalanche resistance due to the intrinsic diode attached to the MOSFET structure with some avalanche capability. When a hole current in the avalanche current will flow through the P-body region under the N + source region to the P + contact region, a forward voltage drop will be created across the base resistance Rb of the parasitic BJT. When the avalanche current is larger, the forward voltage drop on the base resistance Rb of the parasitic BJT is higher, and if the generated voltage drop is larger than the forward conduction voltage drop of the parasitic BJT, the emitter of the parasitic BJT is forward biased and enters the forward amplification working region, which may cause the thermal burnout of the device, and the damage caused by the thermal burnout of the device is irreversible. Thus, if avalanche current is not limited or the device design is not optimized enough, reliability issues may arise once avalanche capability is exceeded, possibly even causing device failure. Therefore, the parasitic bipolar transistor in the power MOSFET does not work as much as possible by the measures adopted in the design process of the power MOSFET, and the reliability of the device in the static process is improved.
Disclosure of Invention
In view of the foregoing, it is an object of the present invention to provide a shielded gate MOSFET that prevents the turn-on of parasitic Bipolar Junction Transistors (BJTs). The leakage unit cell without a source region is arranged beside the traditional shielding grid MOSFET working unit cell, and the thickness of the side dielectric layer of the shielding grid electrode in the leakage unit cell is larger than that of the side dielectric layer of the shielding grid electrode in the working unit cell, so that the avalanche breakdown point is fixed at the leakage unit cell, and the parasitic BJT is prevented from being started.
The technical scheme adopted by the invention is as follows:
a shielded gate MOSFET comprises a metalized drain electrode 1 and a first conductive type semiconductor substrate 2 which are sequentially stacked from bottom to top. A first conductivity type semiconductor drift region 3 and a metallised source 12; the first conductive type semiconductor drift region 3 is provided with a working cell region and a drain cell region;
the working cell area includes: the semiconductor device comprises a first second conduction type semiconductor body region 4, a first conduction type semiconductor heavily doped source region 5, a first second conduction type semiconductor heavily doped contact region 6, a first shielding gate structure and a first control gate structure; the second conductive type semiconductor body region I4 is arranged on two sides of the top layer of the first conductive type semiconductor drift region 3; the first conductive type semiconductor heavily-doped source region I5 and the second conductive type semiconductor heavily-doped contact region I6 are arranged on the top layer of the second conductive type semiconductor body region I4 side by side and are in contact with the metalized source electrode 12 above the second conductive type semiconductor body region I4; the first control gate structure is arranged above the first shielding gate structure, the first control gate structure and the first shielding gate structure are arranged in a first groove 7 between the first second-conductivity-type semiconductor body regions 4 on two sides, and the first groove 7 vertically penetrates into the first-conductivity-type semiconductor drift region 3 from the top layer of the device; the first control gate structure comprises a first control gate electrode 10 and a first control gate dielectric layer 11 around the first control gate electrode, the depth of the first control gate electrode 10 is greater than the junction depth of a first conductive type semiconductor body region 4, and the first control gate electrode 10 is in contact with a metalized source 12 above the first control gate electrode and the first conductive type semiconductor body region 4 and a first conductive type semiconductor heavily doped source region 5 on the periphery of the first control gate dielectric layer 11 through the first control gate dielectric layer 11; the first shielding gate structure comprises a first shielding gate electrode 9 and a first shielding gate dielectric layer 8 around the first shielding gate electrode; the depth of the first shielding gate electrode 9 is less than the junction depth of the first conductive type semiconductor drift region 3, and the first shielding gate electrode 9 is contacted with the first control gate electrode 10 above the first shielding gate electrode and the first conductive type semiconductor drift region 3 on the peripheral side of the first control gate electrode through the first shielding gate dielectric layer 8;
the drainage cellular region comprises: a second conductive type semiconductor body region II 41, a second conductive type semiconductor heavily doped contact region II 61 and a second shielding gate structure; the second conductive type semiconductor body region two 41 is arranged on two sides of the top layer of the first conductive type semiconductor drift region 3; the second conductive type semiconductor heavily doped contact region II 61 is arranged at the top layer of the second conductive type semiconductor body region II 41; the second conductive type semiconductor body region two 41 and the second conductive type semiconductor heavily doped contact region two 61 are in contact with the metalized source electrode 12 above the second conductive type semiconductor body region two; the second shielding gate structure is arranged in a second groove 71 between the second conductive type semiconductor body regions 41 on the two sides, and the second groove 71 vertically penetrates into the first conductive type semiconductor drift region 3 from the top layer of the device; the second shielding gate structure comprises a second shielding gate electrode 91 and a second shielding gate dielectric layer 81 around the second shielding gate electrode 91, wherein the thickness of the second shielding gate dielectric layer 81 on the side surface between the second shielding gate electrode 91 and the first conductive type semiconductor drift region 3 is larger than that of the first shielding gate dielectric layer 8 in the working cell region; the depth of the second shield gate electrode 91 is smaller than the junction depth of the first conductivity type semiconductor drift region 3, and the second shield gate electrode 91 is in contact with the metalized source 12, the second conductivity type semiconductor body region 41 on the peripheral side and the first conductivity type semiconductor drift region 3 above the second shield gate electrode through the second shield gate dielectric layer 81.
Further, the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor, where an N-channel MOSFET is formed, or the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor, where a P-channel MOSFET is formed.
Furthermore, at least one working cell is arranged between any two adjacent leakage cell areas.
Further, the second shielded gate structure includes a first split shielded gate electrode 911, a second split shielded gate electrode 912, and a second shielded gate dielectric layer 81 disposed around the first split shielded gate electrode 911 and the second split shielded gate electrode 912; the first split shield gate electrode 911 is disposed above the second split shield gate electrode 912, the first split shield gate electrode 911 and the second split shield gate electrode 912 are in direct contact or are isolated by a dielectric layer, and the depth of the first split shield gate electrode 911 is greater than the junction depth of the second conductivity type semiconductor body region two 41.
Further, the doping concentration of the second conductivity type semiconductor body region one 4 is equal to that of the second conductivity type semiconductor body region two 41.
Further, the junction depth of the second conductivity type semiconductor body 4 is equal to the junction depth of the second conductivity type semiconductor body 41.
Further, the semiconductor material used in the device of the present invention is silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor material.
The principle and the beneficial effects of the invention are as follows:
according to the invention, the drain unit cell is arranged beside the working unit cell of the traditional shielded gate MOSFET, the drain unit cell does not contain an active electrode region, and the side dielectric layer between the shielded gate electrode and the drift region is thicker, and the lateral auxiliary depletion effect of the shielded gate on the N-type drift region is reduced by the aid of the lateral auxiliary depletion layer, so that the static avalanche breakdown voltage of the drain unit cell is lower than that of the working unit cell, an avalanche breakdown point is fixed at the drain unit cell, and avalanche current flows out through the source electrode above the drain unit cell; however, since the drain unit cell does not contain a source region, a parasitic BJT does not exist correspondingly, and the possibility of conducting the parasitic BJT is completely eliminated. Therefore, the invention can avoid secondary breakdown caused by starting of the parasitic BJT and effectively improve the reliability of the device.
Drawings
Fig. 1 is a schematic cross-sectional view of a cell of a conventional shielded gate MOSFET.
Fig. 2 is a schematic cross-sectional view of a cell of a shielded gate MOSFET according to embodiment 1 of the present invention, wherein i denotes an operating cell region, and ii denotes a bleeder cell region.
Fig. 3 is a schematic cross-sectional view of a cell of a shielded gate MOSFET according to embodiment 2 of the present invention, wherein i denotes an operating cell region, and ii denotes a bleeder cell region.
Fig. 4 is a schematic diagram of a layout of working cells and bleeder cells in a shielded gate MOSFET according to embodiment 2 of the present invention, where i denotes a working cell area, and ii denotes a bleeder cell area, and a number ratio of the working cell area to the bleeder cell area is 1: 1.
Fig. 5 is a schematic cross-sectional view along line AA' of the layout shown in fig. 3.
Fig. 6 is a schematic cross-sectional view along line BB' of the layout shown in fig. 3.
Fig. 7 is a schematic cross-sectional view of a cell of a shielded gate MOSFET according to embodiment 3 of the present invention, wherein i denotes an operating cell region, and ii denotes a bleeder cell region.
In the drawing, 1 is a metalized drain, 2 is a first conductive type semiconductor substrate, 3 is a first conductive type semiconductor drift region, 4 is a first second conductive type semiconductor body region, 41 is a second conductive type semiconductor body region, 5 is a first conductive type semiconductor source region, 51 is a second first conductive type semiconductor source region, 6 is a first second conductive type semiconductor contact region, 61 is a second conductive type semiconductor contact region, 7 is a first trench, 71 is a second trench, 8 is a first shielding gate dielectric layer, 81 is a second shielding gate dielectric layer, 9 is a first shielding gate electrode, 91 is a second shielding gate electrode, 911 is a first split shielding gate electrode, 912 is a second split shielding gate electrode, 10 is a first control gate dielectric layer, 11 is a first control gate dielectric layer, and 12 is a metalized source.
Detailed Description
So that those skilled in the art can better understand the principle and the scheme of the present invention, the following detailed description is given with reference to the accompanying drawings and specific embodiments. The teachings of the present invention are not limited to any particular embodiment nor represent the best embodiment, and general alternatives known to those skilled in the art are also encompassed within the scope of the present invention.
Example 1;
the present embodiment provides a shielded gate MOSFET, as shown in fig. 2, including a metalized drain 1 and a first conductive type semiconductor substrate 2 stacked in sequence from bottom to top. A first conductivity type semiconductor drift region 3 and a metallised source 12; the semiconductor drift region is characterized in that a working cell region and a drain cell region are arranged in the first conductive type semiconductor drift region 3;
the working cell area includes: the semiconductor device comprises a first second conduction type semiconductor body region 4, a first conduction type semiconductor heavily doped source region 5, a first second conduction type semiconductor heavily doped contact region 6, a first shielding gate structure and a first control gate structure; the second conductive type semiconductor body region I4 is arranged on two sides of the top layer of the first conductive type semiconductor drift region 3; the first conductive type semiconductor heavily-doped source region I5 and the second conductive type semiconductor heavily-doped contact region I6 are arranged on the top layer of the second conductive type semiconductor body region I4 side by side and are in contact with the metalized source electrode 12 above the second conductive type semiconductor body region I4; the first control gate structure is arranged above the first shielding gate structure, the first control gate structure and the first shielding gate structure are arranged in a first groove 7 between the first second-conductivity-type semiconductor body regions 4 on two sides, and the first groove 7 vertically penetrates into the first-conductivity-type semiconductor drift region 3 from the top layer of the device; the first control gate structure comprises a first control gate electrode 10 and a first control gate dielectric layer 11 around the first control gate electrode, the depth of the first control gate electrode 10 is greater than the junction depth of a first conductive type semiconductor body region 4, and the first control gate electrode 10 is in contact with a metalized source 12 above the first control gate electrode and the first conductive type semiconductor body region 4 and a first conductive type semiconductor heavily doped source region 5 on the periphery of the first control gate dielectric layer 11 through the first control gate dielectric layer 11; the first shielding gate structure comprises a first shielding gate electrode 9 and a first shielding gate dielectric layer 8 around the first shielding gate electrode; the depth of the first shielding gate electrode 9 is less than the junction depth of the first conductive type semiconductor drift region 3, and the first shielding gate electrode 9 is contacted with the first control gate electrode 10 above the first shielding gate electrode and the first conductive type semiconductor drift region 3 on the peripheral side of the first control gate electrode through the first shielding gate dielectric layer 8;
the drainage cellular region comprises: a second conductive type semiconductor body region II 41, a second conductive type semiconductor heavily doped contact region II 61 and a second shielding gate structure; the second conductive type semiconductor body region two 41 is arranged on two sides of the top layer of the first conductive type semiconductor drift region 3; the second conductive type semiconductor heavily doped contact region II 61 is arranged at the top layer of the second conductive type semiconductor body region II 41; the second conductive type semiconductor body region two 41 and the second conductive type semiconductor heavily doped contact region two 61 are in contact with the metalized source electrode 12 above the second conductive type semiconductor body region two; the second shielding gate structure is arranged in a second groove 71 between the second conductive type semiconductor body regions 41 on the two sides, and the second groove 71 vertically penetrates into the first conductive type semiconductor drift region 3 from the top layer of the device; the second shielding gate structure comprises a second shielding gate electrode 91 and a second shielding gate dielectric layer 81 around the second shielding gate electrode 91, wherein the thickness of the second shielding gate dielectric layer 81 on the side surface between the second shielding gate electrode 91 and the first conductive type semiconductor drift region 3 is larger than that of the first shielding gate dielectric layer 8 in the working cell region; the depth of the second shield gate electrode 91 is smaller than the junction depth of the first conductivity type semiconductor drift region 3, and the second shield gate electrode 91 is in contact with the metalized source 12, the second conductivity type semiconductor body region 41 on the peripheral side and the first conductivity type semiconductor drift region 3 above the second shield gate electrode through the second shield gate dielectric layer 81. In the present embodiment, the bleeder cell region does not have a control gate electrode, and the second shield gate electrode 91 directly extends into the second conductivity type semiconductor body region 41, because the bleeder cell region does not have an N + source region, and does not have an on function even if a control gate electrode is present, and thus the manufacturing process thereof can be omitted to simplify the process.
The working principle of the device of the invention is explained in detail below with reference to the examples:
taking an N-channel device as an example, the working principle of a P-channel device should be easily known to those skilled in the art based on the N-channel device principle disclosure.
When the metalized source 12 is connected to a low potential, the metalized drain 1 is connected to a high potential, and the control gate electrode 10 is connected to a high potential, the working cell area in the shielded gate MOSFET of the present embodiment is in a forward conducting state, and at this time, the first shielded gate electrode 9 and the metalized source 12 have the same potential. When a forward bias voltage applied to the first control gate electrode 10 reaches a threshold voltage, an inversion channel is formed in the P-type body region 4 near the sidewalls of the first trench 7. Thus, electrons are injected as carriers from the heavily doped N + source region 5 into the N-type drift region 3 through the inversion channel in the P-type body region 4, forming a forward conduction current.
When the metalized source 12 is connected with a low potential, the metalized drain 1 is connected with a high potential, the control gate electrode 10 is connected with a low potential, the working cell area and the leakage cell area of the shielded gate MOSFET are both in a reverse blocking state, and the potentials of the shielded gate electrodes 9 and 91 are the same as that of the metalized source 12. Because the shielding gate electrodes 9 and 91 are connected with low potential, the N-type drift region 3 and the metalized drain electrode 1 have the same potential, so that transverse electric fields are respectively generated between the N-type drift region 3 and the shielding gate electrodes 9 and 91 to transversely assist in depleting the N-type drift region 3, the slope of the transverse electric fields is increased, the slope of the longitudinal electric fields is reduced, the area enclosed by the longitudinal electric fields and the depletion regions is increased, and the static breakdown voltage of the unit cell is improved.
When the shielded gate MOSFET of this embodiment is subjected to static avalanche breakdown, since the side dielectric layer between the second shielded gate electrode 91 of the bleeder cell region and the drift region is thicker, the lateral auxiliary depletion effect of the second shielded gate electrode 91 on the N-type drift region can be reduced, the slope of the lateral electric field is reduced, the slope of the longitudinal electric field is improved, the area enclosed by the longitudinal electric field and the depletion region is reduced, and the static breakdown voltage of the bleeder cell is reduced. Since the static avalanche breakdown voltage in the bleeder cell region is lower than that of the working cell region, the static avalanche breakdown point will be limited at the bleeder cell, and since the N + source region 5 is not arranged inside the P-type body region two 41 of the bleeder cell region, no parasitic BJT exists. Therefore, when the avalanche current flows through the bleeder cell, the parasitic BJT is not turned on, thereby preventing the secondary breakdown caused by the turn-on of the parasitic BJT.
Example 2:
this embodiment provides a shielded gate MOSFET, as shown in fig. 3, and the difference of this embodiment from embodiment 1 is that: the second split shield gate electrode 91 in the bleeder cell may be designed as two mutually independent first split shield gate electrode 911 and second split shield gate electrode 912, the first split shield gate electrode 911 is disposed above the second split shield gate electrode 912, and the depth of the first split shield gate electrode 911 is larger than the junction depth of the second conductivity type semiconductor body region two 41. The first split shield gate electrode 911 is structurally equivalent to the first control gate electrode 10 in the operating cell region, but since no source region exists in the drain cell region, the first split shield gate electrode 911 does not have a turn-on function, and the first split shield gate electrode 911 and the second split shield gate electrode 912 can be isolated by using a dielectric layer, which is similar to the operating principle of embodiment 1.
The bleeder cell regions of the present invention may be separated by one or more working cell regions, i.e., the number ratio of working cells to bleeder cells may be 1: 1 or n: 1n >1, and the number of n may be designed by those skilled in the art according to the on-resistance and current capability required by the device. As shown in fig. 4, a layout schematic diagram based on the structure of this embodiment is provided, where the number ratio of the working cell areas and the bleeder cell areas in the layout schematic diagram is 1: 1, that is, the layout schematic diagram is under the condition that the working cells and the bleeder cells are alternately arranged, where the AA 'cross-sectional schematic diagram of the bleeder cells is shown in fig. 5, and the BB' cross-sectional schematic diagram of the working cells is shown in fig. 6.
Example 3:
this embodiment provides a shielded gate MOSFET, as shown in fig. 7, which is different from embodiment 1 in that: the second split shield gate electrode 91 of the bleeder cell may be designed as two mutually independent first split shield gate electrode 911 and second split shield gate electrode 912, the first split shield gate electrode 911 being disposed above the second split shield gate electrode 912, and the depth of the first split shield gate electrode 911 being larger than the junction depth of the second conductivity type semiconductor body region two 41. The first split shield gate electrode 911 structurally corresponds to the first control gate electrode 10 in the operating cell region, but since no source region exists in the bleeder cell region, the first split shield gate electrode 911 does not have a turn-on function, and because of this, the first split shield gate electrode 911 and the second split shield gate electrode 912 can be in direct contact with each other, and the operating principle is similar to that of embodiment 1.
While the present invention has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims (8)

1. A shielded gate MOSFET comprises a metalized drain electrode (1), a first conductive type semiconductor substrate (2), a first conductive type semiconductor drift region (3) and a metalized source electrode (12) which are sequentially stacked from bottom to top; the semiconductor drift region is characterized in that a working cell region and a drain cell region are arranged in the first conductive type semiconductor drift region (3);
the working cell area includes: the semiconductor device comprises a first second conduction type semiconductor body region (4), a first conduction type semiconductor heavily doped source region (5), a first second conduction type semiconductor heavily doped contact region (6), a first shielding gate structure and a first control gate structure; the first second conduction type semiconductor body region (4) is arranged on two sides of the top layer of the first conduction type semiconductor drift region (3); the first conductive type semiconductor heavily-doped source region I (5) and the second conductive type semiconductor heavily-doped contact region I (6) are arranged on the top layer of the second conductive type semiconductor body region I (4) side by side and are in contact with the metalized source electrode (12) above the second conductive type semiconductor body region I; the first control gate structure is arranged above the first shielding gate structure, the first control gate structure and the first shielding gate structure are arranged inside a first groove (7) between first second-conductivity-type semiconductor body regions (4) on two sides, and the first groove (7) vertically penetrates into a first-conductivity-type semiconductor drift region (3) from the top layer of the device; the first control gate structure comprises a first control gate electrode (10) and a first control gate dielectric layer (11) around the first control gate electrode, the depth of the first control gate electrode (10) is greater than the junction depth of a first semiconductor body region (4) of the second conduction type, and the first control gate electrode (10) is in contact with a metalized source electrode (12) above the first control gate electrode through the first control gate dielectric layer (11) and the first semiconductor body region (4) of the second conduction type on the periphery of the first control gate electrode and a first heavily doped source region (5) of the first conduction type; the first shielding gate structure comprises a first shielding gate electrode (9) and a first shielding gate dielectric layer (8) around the first shielding gate electrode; the depth of the first shielding gate electrode (9) is smaller than the junction depth of the first conductive type semiconductor drift region (3), and the first shielding gate electrode (9) is in contact with a first control gate electrode (10) above the first shielding gate electrode and the first conductive type semiconductor drift region (3) on the peripheral side of the first control gate electrode through a first shielding gate dielectric layer (8);
the drainage cellular region comprises: a second conductive type semiconductor body region II (41), a second conductive type semiconductor heavily doped contact region II (61) and a second shielding gate structure; the second conductive type semiconductor body region II (41) is arranged on two sides of the top layer of the first conductive type semiconductor drift region (3); the second conductive type semiconductor heavily-doped contact region II (61) is arranged at the top layer of the second conductive type semiconductor body region II (41); a second conductive type semiconductor body region II (41) and a second conductive type semiconductor heavily-doped contact region II (61) are contacted with the metalized source electrode (12) above the second conductive type semiconductor body region II; the second shielding grid structure is arranged in a second groove (71) between second conductive type semiconductor body regions (41) on two sides, and the second groove (71) vertically penetrates into the first conductive type semiconductor drift region (3) from the top layer of the device; the second shielding gate structure comprises a second shielding gate electrode (91) and a second shielding gate dielectric layer (81) around the second shielding gate electrode, wherein the thickness of the second shielding gate dielectric layer (81) on the side surface between the second shielding gate electrode (91) and the first conductive type semiconductor drift region (3) is larger than that of the first shielding gate dielectric layer (8) in the working cell region; the depth of the second shielded gate electrode (91) is smaller than the junction depth of the first conductive type semiconductor drift region (3), and the second shielded gate electrode (91) is in contact with the metalized source (12) above the second shielded gate dielectric layer (81), the second conductive type semiconductor body region II (41) on the peripheral side and the first conductive type semiconductor drift region (3) through the second shielded gate dielectric layer (81);
the second conductive type semiconductor body region II (41) does not contain a first conductive type semiconductor heavily-doped source region structure; the thickness of the second shielding grid dielectric layer (81) can ensure that the transverse auxiliary depletion effect of the second shielding grid electrode (91) on the first conduction type semiconductor drift region (3) is weakened until the leakage unit cell region breaks down before the working unit cell region.
2. The shielded gate MOSFET of claim 1 wherein any two adjacent bleeder cell regions are separated by at least one working cell region.
3. The shielded gate MOSFET of claim 2, wherein the second shielded gate structure comprises a first split shielded gate electrode (911), a second split shielded gate electrode (912), and a second shielded gate dielectric layer (81) disposed around the first split shielded gate electrode (911) and the second split shielded gate electrode (912); the first split shield gate electrode (911) is disposed above the second split shield gate electrode (912) and either directly contacts or is separated by a dielectric layer.
4. A shielded gate MOSFET as claimed in claim 2 wherein the doping concentration of the first semiconductor body region of the second conductivity type (4) is equal to the doping concentration of the second semiconductor body region of the second conductivity type (41).
5. A shielded gate MOSFET as claimed in claim 2 wherein the junction depth of the first semiconductor body region of the second conductivity type (4) is equal to the junction depth of the second semiconductor body region of the second conductivity type (41).
6. The shielded gate MOSFET of claim 2 wherein the semiconductor material of the shielded gate MOSFET is silicon, silicon carbide, gallium arsenide, indium phosphide or silicon germanium semiconductor material.
7. The shielded gate MOSFET of any of claims 1-6 wherein the first conductivity type semiconductor is an N-type semiconductor and the second conductivity type semiconductor is a P-type semiconductor, when an N-channel MOSFET is formed.
8. The shielded gate MOSFET of any of claims 1-6 wherein the first conductivity type semiconductor is a P-type semiconductor and the second conductivity type semiconductor is an N-type semiconductor, when forming a P-channel MOSFET.
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