CN109830524B - Super-junction power VDMOS with extremely low reverse recovery charge - Google Patents
Super-junction power VDMOS with extremely low reverse recovery charge Download PDFInfo
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
Abstract
The invention relates to a super-junction power VDMOS (vertical double-diffused metal oxide semiconductor) with extremely-low reverse recovery charge, which comprises an N-type substrate and an N-type drift region, wherein the N-type substrate and the N-type drift region are also used as a drain electrode, a first P column is arranged in the N-type drift region, a first P-type body region is arranged at the top of the first P column, an NMOS (N-channel metal oxide semiconductor) tube is arranged on the first P-type body region, a SiO2 isolation layer is arranged between the NMOS tube and the first P-type body region, a first P-type heavily doped region is arranged on the first P-type body region, and a source metal of the super-junction VD; the drain electrode of the super-junction VDMOS is used as the drain electrode of the super-junction power VDMOS, the grid electrode of the super-junction VDMOS is connected with the grid electrode of the NMOS tube and is used as the grid electrode of the super-junction power VDMOS, and the drain electrode of the NMOS tube is used as the source electrode of the super-junction power VDMOS; a Schottky contact is arranged on an N-type drift region of the super-junction VDMOS and is connected with a drain electrode of the NMOS tube, so that a Schottky diode with a cathode and an anode respectively connected with the drain electrode and the source electrode of the structure is formed.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a preparation method of a super junction power VDMOS device with extremely low reverse recovery charge
Background
The Super Junction Vertical-diffusion Metal-oxide-semiconductor field effect transistor (SJ-VDMOS) breaks the silicon limit, realizes extremely low on-resistance, maintains high voltage resistance of the device, and has wide application in pulse width modulation and motor control circuits.
A traditional SJ-VDMOS introduces a highly doped P column to be mutually and transversely depleted with a high-concentration N type voltage-resistant layer so as to reduce a longitudinal electric field of a device and realize high voltage-resistant capability and low on-resistance of the device. But the anode emission area of the SJ-VDMOS body diode is greatly increased by the highly doped p columnHole injection efficiency, resulting in extremely poor reverse recovery characteristics of the SJ-VDMOS body diode, such as excessive reverse recovery current (I)rrm) Excessive reverse recovery charge (Q)rr) And an extremely low softness factor (S), thereby reducing the reliability of the device operation, increasing the operation loss of the system and causing serious electromagnetic interference (EMI) noise, and severely restricting the application of the SJ-VDMOS in the fields of hard switch topological structures and high-frequency switch application. In order to overcome the problem of poor reverse recovery characteristics of the traditional SJ-VDMOS body diode, two main technical approaches are generally adopted: carrier lifetime control techniques and parallel schottky diode techniques. The carrier lifetime control technology, such as the electron irradiation technology and the heavy metal doping technology, effectively reduces the lifetime of minority carriers in the N-type voltage-withstanding layer by introducing a deep-level recombination center to reduce reverse recovery charges, but may cause a large increase in device leakage current, especially at high temperature, and the electron irradiation technology has high cost and a complex heavy metal doping technology process. And (II) the parallel Schottky diode technology enables the free-wheeling current to be conducted by the Schottky diode mostly, reduces the current flowing through the SJ-VDMOS body diode, and therefore remarkably improves the reverse recovery characteristic. This solution inevitably leads to two acute problems. Firstly, the improvement of the reverse recovery characteristic and the level of leakage current of a body diode of the SJ-VDMOS are in a compromise relation with the area size of the Schottky diode, if the area is larger, the improvement effect of the reverse recovery characteristic is more obvious, but the leakage current is also obviously increased; secondly, the current capability of the Schottky diode is lower than that of an SJ-VDMOS body diode, so that the body diode still plays a dominant role in follow current when high follow current flows, and the improvement effect of the scheme on the reverse recovery characteristic is greatly reduced. As can be seen from the above, the conventional parallel schottky scheme cannot greatly improve the reverse recovery characteristic of the SJ-VDMOS body diode on the basis of maintaining a low leakage current level, and the technical scheme is limited by the level of the follow current, and can achieve a good reverse recovery improvement only under a low follow current. Therefore, we propose a new SJ-VDMOS structure, which ensures low leakage characteristics of the device while achieving good reverse recovery characteristics,and under the condition of high follow current, the structure can still realize excellent reverse recovery characteristics.
Disclosure of Invention
The invention provides an SJ-VDMOS device with extremely low reverse recovery charge, which can remarkably reduce the reverse recovery charge Qrr of an SJ-VDMOS body diode, increase the softness factor S of reverse recovery and still realize excellent reverse recovery characteristic under the condition of large follow current while keeping high withstand voltage, low leakage and low production cost, thereby reducing the power consumption and the electromagnetic interference noise of the device during the reverse recovery and further improving the reliability of the device.
The technical scheme of the invention is as follows:
the super-junction power VDMOS comprises a super-junction VDMOS, and the super-junction VDMOS comprises an N-type substrate which is also used as a drain electrode and an N-type drift region arranged on the N-type substrate2The isolating layer is also provided with a first P-type heavily doped region on the first P-type body region, and the source metal of the super-junction VDMOS, the source metal of the NMOS tube and the first P-type heavily doped region are connected; the drain electrode of the super-junction VDMOS is used as the drain electrode of the super-junction power VDMOS, the grid electrode of the super-junction VDMOS is connected with the grid electrode of the N MOS tube and used as the grid electrode of the super-junction power VDMOS, and the drain electrode of the N MOS tube is used as the source electrode of the super-junction power VDMOS; and a Schottky contact is also arranged on the N-type drift region of the super-junction VDMOS and is connected with the drain electrode of the N MOS tube, so that a Schottky diode with a cathode connected with the drain electrode of the super-junction power VDMOS and an anode connected with the source electrode of the super-junction power VDMOS is formed.
Compared with the traditional SJ-VDMOS, the method has the following advantages:
1. the invention utilizes the integrated cellular distributed Schottky contact 9 to conduct the follow current, thereby greatly reducing the follow current periodThe total amount of hole charges stored in the N-type voltage-withstanding layer. Because the body diode of the traditional SJ-VDMOS device is composed of the first P-type body region with high concentration, the P column and the N-type voltage-withstanding layer, when the body diode is conducted in the forward direction, a large amount of hole current can be generated and flows through the N-type voltage-withstanding layer, so that a large amount of holes are stored in the N-type voltage-withstanding layer, the reverse recovery characteristic of the body diode is extremely poor, and the number of reverse recovery charges (Q) is largerr) The total amount is large. The Schottky diode is a majority carrier (electron) conductive device, so that during forward conduction, almost no hole carrier is stored in the N-type voltage-resisting layer, the reverse recovery characteristic of the SJ-VDMOS is remarkably improved, and the Qrr is greatly reduced.
2. The invention utilizes a P-type substrate region 11, an N-type heavily doped drain region 13, an N-type heavily doped source region 51, a P-type heavily doped region 10B and SiO2The reverse bias PN junction formed by the P-type substrate region and the N-type heavily doped drain region in the isolation type NMOS tube 101 formed by the isolation layer 12 has a blocking effect on follow current, the current is forced to follow current only through the Schottky diode, and the opening of an SJ-VDMOS body diode is effectively inhibited, so that the excellent reverse recovery characteristic of the device is realized under the condition of large follow current. The traditional SJ-VDMOS device of the parallel Schottky diode utilizes the characteristics of low turn-on voltage and multi-photon conduction of the Schottky diode, and can realize ideal reverse recovery characteristic under smaller continuous current. When the current (I) is freewheelingF) When the current is higher, the body diode of the SJ-VDMOS plays a leading role in the follow current, and most of the follow current flows through the diode, so that the improvement effect of the method on reverse recovery is greatly reduced. In the invention, due to the existence of the reverse bias PN junction of the NMOS, the follow current completely flows out of the drain electrode through the Schottky diode during the follow current period, thereby obviously improving the poor reverse recovery characteristic of the SJ-VDMOS device of the traditional parallel Schottky diode under the condition of large follow current. As shown in the circuit diagram 3, the NMOS devices are connected in series below the SJ-VDMOS devices, the sources of the two MOS devices are shorted, the gate voltages are the same, and the body diode PN junctions of the two MOS devices are in opposite directions. Therefore, when the loop current flows, the channel of the NMOS tube is not conducted, the body diode is reversely biased, the current cannot flow through the NMOS tube, and the current is forced to flow to the multi-sub conduction onlyThe schottky diode of (1) does not flow through the body diode of the SJ-VDMOS, thereby achieving excellent reverse recovery characteristics of the device under large freewheeling currents, as shown in the reverse recovery comparison diagram of the two structures of fig. 6. Furthermore, the introduction of the schottky contact not only results in a very low reverse recovery stored charge QrrAlso results in a characteristic on-resistance R at forward conductionon,spThis means that there is a trade-off between reverse recovery stored charge and characteristic on-resistance for SJ-VDMOS, as shown in fig. 8. The figure of merit is an important parameter for balancing the merits of the relationship between the reverse recovery stored charge and the characteristic on-resistance, as shown in fig. 9, the figure of merit of the proposed structure is reduced by 94.9% compared with the figure of merit of the conventional structure, which represents the overall superiority of the proposed structure in forward conduction and reverse recovery.
3. The present invention utilizes integrated NMOS and SJ-VDMOS with the same gate and source so that in the inventive structure, driving can be done as with conventional SJ-VDMOS. When conducting in the forward direction, in the circuit schematic diagram of fig. 3, the gate is connected with high potential, the source (drain of NMOS) is connected with 0 potential, the drain of the SJ-VDMOS is connected with high potential, at this time, the channels of NMOS and SJ-VDMOS are simultaneously opened, and the drain current flows from the drain to the source; and when the reverse voltage is resisted, the grid electrode and the source electrode are grounded in a short circuit mode, the drain electrode is connected with high potential, and the reverse bias PN junction formed by the N-type voltage withstanding layer, the P-pilar and the P-body is used for resisting voltage.
4. The invention realizes excellent leakage characteristics by utilizing the characteristic that reverse recovery characteristics can be greatly improved under the condition of extremely small Schottky contact area. The traditional SJ-VDMOS device of the parallel Schottky diode needs a larger Schottky contact area to obtain a good reverse recovery effect, and the larger Schottky area can cause the reverse bias leakage current of the SJ-VDMOS to be obviously increased. In the structure of the invention, by utilizing the characteristic that the follow current only flows through the Schottky diode, the follow current can be realized only by a very small Schottky area, so that the excellent leakage characteristic is realized, as shown in a comparison graph of the reverse bias characteristic of the traditional SJ-VMOS and the proposed structure of which the ratio K of the Schottky area in the whole cell is 9.9 percent in fig. 7.
Drawings
Fig. 1 is a view showing a structure of a conventional SJ-MOSFET.
Fig. 2-1 and 2-2 are structural diagrams of the proposed SJ-MOSFET, in which fig. 2-1 is an overall structural diagram of the proposed SJ-MOSFET, and fig. 2-2 is a partially enlarged structural diagram of an NMOS transistor in the proposed SJ-MOSFET.
Fig. 3 is a diagram showing the construction of the proposed SJ-MOSFET circuit.
FIGS. 4-1 and 4-2 are diagrams illustrating the operation of the proposed structure, wherein FIG. 4-1 is an equivalent circuit diagram of the freewheeling stage of the proposed SJ-VDMOS device, and FIG. 4-2 is an equivalent circuit diagram of the reverse recovery process of the proposed SJ-VDMOS device
FIG. 5-1 is a graph showing a comparison of hole concentration distributions when two structures are turned on in the forward direction.
Fig. 5-2 is a graph showing a comparison of electron concentration distributions when the two structures are turned on in the forward direction.
Fig. 6 is a graph comparing the reverse recovery waveforms of body diode current for two structures.
Fig. 7 is a graph showing a comparison of the reverse bias characteristics of the two structures.
FIG. 8 shows Q of the proposed structurerrAnd Ron,spThe relationship of (c) is compared with the graph.
Figure 9 shows a figure of merit comparison for two configurations.
Detailed Description
The super-junction power VDMOS comprises a super-junction VDMOS, the super-junction VDMOS comprises an N-type substrate 1 which is also used as a drain electrode and an N-type drift region 2 arranged on the N-type substrate 1, and is characterized in that a first P column 31 is arranged in the N-type drift region 2 of the super-junction VDMOS, a first P type body region 41 is arranged at the top of the first P column 31, the top surface of the first P type body region 41 is flush with the top surface of the N-type drift region 2, an N MOS tube 101 is arranged on the first P type body region 41, and an SiO (silicon dioxide) layer is arranged between the N MOS tube 101 and the first P type body region 412The isolation layer 12 is further provided with a first P-type heavily doped region 10A on the first P-type body region 41, and the source metal of the super-junction VDMOS, the source metal of the N MOS tube 101 and the first P-type heavily doped region 10A are connected; the drain electrode of the super-junction VDMOS is used as the drain electrode of the super-junction power VDMOS, and the grid electrode of the super-junction VDMOS and the grid electrode of the N MOS tube 101The drain electrode of the NMOS tube 101 is used as the source electrode of the super junction power VDMOS; a schottky contact 9 is further arranged on the N-type drift region 2 of the super-junction VDMOS, and the schottky contact 9 is connected with the drain of the N MOS transistor 101, thereby forming a schottky diode with a cathode connected to the drain of the super-junction power VDMOS and an anode connected to the source of the super-junction power VDMOS. In the present embodiment, it is preferred that,
the super-junction VDMOS is further provided with a second P column 32 in the N-type drift region 2, a second P-type body region 42 is arranged at the top of the second P column 32, the top surface of the second P-type body region 42 is flush with the top surface of the N-type drift region 2, an N-type heavily doped source region 5 of the super-junction VDMOS is arranged in the second P-type body region 42, a source metal 8 is connected to the N-type heavily doped source region 5 of the super-junction VDMOS, a gate oxide layer 6 containing first gate conductive polysilicon 7 is arranged above the N-type heavily doped source region 5 of the super-junction VDMOS, the first gate conductive polysilicon 7 is a gate of the super-junction VDMOS, and the gate oxide layer 6 and the gate conductive polysilicon 7 extend through the second P-type body region 42 and enter the upper part of the N-type drift region 2.
The N MOS tube 101 comprises a P-type substrate region 11, an N-type heavily doped drain region 13, an N-type heavily doped source region 51 and a second P-type heavily doped region 10B which is in contact with the N-type heavily doped source region 51 of the N MOS tube 101 are arranged at the top of the P-type substrate region 11, drain metal 14 is connected to the N-type heavily doped drain region 13, source metal 8 is connected to the N-type heavily doped source region 51 and the second P-type heavily doped region 10B, a second gate oxide layer 62 which contains second gate conductive polysilicon 72 is arranged on the N-type heavily doped drain region 13, the second gate oxide layer 62 and the second gate conductive polysilicon 72 are gates of the heavily doped NMOS tube 101, and the second gate oxide layer 62 and the second gate conductive polysilicon 72 extend through the P-type substrate region 11 and enter the upper portion of the N-type source region 51.
The Schottky contacts 9 are respectively positioned between the first P-type body region 41 and the second P-type body region 42 and outside the first P-type body region 41 and the second P-type body region 42, and have a length of 2-3 μm.
SiO2The depth of the isolation layer 12 is 4.8 μm to 5.2 μm, the width is 1.9 μm to 2.1 μm, and the thickness is
The concentration of the P-type substrate region 11 of the NMOS tube is 1e16cm-3The length of the gate oxide layer is 1.2-1.6 μm.
The invention is further described below with reference to the accompanying drawings.
The working principle of the invention is as follows:
the proposed SJ-VDMOS device structure is shown in fig. 3.
Forward conduction: when the grid and the drain of the structure are connected with high potential and the source is connected with low potential, the electronic channels in the NMOS and the SJ-VDMOS inside the structure are simultaneously opened, and under the action of the high potential of the drain, the electronic current flowing from the drain to the source is formed.
Reverse turn-off: when the grid and the source of the structure are connected together in short and connected with a low potential and the drain is connected with a high potential, a reverse bias PN junction formed by the N-type voltage-resisting layer, the P-pilar and the P-body bears the reverse bias voltage.
And (3) a follow current process: in the circuit diagram shown in fig. 4-1, the gate and the source are shorted and connected to a high potential, the drain is connected to a low potential, the channel is turned off, and the reverse biased PN junction in the NMOS blocks the follow current from flowing through the body diode of the conventional SJ-VDMOS, and the follow current flows into the N-type voltage-withstanding layer only through the schottky electrode and then flows out through the drain. Since the body diode of the SJ-VDMOS is not turned on during the freewheeling period, the freewheeling current flowing through the device during the freewheeling period is almost entirely composed of the electron current, so that the total amount of holes stored in the N-type voltage-withstanding layer is almost 0, as shown in fig. 5-1 and 5-2, the electron current density in the voltage-withstanding layer is high and the hole current density is very low.
And (3) reverse recovery process: as shown in fig. 4-2, when the external voltage condition gradually changes from the state in the freewheeling process to the state in which the gate and the source are shorted and connected to the low potential and the drain is connected to the high potential, the reverse recovery process occurs. Since the total amount of holes stored in the N-type voltage-withstanding layer is almost zero during the freewheeling period, the space charge region in the N-type voltage-withstanding layer can be quickly depleted for withstanding voltage, and excellent reverse recovery characteristics, such as extremely fast reverse recovery time t, can be realizedrrExtremely low reverse recovery stored charge QrrThe higher softness factor S, as shown in fig. 6 by comparing the reverse recovery waveform of the conventional SJ-VDMOS with the proposed structure having a schottky duty K of 9.9%.
Claims (6)
1. The super-junction power VDMOS comprises a super-junction VDMOS, the super-junction VDMOS comprises an N-type substrate (1) which is also used as a drain electrode and an N-type drift region (2) arranged on the N-type substrate (1), and is characterized in that a first P column (31) is arranged in the N-type drift region (2) of the super-junction VDMOS, a first P body region (41) is arranged at the top of the first P column (31), the top surface of the first P body region (41) is flush with the top surface of the N-type drift region (2), an NMOS tube (101) is arranged on the first P body region (41), and SiO (silicon dioxide) is arranged between the NMOS tube (101) and the first P body region (41)2The isolation layer (12) is further provided with a first P-type heavily doped region (10A) on the first P-type body region (41), and the source metal of the super-junction VDMOS, the source metal of the NMOS tube (101) and the first P-type heavily doped region (10A) are connected; the drain electrode of the super-junction VDMOS serves as the drain electrode of the super-junction power VDMOS, the grid electrode of the super-junction VDMOS is connected with the grid electrode of the NMOS tube (101) and serves as the grid electrode of the super-junction power VDMOS, and the drain electrode of the NMOS tube (101) serves as the source electrode of the super-junction power VDMOS; a Schottky contact (9) is further arranged on the N-type drift region (2) of the super-junction VDMOS, the Schottky contact (9) is connected with the drain electrode of the NMOS tube (101), and therefore a Schottky diode with a cathode connected to the drain electrode of the super-junction power VDMOS and an anode connected to the source electrode of the super-junction power VDMOS is formed.
2. The very low reverse recovery charge superjunction power VDMOS of claim 1, the super-junction VDMOS is provided with a second P column (32) in the N-type drift region (2), a second P-type body region (42) is arranged at the top of the second P column (32), the top surface of the second P-type body region (42) is flush with the top surface of the N-type drift region (2), an N-type heavily doped source region (5) of the super-junction VDMOS is arranged in the second P-type body region (42), a source metal (8) is connected on an N-type heavily doped source region (5) of the super-junction VDMOS, a gate oxide layer (6) internally containing first gate conductive polysilicon (7) is arranged above an N-type heavily doped source region (5) of the super-junction VDMOS, and the first gate conductive polysilicon (7) is a gate of the super-junction VDMOS, the gate oxide layer (6) and the gate conductive polysilicon (7) extend through the second P-type body region (42) and into the upper part of the N-type drift region (2).
3. The very low reverse recovery charge super-junction power VDMOS of claim 1, wherein the NMOS transistor (101) comprises a P-type substrate region (11), an N-type heavily doped drain region (13) of the NMOS transistor (101), an N-type heavily doped source region (51) and a second P-type heavily doped region (10B) contacting the N-type heavily doped source region (51) are disposed on top of the P-type substrate region (11), a drain metal (14) is connected to the N-type heavily doped drain region (13), a source metal (8) is connected to the N-type heavily doped source region (51) and the second P-type heavily doped region (10B), a second gate oxide layer (62) encapsulating a second gate conductive polysilicon (72) is disposed on the N-type heavily doped drain region (13) and the second gate conductive polysilicon (72) is a gate of the NMOS transistor (101), the second gate oxide layer (62) and the second gate conductive polysilicon (72) extend through the P-type substrate region (11) and into the N-type substrate region (11) And the source region (51) is heavily doped.
4. The VDMOS of claim 1, wherein the Schottky contact (9) is between the first and second P-type body regions (41, 42) and outside the first and second P-type body regions (41, 42) and has a length of 2-3 μm.
5. The very low reverse recovery charge superjunction power VDMOS of claim 1, wherein SiO is2The depth of the isolation layer (12) is 4.8-5.2 μm, the width is 1.9-2.1 μm, and the thickness is
6. The very low reverse recovery charge super junction power VDMOS of claim 3, wherein the concentration of the P-type substrate region (11) of the NMOS transistor is 1e16cm-3The length of the gate oxide layer is 1.2-1.6 μm.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910055794.4A CN109830524B (en) | 2019-01-21 | 2019-01-21 | Super-junction power VDMOS with extremely low reverse recovery charge |
| PCT/CN2019/081816 WO2020151088A1 (en) | 2019-01-21 | 2019-04-08 | Super-junction power vdmos having extremely low reverse recovery charge |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910055794.4A CN109830524B (en) | 2019-01-21 | 2019-01-21 | Super-junction power VDMOS with extremely low reverse recovery charge |
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| Publication Number | Publication Date |
|---|---|
| CN109830524A CN109830524A (en) | 2019-05-31 |
| CN109830524B true CN109830524B (en) | 2020-12-11 |
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| CN110828580B (en) * | 2019-10-31 | 2023-03-24 | 东南大学 | Fast recovery bootstrap diode for improving reverse recovery robustness |
| CN111223937B (en) * | 2020-01-17 | 2021-04-23 | 电子科技大学 | GaN longitudinal field effect transistor with integrated freewheeling diode |
| CN111769158B (en) * | 2020-05-21 | 2022-08-26 | 南京邮电大学 | Double-channel super-junction VDMOS device with low reverse recovery charge and manufacturing method |
| CN111969062B (en) * | 2020-09-21 | 2021-06-04 | 电子科技大学 | Super-junction MOSFET (metal-oxide-semiconductor field effect transistor) with improved reverse recovery characteristic |
| CN112383296B (en) * | 2020-11-13 | 2024-03-29 | 奇普电源(常州)有限公司 | Bidirectional combined switch |
| CN116827322A (en) * | 2022-03-21 | 2023-09-29 | 苏州东微半导体股份有限公司 | Semiconductor power device |
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| US7045830B1 (en) * | 2004-12-07 | 2006-05-16 | Fairchild Semiconductor Corporation | High-voltage diodes formed in advanced power integrated circuit devices |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
| WO2016063681A1 (en) * | 2014-10-24 | 2016-04-28 | 富士電機株式会社 | Semiconductor device |
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| CN202616237U (en) * | 2012-04-06 | 2012-12-19 | 东南大学 | Rapid super junction VDMOS |
| CN103489917B (en) * | 2013-10-22 | 2016-09-21 | 东南大学 | A kind of vertical double-diffused MOS structure of high snow slide tolerance ability |
| CN108550623A (en) * | 2018-03-09 | 2018-09-18 | 深圳深爱半导体股份有限公司 | It is integrated with enhanced and device and its manufacturing method of depletion type VDMOS |
| CN108899370B (en) * | 2018-08-22 | 2024-03-15 | 江苏中科君芯科技有限公司 | VDMOS device integrated with resistor area |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US7045830B1 (en) * | 2004-12-07 | 2006-05-16 | Fairchild Semiconductor Corporation | High-voltage diodes formed in advanced power integrated circuit devices |
| CN101510557A (en) * | 2008-01-11 | 2009-08-19 | 艾斯莫斯技术有限公司 | Superjunction device having a dielectric termination and methods for manufacturing the device |
| WO2016063681A1 (en) * | 2014-10-24 | 2016-04-28 | 富士電機株式会社 | Semiconductor device |
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