CN111799337A - SiC JBS diode device and preparation method thereof - Google Patents
SiC JBS diode device and preparation method thereof Download PDFInfo
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- CN111799337A CN111799337A CN202010733250.1A CN202010733250A CN111799337A CN 111799337 A CN111799337 A CN 111799337A CN 202010733250 A CN202010733250 A CN 202010733250A CN 111799337 A CN111799337 A CN 111799337A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 9
- 238000002347 injection Methods 0.000 claims abstract description 43
- 239000007924 injection Substances 0.000 claims abstract description 43
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 238000000034 method Methods 0.000 claims description 44
- 238000000151 deposition Methods 0.000 claims description 25
- 238000001259 photo etching Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 21
- 239000002184 metal Substances 0.000 claims description 21
- 238000005530 etching Methods 0.000 claims description 17
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 12
- 229910052799 carbon Inorganic materials 0.000 claims description 12
- 238000009616 inductively coupled plasma Methods 0.000 claims description 12
- 238000000137 annealing Methods 0.000 claims description 11
- 150000002500 ions Chemical class 0.000 claims description 11
- 230000003213 activating effect Effects 0.000 claims description 6
- 238000004140 cleaning Methods 0.000 claims description 6
- 229910052681 coesite Inorganic materials 0.000 claims description 6
- 229910052906 cristobalite Inorganic materials 0.000 claims description 6
- 238000002955 isolation Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000004151 rapid thermal annealing Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052682 stishovite Inorganic materials 0.000 claims description 6
- 229910052905 tridymite Inorganic materials 0.000 claims description 6
- 239000007943 implant Substances 0.000 claims description 5
- 238000004519 manufacturing process Methods 0.000 claims description 4
- 229910052759 nickel Inorganic materials 0.000 claims description 4
- 229910052719 titanium Inorganic materials 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 238000001465 metallisation Methods 0.000 claims description 3
- 230000003071 parasitic effect Effects 0.000 abstract description 5
- 238000004377 microelectronic Methods 0.000 abstract description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 34
- 229910010271 silicon carbide Inorganic materials 0.000 description 33
- 239000000463 material Substances 0.000 description 7
- 238000002513 implantation Methods 0.000 description 5
- 238000005137 deposition process Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000001000 micrograph Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
Abstract
The invention discloses a SiC JBS diode device and a preparation method thereof, belonging to the technical field of microelectronics, and comprising a cathode, an N + substrate, an N-epitaxial layer, a P + injection region and an anode which are sequentially arranged from bottom to top, wherein a groove structure is arranged between the two P + injection regions; according to the invention, the groove structure is arranged below the Schottky contact surface between the two P + injection regions, the introduction of the groove can increase the Schottky contact area, reduce the parasitic resistance, reduce the on-resistance, enable the device to be easier to open, and solve the problem of overlarge on-resistance caused by lack of carrier modulation of the traditional SiC JBS diode.
Description
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a SiC JBS diode device and a preparation method thereof.
Background
In recent years, with the continuous development of power electronic systems, higher requirements are put on power devices in the systems. Si-based power electronics have not been able to meet the requirements of system applications due to the limitations of the materials themselves. Silicon carbide (SiC) materials, as representative of third generation semiconductor materials, are far better than Si materials in many properties.
In SiC power systems, a good rectifier requires a small turn-on voltage, a large conduction current, a low leakage current, a high breakdown voltage and a high switching speed, while having these characteristics is the most desirable goal we pursue. JBS (J-shaped Barrier Schottky) is a device combining the advantages of Pin and SBD, the forward characteristic of the structure is similar to that of SBD, and the structure has small starting voltage, large conduction current and fast switching speed; the reverse characteristic is more like a PiN diode, and has low leakage current and high breakdown voltage. The use of the JBS structure allows us to flexibly select metals with low barrier as schottky contacts without worrying about increased reverse leakage current. In addition, the excellent performance of the SiC material can exert greater advantages by combining with the advantages of the JBS structure, and the SiC material also becomes the development trend of the current power rectifying device.
As shown in fig. 1, the conventional SiC JBS diode structure includes a cathode, an N + substrate, an N-epitaxial layer, a P + injection region, and an anode sequentially arranged from bottom to top, and when the conventional SiC JBS diode is turned on in the forward direction, the current density is slightly lower due to the P-type region, and the on-resistance is too large, which increases the difficulty in turning on the device.
Disclosure of Invention
In order to solve the problems, the invention provides a SiC JBS diode device and a preparation method thereof, wherein the introduction of a groove can increase the Schottky contact area, reduce the parasitic resistance and reduce the on-resistance, thereby reducing the forward starting voltage and enabling the device to be easier to start.
The invention provides a SiC JBS diode device, which comprises a cathode, an N + substrate, an N-epitaxial layer, P + injection regions and an anode which are arranged from bottom to top in sequence, wherein a groove structure is arranged between the two P + injection regions and is positioned below a Schottky contact interface between the two P + injection regions, and the depth of the groove structure is smaller than that of the P + injection regions.
Preferably, the depth of the groove structure is 0.5-1 μm, and the width is 1-3 μm.
Preferably, the difference between the depth of the groove structure and the depth of the P + injection region is 0.1-3 μm.
Preferably, the distance between the edge of the groove structure and the two P + injection regions is equal and is 0.2-0.8 μm.
Preferably, the metal in contact with the schottky contact interface is Ti or Ni.
The second object of the present invention is to provide a method for manufacturing the SiC JBS diode device, comprising the following steps:
s1, forming an N-epitaxial layer on the N + substrate through epitaxial growth; generally, the overall structure after the N-epitaxial layer is formed is called an epitaxial wafer;
s2 preparation of SiO on N-epitaxial layer2A mask layer, forming a mask pattern by using a photoetching process, and forming a groove structure by using an ICP (inductively coupled plasma) etching method;
s3, cleaning the injection mask layer, forming a new mask layer on the surface, forming a mask pattern by using a photoetching process, and forming a P + injection region by using an Al ion injection means;
s4, performing carbon film protection on the surface of the N-epitaxial layer, activating implanted ions through high-temperature annealing, and removing the carbon film through an oxidation method;
s5 deposition of SiO2Forming an isolation medium, photoetching and etching to form a P + injection region Schottky contact region, depositing Schottky contact metal on the front surface and the back surface of the epitaxial wafer, etching to form a Schottky contact window at the front surface groove structure, depositing Schottky metal, and etching to form a Schottky contact window at the front surface groove structureForming an electrode pattern by a photoetching process, and forming Schottky contact in the groove structure region by a low-temperature rapid thermal annealing process;
and S6, forming thick electrodes on the front surface and the back surface of the epitaxial wafer through a metal deposition process.
Compared with the prior art, the invention has the following beneficial effects:
compared with the traditional SiC JBS diode device, the Schottky contact area between the two P + injection regions is increased by the groove structure arranged below the Schottky contact surface, the parasitic resistance is reduced, and the on-resistance is reduced, so that the forward starting voltage is reduced, the device is easier to start, and the problem of overlarge on-resistance caused by lack of carrier modulation of the traditional SiC JBS diode is solved.
Drawings
FIG. 1 is a schematic cross-sectional view of a conventional SiC JBS diode device;
FIG. 2 is a schematic cross-sectional view of a SiC JBS diode device structure provided by the present invention;
FIG. 3 is an SEM scanning electron microscope image of a SiC JBS diode device prepared in example 1 of the present invention;
fig. 4 is a forward characteristic curve of a SiC JBS diode device made in example 1 of the present invention;
fig. 5 is a reverse characteristic curve of the SiC JBS diode device manufactured in example 1 of the present invention.
Description of reference numerals:
wherein, 1, anode; 2. a P + implantation region; 3. an N-epitaxial layer; 4. an N + substrate; 5. a cathode; 6. and (5) a groove structure.
Detailed Description
In order to make the technical solutions of the present invention better understood and implemented by those skilled in the art, the present invention is further described below with reference to the following specific embodiments and the accompanying drawings, but the embodiments are not meant to limit the present invention. The following detection methods, unless otherwise specified, are all conventional methods; the materials are commercially available unless otherwise specified.
The invention provides a SiC JBS diode device, which comprises a cathode 5, an N + substrate 4, an N-epitaxial layer 3, P + injection regions 2 and an anode 1, wherein the cathode, the N + substrate, the N-epitaxial layer, the P + injection regions 2 and the anode 1 are sequentially arranged from bottom to top, a groove structure 6 is arranged between the two P + injection regions 2, the groove structure 6 is positioned below a Schottky contact interface between the two P + injection regions 2, and the depth of the groove structure 6 is smaller than that of the P + injection regions 2.
According to the invention, the groove structure is arranged below the Schottky contact surface between the two P + injection regions, the introduction of the groove can increase the Schottky contact area, reduce the parasitic resistance, reduce the on-resistance, enable the device to be easier to open, and solve the problem of overlarge on-resistance caused by lack of carrier modulation of the traditional SiC JBS diode.
The preparation method of the SiC JBS diode device specifically comprises the following steps:
(1) forming an N-epitaxial layer 3 on an N + substrate 4 through epitaxial growth; generally, the overall structure after the N-epitaxial layer is formed is called an epitaxial wafer;
(2) preparation of SiO on N-epitaxial layer 32A mask layer, wherein a mask pattern is formed by using a photoetching process, and a groove structure 6 is formed by using an ICP (inductively coupled plasma) etching method;
(3) cleaning the mask layer, forming a new mask layer on the surface through a deposition process, forming a mask pattern through a photoetching process, and forming a P + injection region 2 through an Al ion injection means;
(4) performing carbon film protection on the surface of the N-epitaxial layer 3, activating implanted ions through high-temperature annealing, and removing the carbon film through an oxidation method;
(5) deposition of SiO2Forming an isolation medium, photoetching and etching to form a P + injection region 2 Schottky contact surface, depositing Schottky contact metal on the front surface and the back surface of the N-epitaxial layer 3, etching at the front surface groove structure to form a Schottky contact window, depositing the Schottky contact metal, forming an electrode pattern through a photoetching process, and forming Schottky contact in a Schottky region through a low-temperature rapid thermal annealing process;
(6) and forming thick electrodes on the front surface and the back surface by a metal deposition process.
The above SiC JBS diode device and the method of making the same are specifically illustrated by the following examples.
Example 1
A SiC JBS diode device structure integrated with a trench structure comprises an N + substrate 4 with a doping concentration of 5 × 1018cm-3Is 350 mu m thick, and the lightly doped N-epitaxial layer 3 is positioned on the substrate layer 4; the cathode 5 is located below the N + substrate 4; the surface of the N-epitaxial layer 3 is provided with a groove structure 6; the P + injection region 2 is positioned on the surface of the N-epitaxial layer 3 around the groove structure 6; the anode 1 covers the entire surface of the P + implant region 2 and the surface of the trench structure 6.
The process comprises the following steps:
in a first step, an N-epitaxial layer 3 is formed on an N + substrate 4 by epitaxial growth, the concentration of the N-epitaxial layer being 6X 1015cm-3Thickness 10 μm; generally, the overall structure after the N-epitaxial layer is formed is called an epitaxial wafer;
second, SiO is deposited on the N-epitaxial layer 32A mask layer with a mask thickness of 2 μm; forming a mask pattern by a photoetching process; forming a groove structure 6 by an ICP (inductively coupled plasma) etching method, wherein the width of the groove structure 6 is 1 mu m, and the depth of the groove structure 6 is 0.5 mu m;
thirdly, cleaning the mask layer, forming a mask pattern on the surface of the mask layer through a new mask layer of a deposition process and a photoetching process; forming a P + implantation region 2 structure by Al ion implantation, wherein the surface concentration of the P + implantation region 2 is 1 × 1019cm-3The thickness is 0.8 μm, and the distance between the edge of the trench structure 6 and the P + implantation region 2 is 0.5 μm;
fourthly, performing carbon film protection on the surface of the epitaxial layer by using a C film sputtering machine, and activating implanted ions by high-temperature annealing at 1650 ℃ for 45 min; removing the carbon film by an oxidation method;
the fifth step, deposit SiO2And forming an isolation medium, and photoetching to form a P + region Schottky contact region. Depositing Schottky contact metal Ni on the front surface and the back surface of the epitaxial wafer, etching at the front surface groove to form a Schottky contact window, depositing the Schottky contact metal Ni, forming an electrode pattern through a photoetching process, and performing a low-temperature rapid thermal annealing process on the Schottky regionForming Schottky contact in the region, and annealing at 700 deg.C for 2 min;
and sixthly, depositing Al metal on the front surface to form an anode, and depositing Ti, Ni or Ag metal on the back surface to form a back electrode.
Example 2
A SiC JBS diode device structure integrated with a trench structure comprises an N + substrate 4 with a doping concentration of 5 × 1018cm-3Is 350 μm thick, and the lightly doped N-epitaxial layer 3 is located on the N + substrate layer 4; the cathode 5 is located below the N + substrate 4; the surface of the N-epitaxial layer 3 is provided with a groove structure 6; the P + injection region 2 is positioned on the surface of the N-epitaxial layer 3 around the groove structure 6; the anode 1 covers the entire surface of the P + implant region 2 and the surface of the trench structure 6.
The process comprises the following steps:
and 6, forming an anode on the front surface by depositing Al metal, and forming a back electrode on the back surface by depositing Ti/Ni/Ag metal.
Example 3
A SiC JBS diode device structure integrated with a trench structure comprises an N + substrate 4 with a doping concentration of 5 × 1018cm-3Is 350 μm thick, and the lightly doped N-epitaxial layer 3 is located on the N + substrate layer 4; the cathode 5 is located below the N + substrate 4; the surface of the N-epitaxial layer 3 is provided with a groove structure 6; the P + injection region 2 is positioned on the surface of the N-epitaxial layer 3 around the groove structure 6; the anode 1 covers the entire surface of the P + implant region 2 and the surface of the trench structure 6.
The process comprises the following steps:
and 6, depositing Al metal on the front surface to form an anode, and depositing Ti, Ni or Ag metal on the back surface to form a back electrode.
The SiC JBS diode devices prepared in examples 1 to 3 were similar, and their performance will be specifically described below by taking only the SiC JBS diode device prepared in example 1 as an example.
Fig. 3 is an SEM scanning electron microscope image of the SiC JBS diode device manufactured in example 1 of the present invention, which can be obtained from fig. 3, and the manufacturing of the trench structure can be achieved by the process of the present invention; fig. 4 is a forward characteristic curve of the SiC JBS diode device manufactured in example 1, and as can be analyzed from fig. 4, the forward turn-on voltage of the trench-integrated SiC JBS device is reduced by about 0.15V compared to the conventional SiC JBS device, because the schottky contact area is increased, the on-resistance of the device is reduced, and the device is more easily turned on, and thus it can be seen that the turn-on voltage of the device continues to be reduced as the trench depth and the trench width are increased and the schottky contact area is increased; fig. 5 is a reverse characteristic curve of the SiC JBS diode device manufactured in embodiment 1 of the present invention, and from fig. 5, the SiC JBS device integrated with the trench has a reverse leakage magnitude substantially consistent with that of the planar structure under the condition that a good forward effect is obtained, so that the stability of the device in the reverse direction is ensured. Therefore, the groove structure is arranged below the Schottky contact surface between the two P + injection regions, the Schottky contact area can be increased by introducing the groove, the parasitic resistance is reduced, and the on-resistance is reduced, so that the forward on-voltage is reduced, the device is easier to turn on, and the problem of overlarge on-resistance caused by lack of carrier modulation of the traditional SiC JBS diode is solved.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, it is intended that such changes and modifications be included within the scope of the appended claims and their equivalents.
Claims (6)
1. The utility model provides a SiC JBS diode device, includes negative pole (5), N + substrate (4), N-epitaxial layer (3), P + injection zone (2) and positive pole (1) that set gradually from bottom to top, its characterized in that, two be provided with trench structure (6) between P + injection zone (2), trench structure (6) are located the Schottky contact interface below between two P + injection zones (2), the degree of depth of trench structure (6) is less than the degree of depth of P + injection zone (2).
2. The SiC JBS diode device of claim 1, wherein the trench structure (6) has a depth of 0.5 to 1 μm and a width of 1 to 3 μm.
3. The SiC JBS diode device of claim 2, wherein the difference between the depth of the trench structure (6) and the depth of the P + implant region (2) is 0.1-3 μm.
4. The SiC JBS diode device of claim 1, wherein the edge of the trench structure (6) is equally spaced from the two P + implant regions (2), each 0.2-0.8 μm.
5. The SiC JBS diode device of claim 1, wherein the metal in contact with the schottky contact interface is Ti or Ni.
6. The method of manufacturing a SiC JBS diode device of claim 1, comprising the steps of:
s1, forming an N-epitaxial layer (3) on the N + substrate (4) through epitaxial growth;
s2 preparation of SiO on N-epitaxial layer (3)2A mask layer, a mask pattern is formed by using a photoetching process, and a groove structure (6) is formed by using an ICP (inductively coupled plasma) etching method;
s3, cleaning the injection mask layer, forming a new mask layer on the surface, forming a mask pattern by using a photoetching process, and forming a P + injection region (2) by using an Al ion injection means;
s4, performing carbon film protection on the surface of the N-epitaxial layer (3), activating implanted ions through high-temperature annealing, and removing the carbon film through an oxidation method;
s5 deposition of SiO2Forming an isolation medium, photoetching and etching to form a P + injection region (2) Schottky contact region, depositing Schottky contact metal on the front surface and the back surface of the epitaxial wafer, etching at the front surface groove structure (6) to form a Schottky contact window, depositing the Schottky contact metal, forming an electrode pattern through a photoetching process, and forming Schottky contact in the groove structure region through a low-temperature rapid thermal annealing process;
and S6, forming thick electrodes on the front surface and the back surface of the epitaxial wafer through a metal deposition process.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114464531A (en) * | 2022-04-13 | 2022-05-10 | 深圳芯能半导体技术有限公司 | Structure and manufacturing method of silicon carbide Schottky diode and power electronic equipment |
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2020
- 2020-07-27 CN CN202010733250.1A patent/CN111799337A/en active Pending
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| JP2000031505A (en) * | 1998-07-10 | 2000-01-28 | Sanyo Electric Co Ltd | Schottky barrier diode |
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