CN213816160U

CN213816160U - SiC double-groove MOSFET device

Info

Publication number: CN213816160U
Application number: CN202022709828.8U
Authority: CN
Inventors: 卢小东
Original assignee: Huaxinwei Semiconductor Technology Beijing Co ltd
Current assignee: Huaxinwei Semiconductor Technology Beijing Co ltd
Priority date: 2020-11-20
Filing date: 2020-11-20
Publication date: 2021-07-27
Anticipated expiration: 2030-11-20

Abstract

The utility model discloses a SiC double-groove MOSFET device, the primitive cell structure of the active area of the device is a drain electrode, an n + substrate, an n-drift layer, a p base region, an n + layer, a grid electrode, an insulating layer and a source electrode from bottom to top in sequence; two grooves are arranged in the cell structure, and the two grooves are of a symmetrical structure in the active region. The two grooves are arranged in the cell structure, so that the reliability of the device is improved, and the breakdown voltage of the device is enhanced; the requirements for manufacturing high-voltage and high-current power silicon carbide MOSFET modules can be met.

Description

SiC double-groove MOSFET device

Technical Field

The utility model belongs to the technical field of the semiconductor device technique and specifically relates to a two slot type MOSFET devices of SiC is related to.

Background

Silicon carbide has good physical properties compared to silicon, such as a band gap of about 3 times that of silicon, a breakdown field strength of about 10 times that of silicon, and a thermal conductivity of about 3 times that of silicon. By utilizing such physical characteristics, a low-loss, high-operating-temperature semiconductor device can be realized. When a short circuit occurs in a load, a MOSFET (metal oxide semiconductor field effect transistor) using silicon carbide is turned on, and a high voltage is applied between the drain and source of the MOSFET. When a high voltage is applied between the drain and source, the MOSFET breaks down. The breakdown of the MOSFET is considered to be caused by the generation of thermal effects due to the flow of a large current. In order to avoid breakdown of the MOSFET, it is necessary to extend the time from short-circuiting of the load to breakdown of the MOSFET, and it is necessary to improve the short-circuit withstanding capability.

At present, in the field of high-temperature and high-current modules, the main problems are that silicon carbide power devices are poor in consistency and low in reliability, and the reliability of the devices is greatly improved by adopting a double-channel structure.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a two slot type MOSFET devices of SiC to solve the problem that exists among the prior art.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

the utility model provides a SiC double-groove MOSFET device, the primitive cell structure of the active area of the device is a drain electrode, an n + substrate, an n-drift layer, a p base region, an n + layer, a grid electrode, an insulating layer and a source electrode from bottom to top in sequence; two grooves are arranged in the cell structure, and the two grooves are of a symmetrical structure in the active region.

As a further feature, a p + region under the trench is in electrical communication with the source and the p-base regions.

As a further technical scheme, the doping concentration of the p base region is 1E15-5E17cm-³The thickness of the p base region is 0.2-3 μm.

As a further technical proposal, the doping concentration of the n + layer is more than 1E19cm-³And the thickness of the n + layer is 0.2-2 μm.

As a further technical scheme, the p-type doped region at the bottom of the groove is electrically communicated with the p-base region through the doping of the side wall of the groove.

As a further technical solution, a current spreading region is disposed between the n-drift layer and the p-base region.

Adopt above-mentioned technical scheme, the utility model discloses following beneficial effect has:

the two grooves are arranged in the cell structure, so that the reliability of the device is improved, and the breakdown voltage of the device is enhanced; the requirements for manufacturing high-voltage and high-current power silicon carbide MOSFET modules can be met.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a cell structure of a SiC double trench MOSFET device of the present invention;

icon: the transistor comprises a 1-source electrode, a 2-insulating layer, a 3-n + layer, a 4-p base region, a 5-grid electrode, a 6-groove, a 7-current dispersion region, an 8-p + region, a 9-n-drift layer, a 10-n + substrate and an 11-drain electrode.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.

Referring to fig. 1, the present embodiment provides a SiC double trench MOSFET device, where a cell structure of an active region of the device includes, from bottom to top, a drain 11, an n + substrate 10, an n-drift layer 9, a p-base region 4, an n + layer 3, a gate 5, an insulating layer 2, and a source 1; two grooves 6 are arranged in the cell structure, and the two grooves 6 are of a symmetrical structure in the active region.

In this embodiment, as a further technical solution, the p + region 8 under the trench 6 is electrically communicated with the source 1 and the p-base region 4.

In the embodiment, as a further technical scheme, the doping concentration of the p base region 4 is 1E15-5E17cm^-3The thickness of the p-base region 4 is 0.2-3 μm.

In this embodiment of the present invention,as a further technical scheme, the doping concentration of the n + layer 3 is more than 1E19cm^-3And the thickness of the n + layer 3 is 0.2-2 μm.

In this embodiment, as a further technical solution, the p-type doped region at the bottom of the trench 6 and the p-base region 4 are electrically connected by doping the sidewall of the trench 6.

In this embodiment, as a further technical solution, a current spreading region 7 is disposed between the n-drift layer 9 and the p-base region 4. The current spreading region 7 is used for storing redundant charges and reducing reverse leakage current.

The path of the SiC double-groove MOSFET device is as follows:

1) sequentially preparing an n-drift layer, a p base region and an n + layer on a substrate;

2) making a first patterned mask layer on the SiC surface, preparing by CVD method, and forming SiO by photoetching method₂A graph; etching the SiC groove by an ICP method to form a source groove and a grid groove; simultaneously, etching the junction terminal area and the scribing area;

3) making a second mask layer on the surface of the SiC, taking the second mask layer as a mask for subsequent injection, performing Al ion injection, and forming doping on the side wall and the periphery of the bottom of the double-groove, wherein the injection direction is a direction vertical to the wafer direction and a direction with a set inclination angle; removing SiO at the bottom of the gate trench by ICP anisotropic etching₂Dielectric while continuing to retain SiO on the sidewall of the gate trench₂A dielectric protecting the gate channel region; injecting Al ions to form p + doping at the bottom of the gate trench; removing photoresist and SiO after the injection₂Medium, and RCA cleaning; depositing a graphite layer on the surface, and carrying out high-temperature activation annealing;

5) cleaning with RCA and BOE, and performing sacrificial oxidation; growing a layer of SiO by thermal oxidation₂Removing by BOE corrosion; growing a gate dielectric layer by thermal oxidation, oxidizing, and then growing NO or N₂O or POCl₃Annealing in atmosphere; depositing high-doped polysilicon by CVD method, or depositing undoped polycrystal, and then forming doped polysilicon by injection and annealing method; filling the gate trench with polysilicon, andflattening the surface; forming a photomask by using a photoetching method, and etching off the polycrystalline silicon outside the gate trench to form a polycrystalline silicon gate;

6) and depositing an isolation passivation layer, removing the medium in the source groove and the ohmic contact area by using a photoetching method, and reserving the medium on the gate polysilicon to form the isolation between the gate and the source. Depositing ohmic contact metal on the source ohmic contact area, depositing ohmic contact metal on the back surface, and performing rapid thermal annealing in vacuum or inert atmosphere to respectively form source and drain ohmic contacts;

7) depositing Schottky metal by a PVD method, removing metal in other areas outside the source groove and the ohmic contact area by a photoetching re-etching method, and performing thermal annealing to form Schottky contact in the middle area at the bottom of the source groove and form ohmic contact in the peripheral highly-doped p + area;

8) making thick electrode metal, electrically connecting a source electrode with the Schottky metal, and isolating the electrode pressing metal above the primitive cell from the grid electrode through an isolation passivation layer; making thick electrode metal on the back; and finally, a thick passivation layer is formed, and a window is opened to expose the metal welding area of the source and gate voltage blocks.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A SiC double-groove MOSFET device is characterized in that a cell structure of an active region of the device sequentially comprises a drain electrode, an n + substrate, an n-drift layer, a p base region, an n + layer, a grid electrode, an insulating layer and a source electrode from bottom to top; the cell structure is characterized in that two grooves are arranged in the cell structure, and the two grooves are of a symmetrical structure in an active region.

2. The SiC double trench MOSFET device of claim 1 in which the p + region under the trench is in electrical communication with the source and p-base regions.

3. The SiC double trench MOSFET device of claim 1 in which the p-doped region at the trench bottom of the trench is in electrical communication with the p-base region by doping the sidewalls of the trench.

4. The SiC double trench MOSFET device of claim 1 in which a current spreading region is disposed between the n-drift layer and the p-base region.