CN213212168U

CN213212168U - Groove type MOSFET device

Info

Publication number: CN213212168U
Application number: CN202022079187.2U
Authority: CN
Inventors: 倪炜江
Original assignee: 倪炜江
Current assignee: Anhui Xinta Electronic Technology Co.,Ltd.
Priority date: 2020-09-21
Filing date: 2020-09-21
Publication date: 2021-05-14
Anticipated expiration: 2030-09-21

Abstract

The utility model relates to the technical field of semiconductors, in particular to a trench type MOSFET device, which sequentially comprises a drain electrode, an n + substrate, an n + buffer layer, an n-drift layer, a CSL layer, a p + buried layer, a p well, a p + region, an n + region, a gate medium, a polysilicon gate, a gate source isolation medium and a source electrode from bottom to top; the active region of the device is composed of two types of primitive cells with different structures, wherein one type of primitive cell is a MOSFET conductive primitive cell A; the other type of the primitive cell is a primitive cell B for shielding an electric field of the trench gate structure, and a p + buried layer in the primitive cell B is electrically communicated with the source electrode through a p + region above the p + buried layer; in the direction parallel to the paper surface, the same type of primitive cells are connected in parallel left and right, and in the depth direction perpendicular to the paper surface, the two types of primitive cells are alternately arranged to form a conductive and shielding area. According to the method, the two types of primitive cells are arranged in order and by a certain method, so that the shielding of the trench gate can be realized and the very fine primitive cell size can be obtained. And the device structure and the preparation process are simple, and the popularization and the application are facilitated.

Description

Groove type MOSFET device

Technical Field

The utility model belongs to the technical field of the semiconductor technology and specifically relates to a trench type MOSFET device is related to.

Background

The forbidden band width of the SiC material is about 3 times that of silicon, and the critical breakdown field strength is about 10 times, so that the SiC material is very suitable for application in the fields of high-voltage and ultrahigh-voltage power. SiC trench MOSFETs are the focus of research and product development today. With respect to low channel mobility of a planar structure SiC MOSFET in the (0001) plane, i.e., the silicon plane, the channel of the trench MOSFET is in crystal planes perpendicular to the (0001) plane, such as in the (11-20) planes, and the channel mobility in these crystal planes is higher than in the (0001) plane. While the cell size of trench MOSFETs can be smaller than planar MOSFETs. Therefore, the trench MOSFET exhibits a lower specific on-resistance and a higher current density than the planar MOSFET, and is considered as a structure of a next-generation SiC MOSFET.

However, the trench MOSFET structure easily forms electric field concentration at the bottom of the gate trench, and as shown in fig. 1 (conventional trench MOSFET device structure), a gate electrode 1-1 is disposed in the trench: the p-base region 1-2 and the medium on the side wall form an MOS gate structure, and when the gate voltage is greater than the threshold voltage, the p-base region on the side wall is inverted to form a conductive channel. But this structure is prone to electric field concentration at the bottom of the gate trench, especially at point a. Due to SiO near the interface₂The medium electric field is about 3 times that of SiC, and the critical electric field of SiC is about 10 times that of silicon, so reliability problems are more likely to occur in SiC devices. On the other hand, because each cell on the mesa is provided with the p + region 1-3 and the n + region 1-4 which are parallel, and an isolation dielectric layer 1-5 for avoiding grid source short circuit is needed, the mesa size is limited and cannot be further reduced. How to avoid or mitigate the electric field concentration at the bottom of the gate trench is an important issue. In the prior art, ions are directly implanted at the bottom of a trench to form a p + region shielding structure, but the difficulty of electrically communicating a bottom p + region with a source electrode is brought. Secondly, through the double-groove structure, the p + region shielding structure is formed by injecting ions into the bottom of the source groove, but the problem of increasing the size of the original cell is brought.

The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information constitutes prior art already known to a person skilled in the art.

SUMMERY OF THE UTILITY MODEL

An object of the utility model is to provide a trench type MOSFET device, the device active area has the primitive cell of two kinds of different structures to constitute, and one of them type primitive cell is the electrically conductive primitive cell of MOSFET, and another type primitive cell is for carrying out electric field shielding's primitive cell to the ditch slot bars structure. Through the ordered arrangement of the two types of primitive cells and a certain method, the shielding of the trench gate can be realized, and meanwhile, the very fine primitive cell size can be obtained.

In order to achieve the above purpose, the utility model adopts the following technical scheme:

in a first aspect, the present invention provides a trench MOSFET device, which comprises, from bottom to top, a drain electrode, an n + substrate, an n + buffer layer, an n-drift layer, a CSL layer, a p + buried layer, a p well, a p + region, an n + region, a gate dielectric, a polysilicon gate, a gate source isolation dielectric, and a source electrode; the active region of the device consists of two types of primitive cells with different structures, wherein one type of primitive cell is a MOSFET conductive primitive cell A; the other type of the primitive cell is a primitive cell B for shielding an electric field of the trench gate structure, and a p + buried layer in the primitive cell B is electrically communicated with the source electrode through a p + region above the p + buried layer; in the direction parallel to the paper surface, the same type of primitive cells are connected in parallel left and right, and in the depth direction perpendicular to the paper surface, the two types of primitive cells are alternately arranged to form a conductive and shielding area.

As a further technical scheme, in the section parallel to the paper surface of the primitive cell A and the primitive cell B, only an n + region or a p + region is arranged on the table surface.

As a further technical scheme, the gate source isolation medium is arranged in the groove, and the gate source isolation medium is not arranged on the table top.

As a further technical solution, the p + buried layer has a larger dimension in a depth direction than the p + region thereon.

As a further technical solution, the doping concentration of the CSL layer is equal to or greater than the n-drift layer.

As a further technical solution, the trench depth of the trench MOSFET device is greater than the depth of the p-well, but less than the depth of the CSL layer.

In a second aspect, the present invention further provides a method for manufacturing a trench MOSFET device, including the following steps:

s1, sequentially extending an n + buffer layer, an n-drift layer and an n-type CSL layer on the conductive n + SiC substrate;

s2, etching a mark, etching a medium mask, and performing Al ion injection to form a p + buried layer orderly arranged in a direction parallel to the paper surface;

s3, carrying out secondary epitaxy, and continuing to epitaxially grow an n-epitaxial layer on the CSL layer; forming a p-well, an n + region and a p + region by an ion implantation method;

s4, etching the groove to form a U-shaped groove; successively carrying out high-temperature activation annealing and sacrificial oxidation to form a smooth structure at the bottom of the groove, and removing a damage layer caused by etching of the side wall;

s5, depositing polysilicon doped with nitrogen and phosphorus by CVD method to make the thickness of the bottom of the trench larger than the sidewall of the trench, performing thermal oxidation, and then depositing NO or N₂Annealing in an O atmosphere to form a gate dielectric;

s6, growing polysilicon with heavy doping and low resistivity in situ by an LPCVD method to fill the groove, and carrying out planarization etching until part of the polysilicon above the groove is etched; performing thermal oxidation on the polycrystalline silicon, performing thermal oxidation on the polycrystalline silicon on the surface, and enabling the upper surface of the finally remained polycrystalline silicon to be higher than the p well and the lower surface of the finally remained polycrystalline silicon to be lower than the p well so as to completely cover the p well; at this point, a polysilicon gate has been formed;

s7, depositing a grid source isolation medium, and forming ohmic contact of a source n + region and a p + region by using a silicide self-alignment method; depositing metal on the back, and performing RTA annealing at 900-1100 ℃ together to form back ohmic contact and improve source ohmic contact;

s8, finally, forming the grid, the pressing metal and the passivation medium of the source, the polyimide protective layer and the back pressing metal in sequence.

As a further technical solution, in S3, the p-well is in the whole active region, and the n + region and the p + region are alternately arranged in the depth direction perpendicular to the paper surface; and the depth of the p + region is greater than that of the p well and is communicated with the p + buried layer.

As a further technical solution, the deposition of the gate-source isolation dielectric in S7 requires over-etching to ensure that the dielectric on the mesa is etched clean and the isolation dielectric remains in the trench.

As a further technical solution, the method of forming ohmic contacts of the source n + region and the p + region by the silicide method in S7 is as follows: depositing metal Ni, and performing rapid RTA annealing at the annealing temperature of 500-800 ℃ in a vacuum or inert atmosphere; after annealing in concentrated H₂SO₄And H₂O₂The mixed solution is etched to remove the metal on the medium, and ohmic contact formed by reaction on the surface of the SiC is left.

Adopt above-mentioned technical scheme, the utility model discloses following beneficial effect has:

the utility model discloses an orderly and certain method's of two kinds of primitive cells range, finally can realize can obtaining very meticulous primitive cell size again simultaneously to the shielding of ditch groove bars. And the device structure and the preparation process are simple, and the popularization and the application are facilitated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the embodiments or the technical solutions in the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a schematic diagram of a prior art trench MOSFET device;

fig. 2 is a schematic diagram of a cross section a and a device depth structure of a trench SiC MOSFET device cell structure provided by an embodiment of the present invention;

fig. 3 is a schematic diagram of a cell structure B cross section and a device depth structure of a trench SiC MOSFET device provided by an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a trench SiC MOSFET device provided in an embodiment of the present invention after forming a p + buried layer;

fig. 5 is a schematic structural diagram of a trench SiC MOSFET device according to an embodiment of the present invention after ion implantation doping is completed;

fig. 6 is a schematic structural diagram of a trench SiC MOSFET device according to an embodiment of the present invention after trench etching is completed;

fig. 7 is a schematic structural diagram of a trench SiC MOSFET device according to an embodiment of the present invention after completing a polysilicon gate electrode;

fig. 8 is a schematic structural view of the trench SiC MOSFET device provided in the embodiment of the present invention after completing the source-drain ohmic contact;

icon: the transistor comprises a 1-1-gate electrode, a 1-2-p base region, a 1-3-p + region, a 1-4-n + region, a 1-5-isolation dielectric layer, a 1-drain electrode, a 2-n + substrate, a 3-n + buffer layer, a 4-n-drift layer, a 5-CSL layer, a 6-p + buried layer, a 7-p well, an 8-p + region, a 9-n + region, a 10-polysilicon gate, an 11-gate source isolation dielectric and a 12-trench.

Detailed Description

The technical solution of the present invention will be described clearly and completely with reference to the accompanying drawings, and obviously, the described embodiments are some, but not all embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by a person skilled in the art without creative work belong to the protection scope of the present invention.

In the description of the present invention, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplification of description, but do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present invention can be understood according to specific situations by those skilled in the art.

The following detailed description of the embodiments of the present invention will be made with reference to the accompanying drawings. It is to be understood that the description of the embodiments herein is for purposes of illustration and explanation only and is not intended to limit the invention.

Example one

The method of the present invention is applicable to field effect transistors of various SiC and other semiconductors, such as MOSFET, IGBT, etc., and the following description will be given taking SiC MOSFET as an example.

As shown in fig. 2 and fig. 3, the present embodiment provides a trench MOSFET device, which sequentially includes, from bottom to top, a drain 1, an n + substrate 2, an n + buffer layer 3, an n-drift layer 4, a CSL layer 5, a p + buried layer 6, a p well 7, a p + region 8, an n + region 9, a gate dielectric, a polysilicon gate 10, a gate-source isolation dielectric 11, and a source electrode; the active region of the device is composed of two types of primitive cells with different structures, wherein one type of primitive cell is a MOSFET conductive primitive cell A (the cross section of the primitive cell is shown in figure 2); the other type of the cell is a cell B (the section of the cell is shown in figure 3) for shielding an electric field of the trench gate structure, and a p + buried layer in the cell B is electrically communicated with a source electrode through a p + region above the p + buried layer; in the direction parallel to the paper surface, the same type of primitive cells are connected in parallel left and right, and in the depth direction perpendicular to the paper surface, the two types of primitive cells are alternately arranged to form a conductive and shielding area.

According to the method, the two types of primitive cells are arranged in order and in the depth direction (vertical direction and paper surface) alternately, the primitive cell B can effectively shield the groove grating in the primitive cell A, and the reliability of the device is improved. The gate width of the device is reduced, the saturation current is reduced, and the short-circuit current capacity is improved.

In this embodiment, as a further technical solution, in a cross section of the cell a and the cell B parallel to the paper surface, only an n + region or a p + region is on the mesa. The lateral dimensions of the primitive cells A, B can be very small and the primitive cell density can be very high.

In this embodiment, as a further technical solution, the gate-source isolation medium 11 is in the trench, the thickness of the n + region 9 is greater than that of the gate-source isolation medium 11, the gate-source isolation medium 11 is not on the mesa, the mesa size can be very small, and the cell size is further reduced.

In this embodiment, as a further technical solution, the p + buried layer 6 (first p + region) has a larger depth dimension than the p + region 8 (second p + region) above it, so that the JFET size between the p + buried layers is reduced and the trench gate is better shielded. In addition, the p + buried layer (first p + region) and the p + layer (second p + region) above it may be formed simultaneously by high-energy ion implantation with the same depth direction dimension.

In this embodiment, as a further technical solution, the doping concentration of the CSL layer 5 is greater than or equal to that of the n-drift layer 4, which not only reduces the resistance of the JFET, but also makes it easier for the current to expand around after passing through the JFET region, thereby reducing the on-resistance.

In this embodiment, as a further technical solution, the trench depth of the trench MOSFET device is greater than the depth of the p-well 7, but less than the depth of the CSL layer 5. Meanwhile, the thickness of the polysilicon gate 10 is larger than that of the p-well 7, and the polysilicon gate covers the whole p-well 7, so that a gate-controlled conductive channel is formed.

In the present application, ohmic contacts are formed on the mesas and on portions of the trench sidewalls by a self-aligned method, and thus there is no influence or limitation of alignment deviation. The p + region and the n + region are electrically connected to the source electrode through ohmic contacts with extremely low resistance.

The active region is formed by arranging and combining cells A, B, the same type of cells are connected in parallel from left to right in the direction parallel to the paper surface, and the two types of cells are alternately arranged in the depth direction vertical to the paper surface to form a conductive and shielding region. And the active region is also provided with a grid pressing block metal and a source pressing block metal which are used for electrically connecting the device with an external circuit. There is also a passivation dielectric and a polyimide protective layer that protects the end portions of the device, exposing the middle portion of the metal of the compact. The entire device consists of the active region and the termination portion including the scribe line. The drain on the back side consists of a back ohmic contact and a compact metal.

Example two

The n-type doping and the p-type doping mentioned in the embodiments of the present invention are relative, and may also be referred to as the first doping and the second doping, i.e., the interchanging of the n-type and the p-type is also applicable to the device. Meanwhile, the device structure in the embodiment of the present invention is not only suitable for SiC, but also suitable for other semiconductor materials such as Si, GaN, Ga2O 3. In the embodiment of the present invention, SiC is taken as an example.

The second embodiment provides a preparation method of a trench type MOSFET device, which comprises the following specific steps:

as shown in fig. 4, an n + buffer layer 3, an n-drift layer 4, and an n-type CSL layer 5 (current spreading layer) are sequentially epitaxially grown on a conductive n + substrate 2. The concentration and thickness of the n-drift layer 4 are determined by the voltage-resistant design of the device, and the concentration is generally greater than 5E14cm-³And the thickness is more than 5 um. The thickness of the CSL layer is greater than 0.5um, the concentration is greater than that of the drift layer, and is generally less than 2E17cm-³. And etching the mark, etching the medium mask, and performing Al ion implantation to form the p + buried layer 6 which is orderly arranged in a direction parallel to the paper surface. Two p + regions adjacent in the depth direction can effectively shield the electric field of the middle n region. The interval W between the p + regions in the depth direction and the doping concentration of the CSL layer determine the resistance and the breakdown voltage of the conducting region of the JFET and the strength of electric field shielding of the trench gate. Therefore, when the maximum electric field of the trench gate is controlled to be less than a certain value, for example, 4MV/cm, the width range of W is determined by simulation. In general, W may take values greater than 0.5 microns.

As shown in fig. 5, a second epitaxy is then performed, continuing to epitaxially grow an n-epitaxial layer on the CSL layer 5. Forming a p well 7, an n + region 9 and a p + region 8 by an ion implantation method; wherein the p-well 7 is in the whole active area, and the n + region and the second p + region are alternately arranged in the depth direction perpendicular to the paper surface. The p + region has a depth greater than the p-well and is thus directly connected to the first p + region. The ions implanted in the n + region can be N, P ions, and the ions implanted in the p + region can be Al and B ions. The thickness of the p-well layer is larger than 0.2um, and the concentration is generally 5E15-5E17cm-³Depending on the designed gate threshold voltage. In this embodiment, the size of the second p + region is smaller than a certain value of the first p + region becauseThis second p + region is still above the first p + region even if there is some misalignment. There is still a partial conduction channel in the cell B, and the channel current finally flows through the JFET region between the first p + regions.

As shown in fig. 6, trench etching is performed to form U-shaped trenches 12. The depth of the trench 12 is greater than the depth of the p-well 7 and less than the depth of the CSL layer 5, ensuring the formation of a channel. High temperature activation annealing and sacrificial oxidation are sequentially carried out. The high-temperature activation annealing and the sacrificial oxidation can not only enable the bottom of the groove to form a smoother structure, but also remove a damaged layer caused by etching of the side wall. Since the subsequent source ohmic contact is formed by the self-aligned process, the width of the trench may be less than 0.5 micron and the width of the mesa may also be less than 0.5 micron. The widths of the trenches and mesas, taken together, may be less than 1 micron, so that a fine cell structure of submicron order may be achieved.

As shown in FIG. 7, a CVD process deposits polysilicon doped with nitrogen and phosphorus to a thickness greater at the bottom of the trench than at the sidewalls of the trench, thermal oxidation is performed, and then NO or N is added₂And annealing in O atmosphere to form the gate dielectric. Nitrogen and phosphorus in polysilicon, and NO or N in annealing₂O can effectively passivate the MOS interface state and improve the channel mobility. Finally, the gate dielectric with the bottom of the trench thicker than the side wall is generated. Growing polysilicon with in-situ heavy doping and low resistivity by an LPCVD method to fill the groove, and carrying out planarization etching. So that the polysilicon on the mesa is etched clean, and the polysilicon in the trench is higher than the p-base region. And thermally oxidizing the polysilicon in a short time, thermally oxidizing the polysilicon on the surface, and enabling the upper surface of the finally remained polysilicon to be higher than the p well and the lower surface of the finally remained polysilicon to be lower than the p well so as to completely cover the p well. At this time, the polysilicon gate 10 has been formed.

As shown in fig. 8, a gate source isolation dielectric 11 is deposited and a mesa etch is performed with anisotropy, requiring a slight over etch to ensure the dielectric on the mesa is etched clean and the isolation dielectric remains in the trench. Ohmic contacts to the source n + and p + regions are then formed using a silicide self-aligned process. The method comprises the following steps: depositing metal Ni, and performing rapid RTA annealing at the annealing temperature of 500-800 ℃ in vacuum or inert atmosphere. Concentrated H at a certain ratio and temperature after annealing₂SO₄And H₂O₂The mixed solution of (2) is etched. Ni and SiO react to generate NixSiy compound which cannot be corroded₂Non-reactive and easily corroded, thus leaving only Ni ohmic contacts on the mesa and at portions of the sidewalls. And depositing metal on the back, and performing RTA annealing at 900-1100 ℃ together to form back ohmic contact and improve source ohmic contact.

The gate, source, bulk metal and passivation dielectric, polyimide protective layer, and backside bulk metal are then formed sequentially. The source electrode pressing metal can be Ti/Al, or Ti/W/Al, Ti/TiN/Al, Ti/Cu, Ti/Pt/Auu, Ti/Ag and the like, and the back drain electrode pressing metal can be TiNiAg, TiNiAu, CrNiAg and the like.

The device comprises an active region, a junction terminal and a scribing groove, wherein the active region is formed by connecting a plurality of cells in parallel, a source electrode and a grid electrode of each cell are respectively and electrically connected with corresponding electrode pressing block metal, and the grid electrode and the source electrode are electrically isolated through an isolation dielectric layer.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; although the present invention has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; such modifications and substitutions do not depart from the spirit and scope of the present invention.

Claims

1. A trench type MOSFET device sequentially comprises a drain electrode, an n + substrate, an n + buffer layer, an n-drift layer, a CSL layer, a p + buried layer, a p well, a p + region, an n + region, a gate dielectric, a polysilicon gate, a gate source isolation dielectric and a source electrode from bottom to top; the device is characterized in that an active region of the device consists of two types of primitive cells with different structures, wherein one type of primitive cell is a MOSFET conductive primitive cell A; the other type of the primitive cell is a primitive cell B for shielding an electric field of the trench gate structure, and a p + buried layer in the primitive cell B is electrically communicated with the source electrode through a p + region above the p + buried layer; in the direction parallel to the paper surface, the same type of primitive cells are connected in parallel left and right, and in the depth direction perpendicular to the paper surface, the two types of primitive cells are alternately arranged to form a conductive and shielding area.

2. The trench MOSFET device of claim 1, wherein only n + or p + regions are on the mesa in a cross section of the cell a and the cell B parallel to the paper.

3. The trench MOSFET device of claim 1 wherein the gate-source isolation dielectric is within the trench and the mesa is free of the gate-source isolation dielectric.

4. The trench MOSFET device of claim 1, wherein the p + buried layer has a greater depth dimension than the p + region above it.

5. The trench MOSFET device of claim 1 wherein the CSL layer has a doping concentration equal to or greater than the n-drift layer.

6. The trench MOSFET device of claim 1, wherein the trench depth of the trench MOSFET device is greater than the depth of the p-well but less than the depth of the CSL layer.