WO2024099436A1 - Trench-type sic mosfet device structure and manufacturing method therefor - Google Patents

Trench-type sic mosfet device structure and manufacturing method therefor Download PDF

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Publication number
WO2024099436A1
WO2024099436A1 PCT/CN2023/131026 CN2023131026W WO2024099436A1 WO 2024099436 A1 WO2024099436 A1 WO 2024099436A1 CN 2023131026 W CN2023131026 W CN 2023131026W WO 2024099436 A1 WO2024099436 A1 WO 2024099436A1
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Prior art keywords
dielectric layer
gate trench
gate
trench
layer
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PCT/CN2023/131026
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French (fr)
Chinese (zh)
Inventor
柯行飞
高云斌
李道会
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蔚来动力科技(合肥)有限公司
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Publication of WO2024099436A1 publication Critical patent/WO2024099436A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present application relates to the semiconductor field, and specifically to a trench SiC MOSFET device structure and a manufacturing method thereof.
  • SiC MOSFET devices have the advantages of fast switching speed, high voltage resistance and low power consumption. They are mainly divided into planar type and trench type. Trench power SiC MOSFET devices have lower on-resistance and greater current density, which can achieve lower on-resistance. They have the advantages of high integration, low on-resistance, fast switching speed and low switching loss. They have become the mainstream of related applications in low-voltage and high-voltage fields.
  • trench power SiC MOSFET devices With the wide expansion of application fields and the continuous improvement of equipment performance, the reliability requirements for trench power SiC MOSFET devices are also getting higher and higher.
  • trench power SiC MOSFET devices have the problem of large bottom electric field and easy breakdown or injection of interface states, which limits their application in high-reliability scenarios.
  • the present application provides a method for manufacturing a trench SiC MOSFET device and a trench SiC MOSFET device structure to solve the problem that the existing trench power SiC MOSFET device has a large electric field at the bottom of the gate trench and the gate oxide is easily damaged and broken down, which limits its application in high-reliability scenarios.
  • the present application provides a method for manufacturing a trench SiC MOSFET device, the method comprising:
  • first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first sidewall, the second sidewall and the bottom of the gate trench, and the second dielectric layer fills a hollow area between the first sidewall and the second sidewall of the gate trench;
  • a filler is filled between the gate oxide layer and the second dielectric layer to form a gate.
  • the method further comprises: performing P+ implantation on the body region to form a P+ region;
  • the method further includes: forming Ni salicide on the surfaces of corresponding positions of the source and the P+ region to obtain a source ohmic contact layer.
  • the method further comprises:
  • the contact hole is filled with metal to form a source electrode.
  • the depositing forms a first dielectric layer and a second dielectric layer, comprising:
  • the silicon nitride and silicon oxide in the area outside the gate trench are removed, and the silicon nitride and silicon oxide in the gate trench are retained, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
  • removing the silicon nitride and silicon oxide in the area outside the gate trench includes:
  • the silicon oxide protruding from the SiC epitaxial layer is removed by CMP.
  • removing a portion of the first dielectric layer covering the first sidewall and retaining at least the first dielectric layer covering the bottom of the gate trench comprises:
  • a wet etch-back process is adopted to remove a portion of the first dielectric layer covering the first sidewall, and at least the first dielectric layer covering the bottom of the gate trench is retained.
  • removing a portion of the first dielectric layer covering the first sidewall and retaining at least the first dielectric layer covering the bottom of the gate trench comprises:
  • the first dielectric layer covering the first sidewall and having the same depth as the second dielectric layer is removed.
  • filling a filler between the gate oxide layer and the second dielectric layer to form a gate includes:
  • Polysilicon is deposited to form a polysilicon gate in the region between the gate oxide layer and the second dielectric layer, and the polysilicon on the surface of the SiC epitaxial layer is removed.
  • a trench SiC MOSFET device structure comprising:
  • a gate trench located in the body region, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and a first sidewall of the gate trench passes through the source or contacts the source;
  • a first dielectric layer covering the bottom and second sidewall surface of the gate trench
  • a gate is filled in the gate trench and located between the gate oxide layer and the second dielectric layer.
  • the trench SiC MOSFET device structure further includes:
  • a source ohmic contact layer formed on the surface of the source and the P+ region at corresponding positions;
  • a contact hole is formed on the surface of the source ohmic contact layer and a source metal is filled in the contact hole.
  • the method for manufacturing a trench SiC MOSFET device includes: growing a SiC epitaxial layer on a SiC substrate; forming a body region in the SiC epitaxial layer; performing source injection into the body region to form a source electrode; forming a gate trench in the body region by etching, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and the first side wall of the gate trench passes through the source electrode or contacts the source electrode; depositing a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer fills the hollow area between the first side wall and the second side wall of the gate trench; removing a portion of the first dielectric layer covering the first side wall, and retaining at least the first dielectric layer covering the bottom of the gate trench to form a vacant area; growing a gate oxide layer on the surface of the first side wall exposed in the vacant area; and
  • the first dielectric layer and the second dielectric layer are deposited in the gate trench, and a portion of the first dielectric layer covering the first sidewall is removed, and at least a portion of the first dielectric layer covering the bottom of the gate trench is retained to form a vacant area.
  • a gate oxide layer is grown on the surface of the first sidewall exposed in the vacant area, and a filler is filled between the gate oxide layer and the second dielectric layer to form a gate.
  • the remaining first dielectric layer and second dielectric layer in the gate trench can form a thick oxide layer for protecting the gate oxide layer, reduce the electric field at the bottom of the gate trench, optimize the electric field distribution at the bottom of the gate trench in the reverse cutoff state, and improve the reliability of the device.
  • the thick oxide layer at the bottom and sidewall of the gate trench can greatly reduce the gate charge and optimize the switching characteristics of the device.
  • the above-mentioned gate trench filling method does not need to accurately control the depth of the body region, and does not need to strictly control the position of the gate in the gate trench, which can make the manufacturing process of the trench SiC MOSFET device simple, and has low requirements on equipment and machine, and has high manufacturability.
  • FIG1 is a schematic diagram of a process for manufacturing a trench SiC MOSFET device provided in an embodiment of the present application
  • FIG2 is a schematic diagram of a trench SiC MOSFET device structure provided in an embodiment of the present application.
  • FIGS 3 to 17 are schematic diagrams of the trench SiC MOSFET device manufacturing process provided in this embodiment.
  • SiC silicon carbide
  • SiC silicon carbide
  • Power MOSFET devices based on SiC have the advantages of high current density, high breakdown voltage, low loss, good high-temperature characteristics and radiation resistance. Compared with traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems. Reduce system volume and power loss.
  • Power SiC MOSFET device structures include flat gate type and trench type.
  • Flat gate power SiC MOSFET devices have a parasitic junction field effect transistor (JFET) structure, which increases the device on-resistance and device power consumption.
  • Trench power SiC MOSFET devices use a trench gate structure and do not have a JFET region, so the device on-resistance can be significantly reduced, and the conductive channel is changed from horizontal to vertical, which effectively saves device area and greatly improves power density.
  • trench power SiC MOSFET devices have lower on-resistance and greater current density, they have the advantages of high integration, low on-resistance, fast switching speed, and low switching loss. They have become the mainstream of related applications in low-voltage and high-voltage fields. With the widespread expansion of application fields and the continuous improvement of equipment performance, the reliability requirements for trench power SiC MOSFET devices are also becoming higher and higher.
  • the trench power SiC MOSFET device due to the influence of the electric field concentration effect at the bottom corner of the trench gate, the trench power SiC MOSFET device has a large bottom electric field and is easily broken down or injected into the interface state, which limits its application in high-reliability scenarios.
  • the trench power SiC MOSFET device has a lower on-resistance and a larger current density, but due to the excessive electric field at the bottom of the gate trench, the gate oxide layer is easily damaged and broken down, which limits its application in high-reliability scenarios.
  • the existing trench SiC MOSFET device protects the gate oxide layer at the bottom of the gate trench by depleting the deep body region in advance, that is, the body region is located below the gate trench in the vertical direction, and when the device is subjected to reverse withstand voltage, the depletion layer widens until the depletion layers on both sides of the trench are closed to each other to protect the gate oxide layer at the bottom of the gate trench.
  • the process requires precise control of the depth of the body region, which makes the process complex. For example, if the depth of the body region is too shallow, the protection of the gate oxide layer will be weakened, and the surge capability of the device will be weakened. If the depth of the body region is too deep, the device will have a reduced withstand voltage.
  • an embodiment of the present application provides a method for manufacturing a trench SiC MOSFET device and a trench SiC MOSFET device structure. Please refer to Figures 1, 2 and 3-17 to understand this embodiment.
  • Figure 1 is a flow chart of the method for manufacturing a trench SiC MOSFET device provided in this embodiment
  • Figure 2 is a schematic diagram of the trench SiC MOSFET device structure provided in this embodiment
  • Figures 3-17 are schematic diagrams of the trench SiC MOSFET device manufacturing process provided in this embodiment.
  • the method for manufacturing a trench SiC MOSFET device includes the following steps:
  • S1 forming a SiC epitaxial layer 2 on a SiC substrate 1 ; specifically, a lightly doped SiC epitaxial layer 2 may be grown on the upper surface of a heavily doped SiC substrate 1 .
  • S2 forming a body region 3 in the SiC epitaxial layer 2 (as shown in FIG. 3 ); for example, Al ion implantation is performed on the SiC epitaxial layer 2 , the implantation energy may be 500-800 Kev, and the implantation dose may be E13 atoms per square centimeter.
  • S3 performing source implantation on the body region 3 to form a source 4 (as shown in FIG. 4 ).
  • the implantation energy may be 50-70 KeV
  • the implantation dose may be E15 atoms per square centimeter.
  • a gate trench 5 is formed in the body region 3 by etching, the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2 (as shown in FIG6 ), the inner wall of the gate trench 5 includes a first side wall 19, a second side wall 20 and a trench bottom, the first side wall 19 of the gate trench 5 passes through the source 4 or contacts the source 4 to form a channel; in the present embodiment, plasma dry etching can be used when etching to form the gate trench 5, and the width of the gate trench 5 is 2 um and the depth is 1.5 um.
  • S5 Deposit to form a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first side wall 19, the second side wall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 fills the hollow area between the first side wall 19 and the second side wall 20 of the gate trench 5 (as shown in Figures 7 to 11).
  • S7 growing a gate oxide layer 9 on the surface of the first side wall 19 exposed in the vacant area (as shown in FIG. 13 ); the thickness of the gate oxide layer 9 may be 400-800 ⁇ , and the gate oxide layer 9 may be grown isotropically by chemical vapor deposition.
  • S8 Filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8 (as shown in FIG. 14 ).
  • the first dielectric layer 6 and the second dielectric layer 7 are deposited in the gate trench 5, and after removing part of the first dielectric layer 6 covering the first sidewall 19 and retaining at least part of the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, a gate oxide layer 9 is grown on the surface of the first sidewall 19 exposed in the vacant area, and a filler is filled between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; through this gate trench 5 filling method, the remaining first dielectric layer 6 and the second dielectric layer 7 can form a thick oxide layer for protecting the gate oxide layer 9, reduce the electric field at the bottom of the gate trench 5, optimize the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improve the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 can greatly reduce the gate charge and optimize the switching characteristics of the device.
  • the above-mentioned gate trench 5 filling method does not need to accurately control the depth of the body region 3, and does not need to strictly control the position of the gate 8 in the gate trench 5, which can make the manufacturing process simple, and has low requirements on equipment and machine, and has high manufacturability.
  • the method further includes: injecting P+ into the body region 3 to form a P+ region 10 (as shown in FIG. 5 ); and after filling polysilicon between the gate oxide layer 9 and the second dielectric layer 7, the method further includes: forming Ni salicide 11 on the surface of the corresponding position of the source 4 and the P+ region 10 to obtain a source ohmic contact layer.
  • the process can be specifically: depositing a 400A thick silicon oxide as a temporary protective layer 18, forming an opening at the corresponding position of the source 4 and the P+ region 10, and forming a gate trench 5 in the body region 3.
  • the source 4 and the P+ region 10 are provided at the same time as the source 4.
  • a 1000A thick metal nickel (Ni) is deposited, and an annealing process is performed at 400-500°C to remove excess Ni on the surface of the silicon oxide (temporary protective layer 18).
  • An annealing process is then performed at 600-700°C to form Ni salicide 11 on the surface of the SiC epitaxial layer 2 at the corresponding positions of the source 4 and the P+ region 10 (as shown in FIG. 16).
  • the method further includes: forming a contact hole 12 on the surface of the source ohmic contact layer, specifically, a dielectric layer 14 can be formed after an ILD deposition process, and a contact hole 12 is formed by a photolithography process; filling the contact hole 12 with metal to form a source electrode 13, for example, filling the contact hole 12 with metal tungsten by a W plug process.
  • the surface metal 15 and the back metal 16 are assembled to finally form a trench SiC MOSFET device as shown in FIG. 2 .
  • the first dielectric layer 6 may be silicon oxide
  • the second dielectric layer 7 may be silicon nitride.
  • the deposition to form the first dielectric layer 6 and the second dielectric layer 7 specifically includes the following contents:
  • silicon oxide is deposited (as shown in FIG. 7 ) with a thickness of 7000 ⁇ , so that the silicon oxide covers the surface of the SiC epitaxial layer 2 and covers the sidewalls (the first sidewall 19 and the second sidewall 20 ) and the bottom of the gate trench 5;
  • silicon nitride is deposited on the upper surface of the silicon oxide, and the thickness can be 6000 ⁇ , so that the silicon nitride covers the surface of the silicon oxide and fills the remaining area of the gate trench 5 (as shown in FIG. 8 );
  • the silicon nitride and silicon oxide in the area outside the gate trench 5 are removed, and the silicon nitride and silicon oxide in the gate trench 5 are retained, so that the height of the silicon oxide and silicon nitride in the gate trench 5 is consistent with the height of the SiC epitaxial layer 2 (as shown in Figures 9 and 11), wherein the silicon oxide in the gate trench 5 forms a first dielectric layer 6, and the silicon nitride in the gate trench 5 forms a second dielectric layer 7.
  • the silicon nitride and silicon oxide in the area outside the gate trench 5 can be removed in the following manner: first, the silicon nitride on the top surface is removed by CMP or dry etching to expose the silicon oxide (as shown in FIG. 9 ), and the silicon nitride in the gate trench 5 that is higher than the SiC epitaxial layer 2 is removed (as shown in FIG. 10 ); secondly, the silicon oxide that is higher than the SiC epitaxial layer 2 is removed by CMP process (as shown in FIG. 11 ).
  • CMP Chemical Mechanical Polishing
  • CMP Chemical Mechanical Polishing
  • step S6 a portion of the first dielectric layer 6 covering the first sidewall 19 is removed, and at least a portion of the first dielectric layer 6 covering the bottom of the gate trench 5 is retained, which indicates that in the depth direction of the gate trench 5, the first dielectric layer 6 removed is only a portion of the first dielectric layer 6 covering the first sidewall 19, and the first dielectric layer 6 retained at the bottom of the gate trench 5 can be a portion or all of the first dielectric layer 6 covering the bottom of the gate trench 5, so that when the gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5, a portion or all of the first dielectric layer 6 at the bottom of the gate trench 5 can be retained.
  • the first dielectric layer 6 covering the first sidewall 19 and having the same depth as the second dielectric layer 7 can be removed, that is, the first dielectric layer 6 between the first sidewall 19 and the second dielectric layer 7 is removed so that the region forms a vacant region, and the entire first dielectric layer 6 at the bottom of the gate trench 5 is retained.
  • the above-mentioned process of removing part of the first dielectric layer 6 can be specifically realized in the following manner: a photoresist 17 is coated on the surface of the SiC epitaxial layer 2, and the photoresist 17 is patterned by a photolithography process to form a patterned photoresist 17; based on the patterned photoresist 17, a wet etching back process is used to remove part of the first dielectric layer 6 covering the first sidewall 19, and at least the first dielectric layer 6 covering the bottom of the gate trench 5 is retained (as shown in FIG. 12).
  • silicon nitride the second dielectric layer 7 can prevent the first dielectric layer 6 covering the second sidewall 20 from being removed when the first dielectric layer 6 covering the first sidewall 19 is partially removed.
  • the step S8 of filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8 may specifically refer to: depositing phosphorus-doped polysilicon, the implantation dose may be 1E20 atoms per square centimeter, so that a polysilicon gate is formed in the area between the gate oxide layer 9 and the second dielectric layer 7, and the polysilicon on the surface of the SiC epitaxial layer 2 is removed.
  • the remaining first dielectric layer 6 and second dielectric layer 7 in the gate trench 5 can form a thick oxide layer for protecting the gate oxide layer 9, thereby reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 (the remaining first dielectric layer 6 and second dielectric layer 7) can significantly reduce the gate charge and optimize the switching characteristics of the device.
  • the present embodiment provides a method for manufacturing a trench SiC MOSFET device, which includes growing a SiC epitaxial layer 2 on a SiC substrate 1; forming a body region 3 in the SiC epitaxial layer 2; performing source implantation on the body region 3 to form a source 4; forming a gate trench 5 in the body region 3 by etching, wherein the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2, and the first sidewall 19 of the gate trench 5 passes through the source 4 or contacts the source 4; depositing a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first sidewall 19, the second sidewall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 fills the hollow area between the first sidewall 19 and the second sidewall 20 of the gate trench 5; removing a portion of the first dielectric layer 6 covering the first sidewall 19, and retaining at least the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area; growing
  • the method deposits a first dielectric layer 6 and a second dielectric layer 7 in the gate trench 5, removes a portion of the first dielectric layer 6 covering the first sidewall 19, and at least retains the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, then grows a gate oxide layer 9 on the surface of the first sidewall 19 exposed in the vacant area, and fills a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; through this gate trench 5 filling method, the remaining first dielectric layer 6 and the second dielectric layer 7 in the gate trench can form a thick oxide layer for protecting the gate oxide layer 9, thereby reducing the gate trench 5.
  • the bottom electric field optimizes the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, thereby improving the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 (the first dielectric layer 6 and the second dielectric layer 7 remaining in the gate trench) can significantly reduce the gate charge and optimize the switching characteristics of the device. Furthermore, the above-mentioned gate trench 5 filling method does not require precise control of the depth of the body region 3, and does not require strict control of the position of the gate 8 in the gate trench 5, which can simplify the manufacturing process, and has low requirements on equipment and machines, and has high manufacturability.
  • trench SiC MOSFET device structure which is manufactured by the trench SiC MOSFET device manufacturing method provided in the above embodiment.
  • the trench SiC MOSFET device structure includes:
  • a gate trench 5 located in the body region 3, wherein the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2, and a first sidewall 19 of the gate trench 5 passes through the source 4 or contacts the source 4;
  • a first dielectric layer 6 covering the bottom of the gate trench 5 and the surface of the second sidewall 20;
  • a gate 8 is filled in the gate trench 5 and located between the gate oxide layer 9 and the second dielectric layer 7 .
  • the above-mentioned trench SiC MOSFET device structure also includes: a P+ region 10 formed after P+ injection into the body region 3; a source ohmic contact layer formed on the surface of the corresponding position of the source 4 and the P+ region 10; a contact hole 12 formed on the surface of the source ohmic contact layer and a source electrode 13 filled in the contact hole 12.
  • the gate oxide layer 9 is grown on the first side wall 19 of the gate trench 5; the first dielectric layer 6 covers the bottom of the gate trench 5 and the surface of the second side wall 20; the second dielectric layer 7 is filled in the gate trench 5 and is in contact with the first dielectric layer 6; the gate 8 is filled in the gate trench 5 and is located between the gate oxide layer 9 and the second dielectric layer 7.
  • This gate trench filling method allows the first dielectric layer 6 and the second dielectric layer 7 in the gate trench to form a thick oxide layer for protecting the gate oxide layer 9, reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device; and the thick oxide layer (the first dielectric layer 6 and the second dielectric layer 7) at the bottom and sidewalls of the gate trench 5 can significantly reduce the gate charge and optimize the switching characteristics of the device.

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Abstract

Disclosed in the present application are a trench-type SiC MOSFET device structure and a manufacturing method therefor. The method comprises: growing a SiC epitaxial layer on a SiC substrate; forming a body region in the SiC epitaxial layer; performing source injection on the body region to form a source electrode; forming a gate trench in the body region by means of performing etching; forming a first dielectric layer and a second dielectric layer by means of performing deposition, wherein the first dielectric layer covers a first side wall, a second side wall and the bottom of the gate trench, and the second dielectric layer is filled in a hollow region between the first side wall and the second side wall of the gate trench; removing part of the first dielectric layer that covers the first side wall, and at least reserving the first dielectric layer that covers the bottom of the gate trench, so as to form a vacant area; growing a gate oxide layer on the surface of the first side wall that is exposed from the vacant area; and filling a filler between the gate oxide layer and the second dielectric layer, so as to form a gate electrode. By means of the gate trench filling method, the electric field at the bottom of a gate trench can be reduced, and the electric field distribution at the bottom of the gate trench in a reverse cut-off state is optimized, thereby improving the reliability of a device.

Description

一种沟槽型SiC MOSFET器件结构及其制造方法A trench SiC MOSFET device structure and manufacturing method thereof 技术领域Technical Field
本申请涉及半导体领域，具体涉及一种沟槽型SiC MOSFET器件结构及其制造方法。The present application relates to the semiconductor field, and specifically to a trench SiC MOSFET device structure and a manufacturing method thereof.
背景技术Background technique
现代电力电子装置正朝着高功率密度和高效率的方向发展。碳化硅功率器件因其卓越的高压、高频、高温和高功率密度等器件特性，近年来在高效电能转换领域得到了迅速发展。SiC MOSFET器件具有开关速度快、耐高压和功耗低等优点，其主要分为平面型和沟槽型，沟槽型功率SiC MOSFET器件有着更低的导通电阻和更大的电流密度，可以实现更低的导通电阻，具有集成度高、导通电阻低、开关速度快、开关损耗小等优点，在低压和高压领域成为相关应用的主流，随着应用领域的广泛扩展及设备性能的不断提升，对沟槽型功率SiC MOSFET器件的可靠性要求也越来越高。然而沟槽型功率SiC MOSFET器件存在底部电场较大、容易被击穿或注入界面态的问题，限制了其在高可靠性场景的应用。Modern power electronic devices are developing in the direction of high power density and high efficiency. Silicon carbide power devices have developed rapidly in the field of efficient power conversion in recent years due to their excellent device characteristics such as high voltage, high frequency, high temperature and high power density. SiC MOSFET devices have the advantages of fast switching speed, high voltage resistance and low power consumption. They are mainly divided into planar type and trench type. Trench power SiC MOSFET devices have lower on-resistance and greater current density, which can achieve lower on-resistance. They have the advantages of high integration, low on-resistance, fast switching speed and low switching loss. They have become the mainstream of related applications in low-voltage and high-voltage fields. With the wide expansion of application fields and the continuous improvement of equipment performance, the reliability requirements for trench power SiC MOSFET devices are also getting higher and higher. However, trench power SiC MOSFET devices have the problem of large bottom electric field and easy breakdown or injection of interface states, which limits their application in high-reliability scenarios.
发明内容Summary of the invention
本申请提供一种沟槽型SiC MOSFET器件制作方法以及一种沟槽型SiC MOSFET器件结构，以解决现有的因沟槽型功率SiC MOSFET器件存在栅沟槽底部电场较大、栅氧易损伤和击穿，限制了其在高可靠性场景的应用的问题。The present application provides a method for manufacturing a trench SiC MOSFET device and a trench SiC MOSFET device structure to solve the problem that the existing trench power SiC MOSFET device has a large electric field at the bottom of the gate trench and the gate oxide is easily damaged and broken down, which limits its application in high-reliability scenarios.
本申请实施例提供一种沟槽型SiC MOSFET器件制作方法，所述方法包括：The present application provides a method for manufacturing a trench SiC MOSFET device, the method comprising:
在SiC衬底上形成SiC外延层；forming a SiC epitaxial layer on a SiC substrate;
在所述SiC外延层形成体区；forming a body region in the SiC epitaxial layer;
对所述体区进行源注入，形成源极；Performing source implantation into the body region to form a source electrode;
在所述体区内通过刻蚀形成栅沟槽，所述栅沟槽的底部位于所述SiC外延层的漂移区，所述栅沟槽的第一侧壁穿过所述源极或与所述源极接触；Forming a gate trench in the body region by etching, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and a first sidewall of the gate trench passes through the source or contacts the source;
沉积形成第一介电层和第二介电层，所述第一介电层覆盖于所述栅沟槽的所述第一侧壁、第二侧壁以及底部，所述第二介电层填充于所述栅沟槽的第一侧壁和第二侧壁之间的中空区域； Depositing a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first sidewall, the second sidewall and the bottom of the gate trench, and the second dielectric layer fills a hollow area between the first sidewall and the second sidewall of the gate trench;
去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的部分第一介电层，形成空置区域；Removing a portion of the first dielectric layer covering the first sidewall, and retaining at least a portion of the first dielectric layer covering the bottom of the gate trench to form a vacant area;
在露出于所述空置区域的第一侧壁表面生长栅氧化层；Growing a gate oxide layer on the first sidewall surface exposed in the vacant area;
于所述栅氧化层和所述第二介电层之间填充填充物，形成栅极。A filler is filled between the gate oxide layer and the second dielectric layer to form a gate.
在一些实施方式中，在对所述体区进行源注入之后，在所述体区内通过刻蚀形成栅沟槽之前，所述方法还包括：对所述体区进行P+注入，形成P+区；In some embodiments, after performing source implantation on the body region and before forming a gate trench in the body region by etching, the method further comprises: performing P+ implantation on the body region to form a P+ region;
于所述栅氧化层和所述第二介电层之间填充多晶硅之后，所述方法还包括：在所述源极和所述P+区的对应位置表面形成Ni salicide，获得源极欧姆接触层。After filling polysilicon between the gate oxide layer and the second dielectric layer, the method further includes: forming Ni salicide on the surfaces of corresponding positions of the source and the P+ region to obtain a source ohmic contact layer.
在一些实施方式中，所述方法还包括：In some embodiments, the method further comprises:
于所述源极欧姆接触层表面形成接触孔；forming a contact hole on the surface of the source ohmic contact layer;
在所述接触孔中填充金属，形成源极电极。The contact hole is filled with metal to form a source electrode.
在一些实施方式中，所述沉积形成第一介电层和第二介电层，包括：In some embodiments, the depositing forms a first dielectric layer and a second dielectric layer, comprising:
沉积氧化硅，以使所述氧化硅覆盖于所述SiC外延层表面以及覆盖于所述栅沟槽的侧壁和底部；Depositing silicon oxide so that the silicon oxide covers the surface of the SiC epitaxial layer and covers the sidewalls and the bottom of the gate trench;
在所述氧化硅上表面沉积氮化硅，以使所述氮化硅填充于所述栅沟槽的剩余区域中；Depositing silicon nitride on the upper surface of the silicon oxide so that the silicon nitride fills the remaining area of the gate trench;
去除所述栅沟槽之外区域的氮化硅和氧化硅，保留栅沟槽中的氮化硅和氧化硅，其中，所述栅沟槽中的所述氧化硅形成所述第一介电层，所述栅沟槽中的所述氮化硅形成所述第二介电层。The silicon nitride and silicon oxide in the area outside the gate trench are removed, and the silicon nitride and silicon oxide in the gate trench are retained, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
在一些实施方式中，所述去除所述栅沟槽之外区域的氮化硅和氧化硅，包括：In some embodiments, removing the silicon nitride and silicon oxide in the area outside the gate trench includes:
采用CMP或干法回刻的方式去除顶部的氮化硅、并去除所述栅沟槽中高出所述SiC外延层的氮化硅；Using CMP or dry etching back to remove the silicon nitride on the top and the silicon nitride in the gate trench that is higher than the SiC epitaxial layer;
采用CMP的方式去除高出所述SiC外延层的氧化硅。The silicon oxide protruding from the SiC epitaxial layer is removed by CMP.
在一些实施方式中，所述去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层，包括：In some embodiments, removing a portion of the first dielectric layer covering the first sidewall and retaining at least the first dielectric layer covering the bottom of the gate trench comprises:
在所述SiC外延层表面涂敷光刻胶，采用光刻工艺对所述光刻胶进行图形化处理，以形成图形化的光刻胶；Applying photoresist on the surface of the SiC epitaxial layer, and patterning the photoresist using a photolithography process to form a patterned photoresist;
依据所述图形化的光刻胶，采用湿法回刻工艺去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层。According to the patterned photoresist, a wet etch-back process is adopted to remove a portion of the first dielectric layer covering the first sidewall, and at least the first dielectric layer covering the bottom of the gate trench is retained.
在一些实施方式中，所述去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层，包括： In some embodiments, removing a portion of the first dielectric layer covering the first sidewall and retaining at least the first dielectric layer covering the bottom of the gate trench comprises:
去除所述覆盖于所述第一侧壁、且与所述第二介电层相同深度的第一介电层。The first dielectric layer covering the first sidewall and having the same depth as the second dielectric layer is removed.
在一些实施方式中，于所述栅氧化层和所述第二介电层之间填充填充物，形成栅极，包括：In some embodiments, filling a filler between the gate oxide layer and the second dielectric layer to form a gate includes:
沉积多晶硅，使所述栅氧化层和所述第二介电层之间的区域形成多晶硅栅，并去除SiC外延层表面的多晶硅。Polysilicon is deposited to form a polysilicon gate in the region between the gate oxide layer and the second dielectric layer, and the polysilicon on the surface of the SiC epitaxial layer is removed.
根据本申请的另一方面，提供一种沟槽型SiC MOSFET器件结构，所述沟槽型SiC MOSFET器件结构包括：According to another aspect of the present application, a trench SiC MOSFET device structure is provided, wherein the trench SiC MOSFET device structure comprises:
位于SiC衬底上的SiC外延层；A SiC epitaxial layer on a SiC substrate;
位于所述SiC外延层中的体区；a body region located in the SiC epitaxial layer;
位于所述体区中的源极；a source located in the body region;
位于所述体区内的栅沟槽，所述栅沟槽的底部位于所述SiC外延层的漂移区，所述栅沟槽的第一侧壁穿过所述源极或与所述源极接触；a gate trench located in the body region, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and a first sidewall of the gate trench passes through the source or contacts the source;
在所述栅沟槽的所述第一侧壁生长的栅氧化层；a gate oxide layer grown on the first sidewall of the gate trench;
覆盖于所述栅沟槽的底部及第二侧壁表面的第一介电层；A first dielectric layer covering the bottom and second sidewall surface of the gate trench;
填充于所述栅沟槽内、且与所述第一介电层相接触的第二介电层；a second dielectric layer filled in the gate trench and in contact with the first dielectric layer;
填充于所述栅沟槽内、且位于所述栅氧化层和所述第二介电层之间的栅极。A gate is filled in the gate trench and located between the gate oxide layer and the second dielectric layer.
在一些实施方式中，所述沟槽型SiC MOSFET器件结构还包括：In some embodiments, the trench SiC MOSFET device structure further includes:
对所述体区进行P+注入后形成的P+区；A P+ region formed by performing P+ implantation on the body region;
在所述源极和所述P+区的对应位置表面形成的源极欧姆接触层；A source ohmic contact layer formed on the surface of the source and the P+ region at corresponding positions;
在所述源极欧姆接触层表面形成的接触孔以及填充于所述接触孔中的源极金属。A contact hole is formed on the surface of the source ohmic contact layer and a source metal is filled in the contact hole.
与现有技术相比，本申请具有以下优点：Compared with the prior art, this application has the following advantages:
本申请实施例提供的沟槽型SiC MOSFET器件制作方法包括：在SiC衬底上生长SiC外延层；在SiC外延层形成体区；对体区进行源注入，形成源极；在体区内通过刻蚀形成栅沟槽，栅沟槽的底部位于SiC外延层的漂移区，栅沟槽的第一侧壁穿过源极或与源极接触；沉积形成第一介电层和第二介电层，第一介电层覆盖于栅沟槽的第一侧壁、第二侧壁以及底部，第二介电层填充于栅沟槽的第一侧壁和第二侧壁之间的中空区域；去除部分覆盖于第一侧壁的第一介电层，并至少保留覆盖于栅沟槽底部的第一介电层，形成空置区域；在露出于空置区域的第一侧壁表面生长栅氧化层；于栅氧化层和第二介电层之间填充填充物，形成栅极。通过在栅沟槽中沉积形成第一介电层和第二介电层，在去除部分覆盖于第一侧壁的第一介电层、至少保留覆盖于栅沟槽底部的部分第一介电层、以形成空置区 域之后，在露出于空置区域的第一侧壁表面生长栅氧化层，并于栅氧化层和第二介电层之间填充填充物，形成栅极；通过该种栅沟槽填充方式，可使得栅沟槽内剩余的第一介电层和第二介电层形成用于保护栅氧化层的厚氧化层，降低栅沟槽底部电场，优化反向截止状态时栅沟槽底部电场分布，提升器件的可靠性；并且，栅沟槽底部和侧壁的厚氧化层可大幅度降低栅电荷，优化器件的开关特性。并且，上述栅沟槽填充方式无需精确控制体区的深度，无需严格控制栅极在栅沟槽中的位置，可使得沟槽型SiC MOSFET器件的制造工艺简单，且对设备和机台要求较低，具有较高的可制造性。The method for manufacturing a trench SiC MOSFET device provided in an embodiment of the present application includes: growing a SiC epitaxial layer on a SiC substrate; forming a body region in the SiC epitaxial layer; performing source injection into the body region to form a source electrode; forming a gate trench in the body region by etching, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and the first side wall of the gate trench passes through the source electrode or contacts the source electrode; depositing a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer fills the hollow area between the first side wall and the second side wall of the gate trench; removing a portion of the first dielectric layer covering the first side wall, and retaining at least the first dielectric layer covering the bottom of the gate trench to form a vacant area; growing a gate oxide layer on the surface of the first side wall exposed in the vacant area; and filling a filler between the gate oxide layer and the second dielectric layer to form a gate electrode. The first dielectric layer and the second dielectric layer are deposited in the gate trench, and a portion of the first dielectric layer covering the first sidewall is removed, and at least a portion of the first dielectric layer covering the bottom of the gate trench is retained to form a vacant area. After the gate is formed, a gate oxide layer is grown on the surface of the first sidewall exposed in the vacant area, and a filler is filled between the gate oxide layer and the second dielectric layer to form a gate. Through this gate trench filling method, the remaining first dielectric layer and second dielectric layer in the gate trench can form a thick oxide layer for protecting the gate oxide layer, reduce the electric field at the bottom of the gate trench, optimize the electric field distribution at the bottom of the gate trench in the reverse cutoff state, and improve the reliability of the device. In addition, the thick oxide layer at the bottom and sidewall of the gate trench can greatly reduce the gate charge and optimize the switching characteristics of the device. In addition, the above-mentioned gate trench filling method does not need to accurately control the depth of the body region, and does not need to strictly control the position of the gate in the gate trench, which can make the manufacturing process of the trench SiC MOSFET device simple, and has low requirements on equipment and machine, and has high manufacturability.
上述说明仅是本申请技术方案的概述，为了能够更清楚了解本申请的技术手段，而可依照说明书的内容予以实施，并且为了让本申请的上述和其他目的、特征和优点能够更明显易懂，以下特举较佳实施例，并配合附图，详细说明如下。The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specifically cites the preferred embodiments and describes them in detail with the accompanying drawings.
附图说明BRIEF DESCRIPTION OF THE DRAWINGS
图1是本申请实施例提供的沟槽型SiC MOSFET器件制作方法的流程示意图；FIG1 is a schematic diagram of a process for manufacturing a trench SiC MOSFET device provided in an embodiment of the present application;
图2为本申请实施例提供的沟槽型SiC MOSFET器件结构的示意图；FIG2 is a schematic diagram of a trench SiC MOSFET device structure provided in an embodiment of the present application;
图3-图17为本实施例提供的沟槽型SiC MOSFET器件制作工艺的示意图。Figures 3 to 17 are schematic diagrams of the trench SiC MOSFET device manufacturing process provided in this embodiment.
【符号说明】
衬底1、SiC外延层2、体区3、源极4、栅沟槽5、第一介电层6、第二介电层7、栅
极8、栅氧化层9、P+区10、Ni salicide11、接触孔12、源极金属13、介质层14、表面金属15、背面金属16、光刻胶17、临时保护层18、漂移区、第一侧壁19、第二侧壁20【Symbol Description】
Substrate 1, SiC epitaxial layer 2, body region 3, source 4, gate trench 5, first dielectric layer 6, second dielectric layer 7, gate 8, gate oxide layer 9, P+ region 10, Ni salicide 11, contact hole 12, source metal 13, dielectric layer 14, surface metal 15, back metal 16, photoresist 17, temporary protection layer 18, drift region, first side wall 19, second side wall 20
具体实施方式Detailed ways
在下面的描述中阐述了很多具体细节以便于充分理解本申请。但是本申请能够以很多不同于在此描述的其它方式来实施，本领域技术人员可以在不违背本申请内涵的情况下做类似推广，因此本申请不受下面公开的具体实施的限制。Many specific details are described in the following description to facilitate a full understanding of the present application. However, the present application can be implemented in many other ways than those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present application. Therefore, the present application is not limited to the specific implementation disclosed below.
相较于传统硅(Si)材料，碳化硅(Silicon Carbide，简称SiC)具有禁带宽度宽、临界击穿电场高、饱和漂移速度大和热导率高等优点，是制备高压大功率器件的理想材料，在高能效、高功率、高温电力电子技术中应用广泛，已成为当前功率半导体技术的研究热点。基于SiC制备的功率MOSFET器件具有电流密度大、击穿电压高、损耗低、高温特性好及耐辐射等优点，相比传统的Si基功率MOSFET器件，可简化功率电子系统的拓扑结构、 减小系统体积、降低功率损耗。功率SiC MOSFET器件结构有平栅型和沟槽型两种，平栅型功率SiC MOSFET器件由于存在寄生结型场效应晶体管(Junction Field Electric Transistor，JFET)结构，导致器件导通电阻增加，增加器件功耗。沟槽型功率SiC MOSFET器件由于采用了沟槽栅极结构，不存在JFET区，器件导通电阻可显著降低，并且导电沟道由横向改为纵向，有效节约了器件面积，功率密度大幅提升。Compared with traditional silicon (Si) materials, silicon carbide (SiC) has the advantages of wide bandgap, high critical breakdown electric field, large saturation drift velocity and high thermal conductivity. It is an ideal material for preparing high-voltage and high-power devices. It is widely used in high-efficiency, high-power and high-temperature power electronics technology and has become a research hotspot in current power semiconductor technology. Power MOSFET devices based on SiC have the advantages of high current density, high breakdown voltage, low loss, good high-temperature characteristics and radiation resistance. Compared with traditional Si-based power MOSFET devices, they can simplify the topology of power electronic systems. Reduce system volume and power loss. Power SiC MOSFET device structures include flat gate type and trench type. Flat gate power SiC MOSFET devices have a parasitic junction field effect transistor (JFET) structure, which increases the device on-resistance and device power consumption. Trench power SiC MOSFET devices use a trench gate structure and do not have a JFET region, so the device on-resistance can be significantly reduced, and the conductive channel is changed from horizontal to vertical, which effectively saves device area and greatly improves power density.
由于沟槽型功率SiC MOSFET器件有着更低的导通电阻和更大的电流密度，因此其具有集成度高、导通电阻低、开关速度快、开关损耗小等优点，在低压和高压领域成为相关应用的主流，随着应用领域的广泛扩展及设备性能的不断提升，对沟槽型功率SiC MOSFET器件的可靠性要求也越来越高。Since trench power SiC MOSFET devices have lower on-resistance and greater current density, they have the advantages of high integration, low on-resistance, fast switching speed, and low switching loss. They have become the mainstream of related applications in low-voltage and high-voltage fields. With the widespread expansion of application fields and the continuous improvement of equipment performance, the reliability requirements for trench power SiC MOSFET devices are also becoming higher and higher.
然而，沟槽型功率SiC MOSFET器件由于受沟槽栅底角处电场聚集效应的影响，其存在底部电场较大、容易被击穿或注入界面态的问题，限制了其在高可靠性场景的应用。具体的，沟槽型功率SiC MOSFET器件有着更低的导通电阻和更大的电流密度，但由于栅沟槽底部电场过大，栅氧化层易损伤和击穿，限制了其在高可靠性场景的应用。为了保护栅沟槽的栅氧化层，现有的沟槽型SiC MOSFET器件通过深体区提前耗尽的方式保护栅沟槽底部的栅氧化层，即，体区纵向上处于栅沟槽的下方，当器件承受反向耐压时耗尽层展宽、直至沟槽两侧的耗尽层互相闭合，以保护栅沟槽底部的栅氧化层。然而，该工艺中需要精确控制体区的深度，使得工艺复杂度较高，例如，体区深度太浅会导致对栅氧化层的保护减弱，器件浪涌能力变弱，体区深度太深会导致器件耐压降低。However, due to the influence of the electric field concentration effect at the bottom corner of the trench gate, the trench power SiC MOSFET device has a large bottom electric field and is easily broken down or injected into the interface state, which limits its application in high-reliability scenarios. Specifically, the trench power SiC MOSFET device has a lower on-resistance and a larger current density, but due to the excessive electric field at the bottom of the gate trench, the gate oxide layer is easily damaged and broken down, which limits its application in high-reliability scenarios. In order to protect the gate oxide layer of the gate trench, the existing trench SiC MOSFET device protects the gate oxide layer at the bottom of the gate trench by depleting the deep body region in advance, that is, the body region is located below the gate trench in the vertical direction, and when the device is subjected to reverse withstand voltage, the depletion layer widens until the depletion layers on both sides of the trench are closed to each other to protect the gate oxide layer at the bottom of the gate trench. However, the process requires precise control of the depth of the body region, which makes the process complex. For example, if the depth of the body region is too shallow, the protection of the gate oxide layer will be weakened, and the surge capability of the device will be weakened. If the depth of the body region is too deep, the device will have a reduced withstand voltage.
针对现有的沟槽型功率SiC MOSFET器件存在的上述问题，为了解决现有的因沟槽型功率SiC MOSFET器件存在栅沟槽底部电场较大、栅氧易损伤和击穿，限制了其在高可靠性场景的应用的问题，以及为了降低工艺复杂度，本申请实施例提供一种沟槽型SiC MOSFET器件制作方法以及一种沟槽型SiC MOSFET器件结构，请参考图1、图2以及图3-图17理解该实施例，图1为本实施例提供的沟槽型SiC MOSFET器件制作方法的流程图，图2为本实施例提供的沟槽型SiC MOSFET器件结构的示意图；图3-图17为本实施例提供的沟槽型SiC MOSFET器件制作工艺的示意图。In view of the above-mentioned problems existing in the existing trench power SiC MOSFET devices, in order to solve the problem that the existing trench power SiC MOSFET devices have a large electric field at the bottom of the gate trench, and the gate oxide is easily damaged and broken down, which limits their application in high-reliability scenarios, and in order to reduce the complexity of the process, an embodiment of the present application provides a method for manufacturing a trench SiC MOSFET device and a trench SiC MOSFET device structure. Please refer to Figures 1, 2 and 3-17 to understand this embodiment. Figure 1 is a flow chart of the method for manufacturing a trench SiC MOSFET device provided in this embodiment, and Figure 2 is a schematic diagram of the trench SiC MOSFET device structure provided in this embodiment; Figures 3-17 are schematic diagrams of the trench SiC MOSFET device manufacturing process provided in this embodiment.
如图1-图17所示，本实施例提供的沟槽型SiC MOSFET器件制作方法包括如下步骤：As shown in FIGS. 1 to 17 , the method for manufacturing a trench SiC MOSFET device provided in this embodiment includes the following steps:
S1：在SiC衬底1上形成SiC外延层2；具体可在重掺杂的SiC衬底1的上表面生长轻掺杂的SiC外延层2。S1: forming a SiC epitaxial layer 2 on a SiC substrate 1 ; specifically, a lightly doped SiC epitaxial layer 2 may be grown on the upper surface of a heavily doped SiC substrate 1 .
S2：在SiC外延层2形成体区3(如图3所示)；例如，对SiC外延层2进行Al离子注入，注入能量可以为500-800Kev，注入剂量可以为E13原子数每平方厘米。 S2: forming a body region 3 in the SiC epitaxial layer 2 (as shown in FIG. 3 ); for example, Al ion implantation is performed on the SiC epitaxial layer 2 , the implantation energy may be 500-800 Kev, and the implantation dose may be E13 atoms per square centimeter.
S3：对所述体区3进行源注入，形成源极4(如图4所示)，例如，对体区3进行N+注入，注入能量可以为50-70Kev，注入剂量可以为E15原子数每平方厘米。S3: performing source implantation on the body region 3 to form a source 4 (as shown in FIG. 4 ). For example, performing N+ implantation on the body region 3 , the implantation energy may be 50-70 KeV, and the implantation dose may be E15 atoms per square centimeter.
S4：在所述体区3内通过刻蚀形成栅沟槽5，栅沟槽5的底部位于SiC外延层2的漂移区(如图6所示)，栅沟槽5内壁包括第一侧壁19、第二侧壁20以及沟槽底部，所述栅沟槽5的第一侧壁19穿过所述源极4或与所述源极4接触，以形成沟道；在本实施例中，刻蚀形成栅沟槽5时可采用等离子体干法刻蚀，栅沟槽5的宽度为2um、深度为1.5um。S4: A gate trench 5 is formed in the body region 3 by etching, the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2 (as shown in FIG6 ), the inner wall of the gate trench 5 includes a first side wall 19, a second side wall 20 and a trench bottom, the first side wall 19 of the gate trench 5 passes through the source 4 or contacts the source 4 to form a channel; in the present embodiment, plasma dry etching can be used when etching to form the gate trench 5, and the width of the gate trench 5 is 2 um and the depth is 1.5 um.
S5：沉积形成第一介电层6和第二介电层7，所述第一介电层6覆盖于所述栅沟槽5的第一侧壁19、第二侧壁20以及沟槽底部，所述第二介电层7填充于所述栅沟槽5的第一侧壁19和第二侧壁20之间的中空区域(如图7-图11所示)。S5: Deposit to form a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first side wall 19, the second side wall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 fills the hollow area between the first side wall 19 and the second side wall 20 of the gate trench 5 (as shown in Figures 7 to 11).
S6：去除部分覆盖于所述第一侧壁19的第一介电层6，并至少保留覆盖于所述栅沟槽5底部的部分第一介电层6，形成空置区域(如图12所示)。S6: removing a portion of the first dielectric layer 6 covering the first sidewall 19 and retaining at least a portion of the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area (as shown in FIG. 12 ).
S7：在露出于所述空置区域的第一侧壁19表面生长栅氧化层9(如图13所示)；栅氧化层9的厚度可以为400-800A，生长栅氧化层9的方式可以为采用化学汽相沉积法各向同性生长。S7: growing a gate oxide layer 9 on the surface of the first side wall 19 exposed in the vacant area (as shown in FIG. 13 ); the thickness of the gate oxide layer 9 may be 400-800 Å, and the gate oxide layer 9 may be grown isotropically by chemical vapor deposition.
S8：于所述栅氧化层9和所述第二介电层7之间填充填充物，形成栅极8(如图14所示)。S8: Filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8 (as shown in FIG. 14 ).
通过在栅沟槽5中沉积形成第一介电层6和第二介电层7，在去除部分覆盖于第一侧壁19的第一介电层6、至少保留覆盖于栅沟槽5底部的部分第一介电层6、以形成空置区域之后，在露出于空置区域的第一侧壁19表面生长栅氧化层9，并于栅氧化层9和第二介电层7之间填充填充物，形成栅极8；通过该种栅沟槽5填充方式，可使得剩余的第一介电层6和第二介电层7形成用于保护栅氧化层9的厚氧化层，降低栅沟槽5底部电场，优化反向截止状态时栅沟槽5底部电场分布，提升器件的可靠性；并且，栅沟槽5底部和侧壁的厚氧化层可大幅度降低栅电荷，优化器件的开关特性。并且，上述栅沟槽5填充方式无需精确控制体区3的深度，无需严格控制栅极8在栅沟槽5中的位置，可使得制造工艺简单，且对设备和机台要求较低，具有较高的可制造性。The first dielectric layer 6 and the second dielectric layer 7 are deposited in the gate trench 5, and after removing part of the first dielectric layer 6 covering the first sidewall 19 and retaining at least part of the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, a gate oxide layer 9 is grown on the surface of the first sidewall 19 exposed in the vacant area, and a filler is filled between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; through this gate trench 5 filling method, the remaining first dielectric layer 6 and the second dielectric layer 7 can form a thick oxide layer for protecting the gate oxide layer 9, reduce the electric field at the bottom of the gate trench 5, optimize the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improve the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 can greatly reduce the gate charge and optimize the switching characteristics of the device. In addition, the above-mentioned gate trench 5 filling method does not need to accurately control the depth of the body region 3, and does not need to strictly control the position of the gate 8 in the gate trench 5, which can make the manufacturing process simple, and has low requirements on equipment and machine, and has high manufacturability.
在本实施例中，在对体区3进行源注入之后，在所述体区3内通过刻蚀形成栅沟槽5之前，所述方法还包括：对所述体区3进行P+注入，形成P+区10(如图5所示)；并且，在于所述栅氧化层9和所述第二介电层7之间填充多晶硅之后，所述方法还包括：在源极4和P+区10的对应位置表面形成Ni salicide11，获得源极欧姆接触层。该过程具体可以为：沉积400A厚度的氧化硅作为临时保护层18，在源极4和P+区10的对应位置形成开 口(如图15所示)，沉积1000A厚度的金属镍(Ni)，经400-500℃退火工艺，去除氧化硅(临时保护层18)表面多余的Ni，再经600-700℃退火工艺，以此在在源极4和P+区10的对应位置的SiC外延层2表面形成Ni salicide11(如图16所示)。In this embodiment, after the source is injected into the body region 3 and before the gate trench 5 is formed in the body region 3 by etching, the method further includes: injecting P+ into the body region 3 to form a P+ region 10 (as shown in FIG. 5 ); and after filling polysilicon between the gate oxide layer 9 and the second dielectric layer 7, the method further includes: forming Ni salicide 11 on the surface of the corresponding position of the source 4 and the P+ region 10 to obtain a source ohmic contact layer. The process can be specifically: depositing a 400A thick silicon oxide as a temporary protective layer 18, forming an opening at the corresponding position of the source 4 and the P+ region 10, and forming a gate trench 5 in the body region 3. The source 4 and the P+ region 10 are provided at the same time as the source 4. A 1000A thick metal nickel (Ni) is deposited, and an annealing process is performed at 400-500°C to remove excess Ni on the surface of the silicon oxide (temporary protective layer 18). An annealing process is then performed at 600-700°C to form Ni salicide 11 on the surface of the SiC epitaxial layer 2 at the corresponding positions of the source 4 and the P+ region 10 (as shown in FIG. 16).
在本实施例中，在于所述栅氧化层9和所述第二介电层7之间填充填充物，以形成栅极8之后，所述方法还包括：于所述源极欧姆接触层表面形成接触孔12，具体可在ILD沉积工艺后形成介质层14，采用光刻刻蚀工艺形成接触孔12；在接触孔12中填充金属，形成源极电极13，例如采用W塞工艺在接触孔12中填充金属钨。在此基础上组装表面金属15及背面金属16，可最终形成如图2所示的沟槽型SiC MOSFET器件。In this embodiment, after filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form the gate 8, the method further includes: forming a contact hole 12 on the surface of the source ohmic contact layer, specifically, a dielectric layer 14 can be formed after an ILD deposition process, and a contact hole 12 is formed by a photolithography process; filling the contact hole 12 with metal to form a source electrode 13, for example, filling the contact hole 12 with metal tungsten by a W plug process. On this basis, the surface metal 15 and the back metal 16 are assembled to finally form a trench SiC MOSFET device as shown in FIG. 2 .
在本实施例中，第一介电层6可以为氧化硅，第二介电层7可以为氮化硅在上述步骤S5中，所述沉积形成第一介电层6和第二介电层7，具体包括如下内容：In this embodiment, the first dielectric layer 6 may be silicon oxide, and the second dielectric layer 7 may be silicon nitride. In the above step S5, the deposition to form the first dielectric layer 6 and the second dielectric layer 7 specifically includes the following contents:
首先，沉积氧化硅(如图7所示)，厚度可以为7000A，以使氧化硅覆盖于SiC外延层2表面以及覆盖于所述栅沟槽5的侧壁(第一侧壁19和第二侧壁20)和底部；First, silicon oxide is deposited (as shown in FIG. 7 ) with a thickness of 7000 Å, so that the silicon oxide covers the surface of the SiC epitaxial layer 2 and covers the sidewalls (the first sidewall 19 and the second sidewall 20 ) and the bottom of the gate trench 5;
其次，在所述氧化硅上表面沉积氮化硅，厚度可以为6000A，以使所述氮化硅覆盖于所述氧化硅表面、并填充于所述栅沟槽5的剩余区域中(如图8所示)；Secondly, silicon nitride is deposited on the upper surface of the silicon oxide, and the thickness can be 6000 Å, so that the silicon nitride covers the surface of the silicon oxide and fills the remaining area of the gate trench 5 (as shown in FIG. 8 );
最后，去除所述栅沟槽5之外区域的氮化硅和氧化硅，保留栅沟槽5中的氮化硅和氧化硅，使所述栅沟槽5中的氧化硅和氮化硅的高度与所述SiC外延层2的高度一致(如图9图11所示)，其中，所述栅沟槽5中的氧化硅形成第一介电层6，栅沟槽5中的氮化硅形成第二介电层7。Finally, the silicon nitride and silicon oxide in the area outside the gate trench 5 are removed, and the silicon nitride and silicon oxide in the gate trench 5 are retained, so that the height of the silicon oxide and silicon nitride in the gate trench 5 is consistent with the height of the SiC epitaxial layer 2 (as shown in Figures 9 and 11), wherein the silicon oxide in the gate trench 5 forms a first dielectric layer 6, and the silicon nitride in the gate trench 5 forms a second dielectric layer 7.
在本实施例中，可通过如下方式去除所述栅沟槽5之外区域的氮化硅和氧化硅：首先，采用CMP或干法回刻的方式去除顶部表面的氮化硅，以露出氧化硅(如图9所示)、并去除所述栅沟槽5中高出所述SiC外延层2的氮化硅(如图10所示)；其次，采用CMP工艺去除高出所述SiC外延层2的氧化硅(如图11所示)。CMP(Chemical Mechanical Polishing，化学机械抛光)采用将机械摩擦和化学腐蚀相结合的工艺对半导体材料表明进行平整处理，与机械抛光相比，CMP工艺能使半导体材料表面变得更加平坦，并且加工成本低、加工方法简单。In this embodiment, the silicon nitride and silicon oxide in the area outside the gate trench 5 can be removed in the following manner: first, the silicon nitride on the top surface is removed by CMP or dry etching to expose the silicon oxide (as shown in FIG. 9 ), and the silicon nitride in the gate trench 5 that is higher than the SiC epitaxial layer 2 is removed (as shown in FIG. 10 ); secondly, the silicon oxide that is higher than the SiC epitaxial layer 2 is removed by CMP process (as shown in FIG. 11 ). CMP (Chemical Mechanical Polishing) uses a process that combines mechanical friction and chemical corrosion to flatten the surface of semiconductor materials. Compared with mechanical polishing, the CMP process can make the surface of semiconductor materials flatter, and the processing cost is low and the processing method is simple.
上述步骤S6中的去除部分覆盖于第一侧壁19的第一介电层6，并至少保留覆盖于栅沟槽5底部的部分第一介电层6，其表征在栅沟槽5深度方向上，去除的第一介电层6仅为覆盖于第一侧壁19的第一介电层6中的一部分，且保留在栅沟槽5底部的第一介电层6可以为覆盖于栅沟槽5底部的第一介电层6中的部分或全部，以此实现在栅沟槽5的第一侧壁19生长栅氧化层9的同时，栅沟槽5底部的部分或全部第一介电层6能够得以保 留。在本实施例中，可去除覆盖于第一侧壁19、且与第二介电层7相同深度的第一介电层6，即，去除第一侧壁19和第二介电层7之间的第一介电层6，以使该区域形成空置区域，且栅沟槽5底部的全部第一介电层6得以保留。在本实施例中，具体可通过如下方式实现上述去除部分第一介电层6的过程：在所述SiC外延层2表面涂敷光刻胶17，采用光刻工艺对所述光刻胶17进行图形化处理，以形成图形化的光刻胶17；依据所述图形化的光刻胶17，采用湿法回刻工艺去除部分覆盖于所述第一侧壁19的第一介电层6，并至少保留覆盖于所述栅沟槽5底部的第一介电层6(如图12所示)。需要说明的是，氮化硅(第二介电层7)可在上述去除部分覆盖于第一侧壁19的第一介电层6时、使覆盖于第二侧壁20的第一介电层6免于去除。In the above step S6, a portion of the first dielectric layer 6 covering the first sidewall 19 is removed, and at least a portion of the first dielectric layer 6 covering the bottom of the gate trench 5 is retained, which indicates that in the depth direction of the gate trench 5, the first dielectric layer 6 removed is only a portion of the first dielectric layer 6 covering the first sidewall 19, and the first dielectric layer 6 retained at the bottom of the gate trench 5 can be a portion or all of the first dielectric layer 6 covering the bottom of the gate trench 5, so that when the gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5, a portion or all of the first dielectric layer 6 at the bottom of the gate trench 5 can be retained. In this embodiment, the first dielectric layer 6 covering the first sidewall 19 and having the same depth as the second dielectric layer 7 can be removed, that is, the first dielectric layer 6 between the first sidewall 19 and the second dielectric layer 7 is removed so that the region forms a vacant region, and the entire first dielectric layer 6 at the bottom of the gate trench 5 is retained. In this embodiment, the above-mentioned process of removing part of the first dielectric layer 6 can be specifically realized in the following manner: a photoresist 17 is coated on the surface of the SiC epitaxial layer 2, and the photoresist 17 is patterned by a photolithography process to form a patterned photoresist 17; based on the patterned photoresist 17, a wet etching back process is used to remove part of the first dielectric layer 6 covering the first sidewall 19, and at least the first dielectric layer 6 covering the bottom of the gate trench 5 is retained (as shown in FIG. 12). It should be noted that silicon nitride (the second dielectric layer 7) can prevent the first dielectric layer 6 covering the second sidewall 20 from being removed when the first dielectric layer 6 covering the first sidewall 19 is partially removed.
在本实施例中，上述步骤S8中的于所述栅氧化层9和所述第二介电层7之间填充填充物，形成栅极8，具体可以是指：沉积掺杂磷的多晶硅，注入剂量可以为1E20原子数每平方厘米，使所述栅氧化层9和所述第二介电层7之间的区域形成多晶硅栅，并去除SiC外延层2表面的多晶硅。In this embodiment, the step S8 of filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8 may specifically refer to: depositing phosphorus-doped polysilicon, the implantation dose may be 1E20 atoms per square centimeter, so that a polysilicon gate is formed in the area between the gate oxide layer 9 and the second dielectric layer 7, and the polysilicon on the surface of the SiC epitaxial layer 2 is removed.
通过上述过程，可使得栅沟槽5中剩余的第一介电层6和第二介电层7形成用于保护栅氧化层9的厚氧化层，降低栅沟槽5底部电场，优化反向截止状态时栅沟槽5底部电场分布，提升器件的可靠性；并且，栅沟槽5底部和侧壁的厚氧化层(剩余的第一介电层6和第二介电层7)可大幅度降低栅电荷，优化器件的开关特性。Through the above process, the remaining first dielectric layer 6 and second dielectric layer 7 in the gate trench 5 can form a thick oxide layer for protecting the gate oxide layer 9, thereby reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 (the remaining first dielectric layer 6 and second dielectric layer 7) can significantly reduce the gate charge and optimize the switching characteristics of the device.
本实施例提供的沟槽型SiC MOSFET器件制作方法，在SiC衬底1上生长SiC外延层2；在SiC外延层2形成体区3；对体区3进行源注入，形成源极4；在体区3内通过刻蚀形成栅沟槽5，栅沟槽5的底部位于SiC外延层2的漂移区，栅沟槽5的第一侧壁19穿过源极4或与源极4接触；沉积形成第一介电层6和第二介电层7，第一介电层6覆盖于栅沟槽5的第一侧壁19、第二侧壁20以及底部，第二介电层7填充于栅沟槽5的第一侧壁19和第二侧壁20之间的中空区域；去除部分覆盖于第一侧壁19的第一介电层6，并至少保留覆盖于栅沟槽5底部的第一介电层6，形成空置区域；在露出于空置区域的第一侧壁19表面生长栅氧化层9；于栅氧化层9和第二介电层7之间填充填充物，形成栅极8。该方法通在栅沟槽5中沉积形成第一介电层6和第二介电层7，在去除部分覆盖于第一侧壁19的第一介电层6、至少保留覆盖于栅沟槽5底部的第一介电层6、以形成空置区域之后，在露出于空置区域的第一侧壁19表面生长栅氧化层9，并于栅氧化层9和第二介电层7之间填充填充物，形成栅极8；通过该种栅沟槽5填充方式，可使得栅沟槽内剩余的第一介电层6和第二介电层7形成用于保护栅氧化层9的厚氧化层，降低栅沟槽5 底部电场，优化反向截止状态时栅沟槽5底部电场分布，提升器件的可靠性；并且，栅沟槽5底部和侧壁的厚氧化层(栅沟槽内剩余的第一介电层6和第二介电层7)可大幅度降低栅电荷，优化器件的开关特性。进一步的，上述栅沟槽5填充方式无需精确控制体区3的深度，无需严格控制栅极8在栅沟槽5中的位置，可使得制造工艺简单，且对设备和机台要求较低，具有较高的可制造性。The present embodiment provides a method for manufacturing a trench SiC MOSFET device, which includes growing a SiC epitaxial layer 2 on a SiC substrate 1; forming a body region 3 in the SiC epitaxial layer 2; performing source implantation on the body region 3 to form a source 4; forming a gate trench 5 in the body region 3 by etching, wherein the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2, and the first sidewall 19 of the gate trench 5 passes through the source 4 or contacts the source 4; depositing a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first sidewall 19, the second sidewall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 fills the hollow area between the first sidewall 19 and the second sidewall 20 of the gate trench 5; removing a portion of the first dielectric layer 6 covering the first sidewall 19, and retaining at least the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area; growing a gate oxide layer 9 on the surface of the first sidewall 19 exposed in the vacant area; and filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8. The method deposits a first dielectric layer 6 and a second dielectric layer 7 in the gate trench 5, removes a portion of the first dielectric layer 6 covering the first sidewall 19, and at least retains the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area, then grows a gate oxide layer 9 on the surface of the first sidewall 19 exposed in the vacant area, and fills a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; through this gate trench 5 filling method, the remaining first dielectric layer 6 and the second dielectric layer 7 in the gate trench can form a thick oxide layer for protecting the gate oxide layer 9, thereby reducing the gate trench 5. The bottom electric field optimizes the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, thereby improving the reliability of the device; and the thick oxide layer at the bottom and sidewall of the gate trench 5 (the first dielectric layer 6 and the second dielectric layer 7 remaining in the gate trench) can significantly reduce the gate charge and optimize the switching characteristics of the device. Furthermore, the above-mentioned gate trench 5 filling method does not require precise control of the depth of the body region 3, and does not require strict control of the position of the gate 8 in the gate trench 5, which can simplify the manufacturing process, and has low requirements on equipment and machines, and has high manufacturability.
本申请另一实施例提供一种沟槽型SiC MOSFET器件结构，该沟槽型SiC MOSFET器件结构通过上述实施例提供的沟槽型SiC MOSFET器件制作方法制作获得，如图2所示，该沟槽型SiC MOSFET器件结构包括：Another embodiment of the present application provides a trench SiC MOSFET device structure, which is manufactured by the trench SiC MOSFET device manufacturing method provided in the above embodiment. As shown in FIG. 2 , the trench SiC MOSFET device structure includes:
位于SiC衬底1上的SiC外延层2；A SiC epitaxial layer 2 located on a SiC substrate 1;
位于所述SiC外延层2中的体区3；A body region 3 located in the SiC epitaxial layer 2;
位于所述体区3中的源极4；a source electrode 4 located in the body region 3;
位于所述体区3内的栅沟槽5，所述栅沟槽5的底部位于所述SiC外延层2的漂移区，所述栅沟槽5的第一侧壁19穿过所述源极4或与所述源极4接触；a gate trench 5 located in the body region 3, wherein the bottom of the gate trench 5 is located in the drift region of the SiC epitaxial layer 2, and a first sidewall 19 of the gate trench 5 passes through the source 4 or contacts the source 4;
在所述栅沟槽5的所述第一侧壁19生长的栅氧化层9；A gate oxide layer 9 grown on the first sidewall 19 of the gate trench 5;
覆盖于所述栅沟槽5的底部及第二侧壁20表面的第一介电层6；A first dielectric layer 6 covering the bottom of the gate trench 5 and the surface of the second sidewall 20;
填充于所述栅沟槽5内、且与所述第一介电层6相接触的第二介电层7；a second dielectric layer 7 filled in the gate trench 5 and in contact with the first dielectric layer 6;
填充于所述栅沟槽5内、且位于所述栅氧化层9和所述第二介电层7之间的栅极8。A gate 8 is filled in the gate trench 5 and located between the gate oxide layer 9 and the second dielectric layer 7 .
在本实施例中，上述沟槽型SiC MOSFET器件结构还包括：对体区3进行P+注入后形成的P+区10；在源极4和P+区10的对应位置表面形成的源极欧姆接触层；在源极欧姆接触层表面形成的接触孔12以及填充于接触孔12中的源极电极13。In this embodiment, the above-mentioned trench SiC MOSFET device structure also includes: a P+ region 10 formed after P+ injection into the body region 3; a source ohmic contact layer formed on the surface of the corresponding position of the source 4 and the P+ region 10; a contact hole 12 formed on the surface of the source ohmic contact layer and a source electrode 13 filled in the contact hole 12.
本实施例提供的沟槽型SiC MOSFET器件结构，栅氧化层9生长于栅沟槽5的第一侧壁19；第一介电层6覆盖于栅沟槽5的底部及第二侧壁20表面；第二介电层7填充于栅沟槽5内、且与第一介电层6相接触；栅极8填充于栅沟槽5内、且位于栅氧化层9和第二介电层7之间。该种栅沟槽填充方式使得栅沟槽中的第一介电层6和第二介电层7形成用于保护栅氧化层9的厚氧化层，降低栅沟槽5底部电场，优化反向截止状态时栅沟槽5底部电场分布，提升器件的可靠性；并且，栅沟槽5底部和侧壁的厚氧化层(第一介电层6和第二介电层7)可大幅度降低栅电荷，优化器件的开关特性。In the trench SiC MOSFET device structure provided in this embodiment, the gate oxide layer 9 is grown on the first side wall 19 of the gate trench 5; the first dielectric layer 6 covers the bottom of the gate trench 5 and the surface of the second side wall 20; the second dielectric layer 7 is filled in the gate trench 5 and is in contact with the first dielectric layer 6; the gate 8 is filled in the gate trench 5 and is located between the gate oxide layer 9 and the second dielectric layer 7. This gate trench filling method allows the first dielectric layer 6 and the second dielectric layer 7 in the gate trench to form a thick oxide layer for protecting the gate oxide layer 9, reducing the electric field at the bottom of the gate trench 5, optimizing the electric field distribution at the bottom of the gate trench 5 in the reverse cutoff state, and improving the reliability of the device; and the thick oxide layer (the first dielectric layer 6 and the second dielectric layer 7) at the bottom and sidewalls of the gate trench 5 can significantly reduce the gate charge and optimize the switching characteristics of the device.
应当说明的是，在本专利的示例和说明书中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任 何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。It should be noted that in the examples and description of this patent, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Any other variation is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, an element limited by the sentence "comprising a" does not exclude the presence of other identical elements in the process, method, article or device including the element.
本申请虽然以较佳实施例公开如上，但其并不是用来限定本申请，任何本领域技术人员在不脱离本申请的精神和范围内，都可以做出可能的变动和修改，因此本申请的保护范围应当以本申请权利要求所界定的范围为准。 Although the present application is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present application. Any technical personnel in this field may make possible changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims of the present application.

Claims (10)

  1. 一种沟槽型SiC MOSFET器件制作方法，其特征在于，所述方法包括：A method for manufacturing a trench SiC MOSFET device, characterized in that the method comprises:
    在SiC衬底上形成SiC外延层；forming a SiC epitaxial layer on a SiC substrate;
    在所述SiC外延层形成体区；forming a body region in the SiC epitaxial layer;
    对所述体区进行源注入，形成源极；Performing source implantation into the body region to form a source electrode;
    在所述体区内通过刻蚀形成栅沟槽，所述栅沟槽的底部位于所述SiC外延层的漂移区，所述栅沟槽的第一侧壁穿过所述源极或与所述源极接触；Forming a gate trench in the body region by etching, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and a first sidewall of the gate trench passes through the source or contacts the source;
    沉积形成第一介电层和第二介电层，所述第一介电层覆盖于所述栅沟槽的所述第一侧壁、第二侧壁以及底部，所述第二介电层填充于所述栅沟槽的第一侧壁和第二侧壁之间的中空区域；Depositing a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first sidewall, the second sidewall and the bottom of the gate trench, and the second dielectric layer fills a hollow area between the first sidewall and the second sidewall of the gate trench;
    去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的部分第一介电层，形成空置区域；Removing a portion of the first dielectric layer covering the first sidewall, and retaining at least a portion of the first dielectric layer covering the bottom of the gate trench to form a vacant area;
    在露出于所述空置区域的第一侧壁表面生长栅氧化层；Growing a gate oxide layer on the first sidewall surface exposed in the vacant area;
    于所述栅氧化层和所述第二介电层之间填充填充物，形成栅极。A filler is filled between the gate oxide layer and the second dielectric layer to form a gate.
  2. 根据权利要求1所述的方法，其特征在于，在对所述体区进行源注入之后，在所述体区内通过刻蚀形成栅沟槽之前，所述方法还包括：对所述体区进行P+注入，形成P+区；The method according to claim 1, characterized in that after performing source implantation on the body region and before forming a gate trench in the body region by etching, the method further comprises: performing P+ implantation on the body region to form a P+ region;
    于所述栅氧化层和所述第二介电层之间填充多晶硅之后，所述方法还包括：在所述源极和所述P+区的对应位置表面形成Ni salicide，获得源极欧姆接触层。After filling polysilicon between the gate oxide layer and the second dielectric layer, the method further includes: forming Ni salicide on the surfaces of corresponding positions of the source and the P+ region to obtain a source ohmic contact layer.
  3. 根据权利要求2所述的方法，其特征在于，所述方法还包括：The method according to claim 2, characterized in that the method further comprises:
    于所述源极欧姆接触层表面形成接触孔；forming a contact hole on the surface of the source ohmic contact layer;
    在所述接触孔中填充金属，形成源极电极。The contact hole is filled with metal to form a source electrode.
  4. 根据权利要求1所述的方法，其特征在于，所述沉积形成第一介电层和第二介电层，包括：The method according to claim 1, characterized in that the deposition to form the first dielectric layer and the second dielectric layer comprises:
    沉积氧化硅，以使所述氧化硅覆盖于所述SiC外延层表面以及覆盖于所述栅沟槽的侧壁和底部；Depositing silicon oxide so that the silicon oxide covers the surface of the SiC epitaxial layer and covers the sidewalls and the bottom of the gate trench;
    在所述氧化硅上表面沉积氮化硅，以使所述氮化硅填充于所述栅沟槽的剩余区域中；Depositing silicon nitride on the upper surface of the silicon oxide so that the silicon nitride fills the remaining area of the gate trench;
    去除所述栅沟槽之外区域的氮化硅和氧化硅，保留栅沟槽中的氮化硅和氧化硅，其中，所述栅沟槽中的所述氧化硅形成所述第一介电层，所述栅沟槽中的所述氮化硅形成所述第二介电层。 The silicon nitride and silicon oxide in the area outside the gate trench are removed, and the silicon nitride and silicon oxide in the gate trench are retained, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
  5. 根据权利要求4所述的方法，其特征在于，所述去除所述栅沟槽之外区域的氮化硅和氧化硅，包括：The method according to claim 4, characterized in that the removing of silicon nitride and silicon oxide in the area outside the gate trench comprises:
    采用CMP或干法回刻的方式去除顶部的氮化硅、并去除所述栅沟槽中高出所述SiC外延层的氮化硅；Using CMP or dry etching back to remove the silicon nitride on the top and the silicon nitride in the gate trench that is higher than the SiC epitaxial layer;
    采用CMP的方式去除高出所述SiC外延层的氧化硅。The silicon oxide protruding from the SiC epitaxial layer is removed by CMP.
  6. 根据权利要求1所述的方法，其特征在于，所述去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层，包括：The method according to claim 1, characterized in that the removing of a portion of the first dielectric layer covering the first sidewall and retaining at least the first dielectric layer covering the bottom of the gate trench comprises:
    在所述SiC外延层表面涂敷光刻胶，采用光刻工艺对所述光刻胶进行图形化处理，以形成图形化的光刻胶；Applying photoresist on the surface of the SiC epitaxial layer, and patterning the photoresist using a photolithography process to form a patterned photoresist;
    依据所述图形化的光刻胶，采用湿法回刻工艺去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层。According to the patterned photoresist, a wet etch-back process is adopted to remove a portion of the first dielectric layer covering the first sidewall, and at least the first dielectric layer covering the bottom of the gate trench is retained.
  7. 根据权利要求1或6所述的方法，其特征在于，所述去除部分覆盖于所述第一侧壁的第一介电层，并至少保留覆盖于所述栅沟槽底部的第一介电层，包括：The method according to claim 1 or 6, characterized in that the removing part of the first dielectric layer covering the first sidewall and at least retaining the first dielectric layer covering the bottom of the gate trench comprises:
    去除所述覆盖于所述第一侧壁、且与所述第二介电层相同深度的第一介电层。The first dielectric layer covering the first sidewall and having the same depth as the second dielectric layer is removed.
  8. 根据权利要求1所述的方法，其特征在于，于所述栅氧化层和所述第二介电层之间填充填充物，形成栅极，包括：The method according to claim 1, characterized in that filling a filler between the gate oxide layer and the second dielectric layer to form a gate comprises:
    沉积多晶硅，使所述栅氧化层和所述第二介电层之间的区域形成多晶硅栅，并去除SiC外延层表面的多晶硅。Polysilicon is deposited to form a polysilicon gate in the region between the gate oxide layer and the second dielectric layer, and the polysilicon on the surface of the SiC epitaxial layer is removed.
  9. 一种沟槽型SiC MOSFET器件结构，其特征在于，所述沟槽型SiC MOSFET器件结构包括：A trench SiC MOSFET device structure, characterized in that the trench SiC MOSFET device structure comprises:
    位于SiC衬底上的SiC外延层；A SiC epitaxial layer on a SiC substrate;
    位于所述SiC外延层中的体区；a body region located in the SiC epitaxial layer;
    位于所述体区中的源极；a source located in the body region;
    位于所述体区内的栅沟槽，所述栅沟槽的底部位于所述SiC外延层的漂移区，所述栅沟槽的第一侧壁穿过所述源极或与所述源极接触；a gate trench located in the body region, wherein the bottom of the gate trench is located in the drift region of the SiC epitaxial layer, and a first sidewall of the gate trench passes through the source or contacts the source;
    在所述栅沟槽的所述第一侧壁生长的栅氧化层；a gate oxide layer grown on the first sidewall of the gate trench;
    覆盖于所述栅沟槽的底部及第二侧壁表面的第一介电层；A first dielectric layer covering the bottom and second sidewall surface of the gate trench;
    填充于所述栅沟槽内、且与所述第一介电层相接触的第二介电层；a second dielectric layer filled in the gate trench and in contact with the first dielectric layer;
    填充于所述栅沟槽内、且位于所述栅氧化层和所述第二介电层之间的栅极。A gate is filled in the gate trench and located between the gate oxide layer and the second dielectric layer.
  10. 根据权利要求9所述的沟槽型SiC MOSFET器件结构，其特征在于，还包括： The trench SiC MOSFET device structure according to claim 9, further comprising:
    对所述体区进行P+注入后形成的P+区；A P+ region formed by performing P+ implantation on the body region;
    在所述源极和所述P+区的对应位置表面形成的源极欧姆接触层；A source ohmic contact layer formed on the surface of the source and the P+ region at corresponding positions;
    在所述源极欧姆接触层表面形成的接触孔以及填充于所述接触孔中的源极金属。 A contact hole is formed on the surface of the source ohmic contact layer and a source metal is filled in the contact hole.
PCT/CN2023/131026 2022-11-11 2023-11-10 Trench-type sic mosfet device structure and manufacturing method therefor WO2024099436A1 (en)

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