CN115642088A - Groove type SiC MOSFET device structure and manufacturing method thereof - Google Patents
Groove type SiC MOSFET device structure and manufacturing method thereof Download PDFInfo
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Abstract
The application discloses a groove type SiC MOSFET device structure and a manufacturing method thereof, wherein the method comprises the following steps: growing a SiC epitaxial layer on the SiC substrate; forming a body region on the SiC epitaxial layer; performing source injection on the body region to form a source electrode; forming a gate trench in the body region by etching; depositing to form a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer is filled in a hollow area between the first side wall and the second side wall of the gate trench; removing part of the first dielectric layer covering the first side wall, and at least reserving the first dielectric layer covering the bottom of the gate trench to form a vacant region; growing a gate oxide layer on the surface of the first side wall exposed out of the vacant area; and filling filler between the gate oxide layer and the second dielectric layer to form a gate. By the gate trench filling mode, the electric field at the bottom of the gate trench can be reduced, the electric field distribution at the bottom of the gate trench in a reverse cut-off state is optimized, and the reliability of a device is improved.
Description
Technical Field
The application relates to the field of semiconductors, in particular to a trench type SiC MOSFET device structure and a manufacturing method thereof.
Background
Modern power electronics are moving towards high power density and high efficiency. Silicon carbide power devices have been rapidly developed in the field of high efficiency power conversion in recent years due to their excellent device characteristics such as high voltage, high frequency, high temperature, and high power density. The SiC MOSFET device has the advantages of high switching speed, high voltage resistance, low power consumption and the like, and is mainly divided into a planar type and a groove type, the groove type power SiC MOSFET device has lower on-resistance and higher current density, can realize lower on-resistance, has the advantages of high integration level, low on-resistance, high switching speed, small switching loss and the like, becomes the mainstream of relevant application in the fields of low voltage and high voltage, and has higher and higher reliability requirements on the groove type power SiMOSFET device along with the wide expansion of the application field and the continuous promotion of the equipment performance. However, the trench type power SiC MOSFET device has the problems that the bottom electric field is large and the device is easily broken down or injected into an interface state, which limits the application of the device in a high-reliability scenario.
Disclosure of Invention
The application provides a groove type SiC MOSFET device manufacturing method and a groove type SiC MOSFET device structure, which aim to solve the problem that the application of the groove type SiC MOSFET device in a high-reliability scene is limited due to the fact that an electric field at the bottom of a grid groove is large, grid oxygen is easy to damage and breakdown and the existing groove type power SiC MOSFET device is provided.
The embodiment of the application provides a manufacturing method of a groove type SiC MOSFET device, which comprises the following steps:
forming a SiC epitaxial layer on a SiC substrate;
forming a body region on the SiC epitaxial layer;
performing source injection on the body region to form a source electrode;
forming a gate trench in the body region by etching, wherein the bottom of the gate trench is positioned in a drift region of the SiC epitaxial layer, and a first side wall of the gate trench penetrates through the source electrode or is in contact with the source electrode;
depositing to form a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer is filled in a hollow area between the first side wall and the second side wall of the gate trench;
removing part of the first dielectric layer covering the first side wall, and at least reserving part of the first dielectric layer covering the bottom of the gate trench to form a vacant area;
growing a gate oxide layer on the surface of the first side wall exposed out of the vacant region;
and filling filler between the gate oxide layer and the second dielectric layer to form a gate.
In some embodiments, after the source implanting the body region and before forming a gate trench in the body region by etching, the method further comprises: performing P + injection on the body region to form a P + region;
after filling polysilicon between the gate oxide layer and the second dielectric layer, the method further comprises: and forming Ni salicide on the surfaces of the source electrode and the corresponding position of the P + region to obtain an ohmic contact layer of the source electrode.
In some embodiments, the method further comprises:
forming a contact hole on the surface of the source ohmic contact layer;
and filling metal in the contact hole to form a source electrode.
In some embodiments, the depositing forms a first dielectric layer and a second dielectric layer, including:
depositing silicon oxide to enable the silicon oxide to cover the surface of the SiC epitaxial layer and the side wall and the bottom of the gate groove;
depositing silicon nitride on the upper surface of the silicon oxide so that the silicon nitride is filled in the remaining area of the gate trench;
and removing the silicon nitride and the silicon oxide in the region outside the gate trench, and reserving the silicon nitride and the silicon oxide in the gate trench, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
In some embodiments, the removing the silicon nitride and the silicon oxide in the region outside the gate trench includes:
removing the silicon nitride on the top in a CMP or dry back etching mode, and removing the silicon nitride higher than the SiC epitaxial layer in the gate trench;
and removing the silicon oxide higher than the SiC epitaxial layer by adopting a CMP mode.
In some embodiments, the removing part of the first dielectric layer covering the first sidewall and at least remaining the first dielectric layer covering the bottom of the gate trench includes:
coating photoresist on the surface of the SiC epitaxial layer, and carrying out patterning treatment on the photoresist by adopting a photoetching process to form patterned photoresist;
and removing part of the first dielectric layer covering the first side wall by adopting a wet back etching process according to the patterned photoresist, and at least reserving the first dielectric layer covering the bottom of the gate trench.
In some embodiments, the removing the portion of the first dielectric layer covering the first sidewall and at least remaining the first dielectric layer covering the bottom of the gate trench includes:
and removing the first dielectric layer which covers the first side wall and has the same depth as the second dielectric layer.
In some embodiments, filling a filler between the gate oxide layer and the second dielectric layer to form a gate electrode, includes:
and depositing polycrystalline silicon, forming a polycrystalline silicon gate in a region between the gate oxide layer and the second dielectric layer, and removing the polycrystalline silicon on the surface of the SiC epitaxial layer.
According to another aspect of the present invention, there is provided a trench type SiC MOSFET device structure, including:
a SiC epitaxial layer on the SiC substrate;
a body region located in the SiC epitaxial layer;
a source located in the body region;
the gate trench is positioned in the body region, the bottom of the gate trench is positioned in a drift region of the SiC epitaxial layer, and a first side wall of the gate trench penetrates through the source electrode or is in contact with the source electrode;
a gate oxide layer grown on the first side wall of the gate trench;
the first dielectric layer covers the bottom of the gate groove and the surface of the second side wall;
the second dielectric layer is filled in the gate trench and is in contact with the first dielectric layer;
and the grid electrode is filled in the grid groove and positioned between the grid oxide layer and the second dielectric layer.
In some embodiments, the trench SiC MOSFET device structure further comprises:
a P + region formed after P + injection is carried out on the body region;
a source ohmic contact layer formed on the surface of the source and the corresponding position of the P + region;
the contact hole is formed on the surface of the source ohmic contact layer, and the source metal is filled in the contact hole.
Compared with the prior art, the method has the following advantages:
the manufacturing method of the groove type SiC MOSFET device provided by the embodiment of the application comprises the following steps: growing a SiC epitaxial layer on the SiC substrate; forming a body region on the SiC epitaxial layer; performing source injection on the body region to form a source electrode; forming a gate trench in the body region by etching, wherein the bottom of the gate trench is positioned in a drift region of the SiC epitaxial layer, and the first side wall of the gate trench penetrates through the source electrode or is in contact with the source electrode; depositing to form a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer is filled in a hollow area between the first side wall and the second side wall of the gate trench; removing part of the first dielectric layer covering the first side wall, and at least reserving the first dielectric layer covering the bottom of the gate trench to form a vacant region; growing a gate oxide layer on the surface of the first side wall exposed out of the vacant region; and filling filler between the gate oxide layer and the second dielectric layer to form a gate. Forming a first dielectric layer and a second dielectric layer in the gate trench by deposition, removing part of the first dielectric layer covering the first side wall, at least reserving part of the first dielectric layer covering the bottom of the gate trench to form a vacant region, growing a gate oxide layer on the surface of the first side wall exposed out of the vacant region, and filling filler between the gate oxide layer and the second dielectric layer to form a gate; by the gate trench filling mode, the first dielectric layer and the second dielectric layer which are remained in the gate trench can form a thick oxide layer for protecting the gate oxide layer, so that the electric field at the bottom of the gate trench is reduced, the distribution of the electric field at the bottom of the gate trench in a reverse cut-off state is optimized, and the reliability of a device is improved; in addition, the thick oxide layers at the bottom and the side wall of the gate trench can greatly reduce gate charges and optimize the switching characteristics of the device. In addition, the gate trench filling mode does not need to accurately control the depth of the body region, and does not need to strictly control the position of the gate in the gate trench, so that the manufacturing process of the trench type SiC MOSFET device is simple, the requirements on equipment and machines are low, and the trench type SiC MOSFET device has high manufacturability.
The foregoing description is only an overview of the technical solutions of the present application, and in order to make the technical means of the present application more clearly understood, the present application may be implemented in accordance with the content of the description, and in order to make the above and other objects, features, and advantages of the present application more clearly understood, the following preferred embodiments are specifically described below with reference to the accompanying drawings.
Drawings
Fig. 1 is a schematic flow chart of a method for manufacturing a trench SiC MOSFET device according to an embodiment of the present application;
fig. 2 is a schematic diagram of a trench SiC MOSFET device structure provided in an embodiment of the present application;
fig. 3-17 are schematic diagrams illustrating a manufacturing process of a trench SiC MOSFET device according to this embodiment;
[ notation ] to show
The transistor comprises a substrate 1, a SiC epitaxial layer 2, a body region 3, a source electrode 4, a gate trench 5, a first dielectric layer 6, a second dielectric layer 7, a gate electrode 8, a gate oxide layer 9, a P + region 10, nisalicide11, a contact hole 12, a source electrode metal 13, a dielectric layer 14, a surface metal 15, a back metal 16, photoresist 17, a temporary protection layer 18, a drift region, a first side wall 19 and a second side wall 20
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. This application is capable of implementation in many different ways than those herein set forth and of similar import by those skilled in the art without departing from the spirit of this application and is therefore not limited to the specific implementations disclosed below.
Compared with the traditional Silicon (Si) material, silicon Carbide (SiC) has the advantages of wide forbidden bandwidth, high critical breakdown electric field, large saturation drift velocity, high thermal conductivity and the like, is an ideal material for preparing high-voltage and high-power devices, is widely applied to the high-energy-efficiency, high-power and high-temperature power electronic technology, and has become a research hotspot of the current power semiconductor technology. The power MOSFET device prepared based on SiC has the advantages of large current density, high breakdown voltage, low loss, good high-temperature characteristic, radiation resistance and the like, and compared with the traditional Si-based power MOSFET device, the power MOSFET device can simplify the topological structure of a power electronic system, reduce the system volume and reduce the power loss. The structures of the power SiC MOSFET device comprise a flat gate type and a groove type, and due to the existence of a parasitic Junction Field Effect Transistor (JFET) structure, the on-resistance of the device is increased, and the power consumption of the device is increased. The groove type power SiC MOSFET device adopts a groove grid structure, a JFET (junction field effect transistor) area does not exist, the on-resistance of the device can be obviously reduced, the transverse direction of a conducting channel is changed into the longitudinal direction, the area of the device is effectively saved, and the power density is greatly improved.
Because the groove type power SiC MOSFET device has lower on-resistance and higher current density, the groove type power SiC MOSFET device has the advantages of high integration level, low on-resistance, high switching speed, small switching loss and the like, becomes the mainstream of relevant application in the fields of low voltage and high voltage, and has higher and higher reliability requirements on the groove type power SiC MOSFET device along with the wide expansion of the application field and the continuous improvement of the equipment performance.
However, the trench type power SiC MOSFET device is affected by the electric field concentration effect at the bottom corner of the trench gate, and has the problems that the bottom electric field is large and is easily broken down or injected into an interface state, which limits the application of the device in a high-reliability scenario. Specifically, the trench type power SiC MOSFET device has a lower on-resistance and a higher current density, but because the electric field at the bottom of the gate trench is too large, the gate oxide layer is easily damaged and broken down, which limits the application thereof in a high-reliability scenario. In order to protect the gate oxide layer of the gate trench, the conventional trench SiC MOSFET device protects the gate oxide layer at the bottom of the gate trench in a manner that a deep body region is depleted in advance, that is, a body region is longitudinally positioned below the gate trench, and when the device bears reverse withstand voltage, the depletion layers widen until the depletion layers at two sides of the trench are closed to protect the gate oxide layer at the bottom of the gate trench. However, the process needs to control the depth of the body region precisely, so that the process complexity is high, for example, too shallow depth of the body region can lead to weak protection of a gate oxide layer, weak surge capability of a device, and too deep depth of the body region can lead to reduced withstand voltage of the device.
For the above problems of the existing trench type power SiC MOSFET device, in order to solve the problem that the application of the existing trench type power SiC MOSFET device is limited in a high reliability scenario due to a large electric field at the bottom of a gate trench and easy damage and breakdown of gate oxide, and to reduce process complexity, an embodiment of the present application provides a method for manufacturing a trench type SiC MOSFET device and a trench type SiC MOSFET device structure, and please refer to fig. 1, fig. 2, and fig. 3 to fig. 17 to understand the embodiment, fig. 1 is a flowchart of a method for manufacturing a trench type SiC MOSFET device provided in the present embodiment, and fig. 2 is a schematic diagram of a trench type SiC MOSFET device structure provided in the present embodiment; fig. 3 to fig. 17 are schematic diagrams of a manufacturing process of the trench SiC MOSFET device provided in this embodiment.
As shown in fig. 1 to fig. 17, the method for manufacturing a trench SiC MOSFET device provided in this embodiment includes the following steps:
s1: forming a SiC epitaxial layer 2 on a SiC substrate 1; in particular, a lightly doped SiC epitaxial layer 2 may be grown on the upper surface of a heavily doped SiC substrate 1.
S2: forming a body region 3 in the SiC epitaxial layer 2 (as shown in fig. 3); for example, the SiC epitaxial layer 2 may be implanted with Al ions at an implantation energy of 500 to 800Kev and at an implantation dose of E13 atoms per square centimeter.
S3: the source region 3 is source implanted to form a source 4 (as shown in figure 4), for example, the body region 3 is N + implanted, the implant energy may be 50-70Kev, and the implant dose may be E15 atoms per square centimeter.
S4: forming a gate trench 5 in the body region 3 by etching, wherein the bottom of the gate trench 5 is located in a drift region (shown in fig. 6) of the SiC epitaxial layer 2, the inner wall of the gate trench 5 includes a first side wall 19, a second side wall 20 and a trench bottom, and the first side wall 19 of the gate trench 5 passes through the source 4 or contacts with the source 4 to form a channel; in this embodiment, when the gate trench 5 is formed by etching, a plasma dry etching may be used, and the width of the gate trench 5 is 2um and the depth thereof is 1.5um.
S5: depositing to form a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first sidewall 19, the second sidewall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 fills a hollow region between the first sidewall 19 and the second sidewall 20 of the gate trench 5 (as shown in fig. 7-11).
S6: part of the first dielectric layer 6 covering the first sidewall 19 is removed, and at least part of the first dielectric layer 6 covering the bottom of the gate trench 5 remains, forming an empty region (as shown in fig. 12).
S7: growing a gate oxide layer 9 on the surface of the first side wall 19 exposed in the vacant region (as shown in fig. 13); the thickness of the gate oxide layer 9 can be 400-800A, and the manner of growing the gate oxide layer 9 can be isotropic growth by using a chemical vapor deposition method.
S8: and filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8 (as shown in fig. 14).
Forming a first dielectric layer 6 and a second dielectric layer 7 in the gate trench 5 by deposition, removing part of the first dielectric layer 6 covering the first side wall 19, at least reserving part of the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant region, growing a gate oxide layer 9 on the surface of the first side wall 19 exposed out of the vacant region, and filling filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; by adopting the filling mode of the gate trench 5, the residual first dielectric layer 6 and the second dielectric layer 7 can form a thick oxide layer for protecting the gate oxide layer 9, so that the electric field at the bottom of the gate trench 5 is reduced, the distribution of the electric field at the bottom of the gate trench 5 in a reverse cut-off state is optimized, and the reliability of a device is improved; moreover, the thick oxide layers at the bottom and the side wall of the gate trench 5 can greatly reduce gate charges and optimize the switching characteristics of the device. In addition, the filling mode of the gate trench 5 does not need to accurately control the depth of the body region 3, and does not need to strictly control the position of the gate 8 in the gate trench 5, so that the manufacturing process is simple, the requirements on equipment and machines are low, and the manufacturability is high.
In this embodiment, after performing source implantation on the body region 3, before forming the gate trench 5 in the body region 3 by etching, the method further includes: performing P + implantation on the body region 3 to form a P + region 10 (as shown in fig. 5); and, after filling polysilicon between the gate oxide layer 9 and the second dielectric layer 7, the method further comprises: and forming Nisalicide11 on the surfaces of the source electrode 4 and the corresponding position of the P + region 10 to obtain a source electrode ohmic contact layer. The process may specifically be: depositing silicon oxide with the thickness of 400A as a temporary protection layer 18, forming openings at corresponding positions of the source 4 and the P + region 10 (as shown in FIG. 15), depositing metal nickel (Ni) with the thickness of 1000A, removing redundant Ni on the surface of the silicon oxide (temporary protection layer 18) through an annealing process at 400-500 ℃, and then performing an annealing process at 600-700 ℃ so as to form Nisalicide11 on the surface of the SiC epitaxial layer 2 at corresponding positions of the source 4 and the P + region 10 (as shown in FIG. 16).
In this embodiment, after filling a filler between the gate oxide layer 9 and the second dielectric layer 7 to form the gate 8, the method further comprises: forming a contact hole 12 on the surface of the source ohmic contact layer, specifically forming a dielectric layer 14 after an ILD deposition process, and forming the contact hole 12 by adopting a photoetching process; the contact hole 12 is filled with metal to form a source electrode 13, and the contact hole 12 is filled with metal tungsten by, for example, a W plug process. On the basis of this, the surface metal 15 and the back metal 16 are assembled to finally form the trench SiC MOSFET device shown in fig. 2.
In this embodiment, the first dielectric layer 6 may be silicon oxide, the second dielectric layer 7 may be silicon nitride, and in step S5, the first dielectric layer 6 and the second dielectric layer 7 are formed by deposition, which specifically includes the following steps:
firstly, depositing silicon oxide (as shown in fig. 7) with a thickness of 7000A so that the silicon oxide covers the surface of the SiC epitaxial layer 2 and covers the sidewalls (the first sidewall 19 and the second sidewall 20) and the bottom of the gate trench 5;
secondly, depositing silicon nitride on the upper surface of the silicon oxide with a thickness of 6000A, so that the silicon nitride covers the silicon oxide surface and fills the remaining region of the gate trench 5 (as shown in fig. 8);
finally, removing the silicon nitride and the silicon oxide outside the gate trench 5, and keeping the silicon nitride and the silicon oxide in the gate trench 5 to make the height of the silicon oxide and the silicon nitride in the gate trench 5 consistent with the height of the SiC epitaxial layer 2 (as shown in fig. 9 and 11), wherein the silicon oxide in the gate trench 5 forms a first dielectric layer 6, and the silicon nitride in the gate trench 5 forms a second dielectric layer 7.
In this embodiment, the silicon nitride and the silicon oxide in the region outside the gate trench 5 can be removed as follows: firstly, removing silicon nitride on the top surface by CMP or dry etching to expose silicon oxide (as shown in fig. 9) and removing silicon nitride higher than the SiC epitaxial layer 2 in the gate trench 5 (as shown in fig. 10); next, the silicon oxide higher than the SiC epitaxial layer 2 is removed by a CMP process (as shown in fig. 11). CMP (Chemical Mechanical Polishing) is a process of planarizing a surface of a semiconductor material by a process of combining Mechanical friction and Chemical etching, and compared with Mechanical Polishing, the CMP process can planarize the surface of the semiconductor material more, and has low processing cost and a simple processing method.
The removed part in the step S6 covers the first dielectric layer 6 on the first sidewall 19, and at least a part of the first dielectric layer 6 covering the bottom of the gate trench 5 remains, which is characterized in that in the depth direction of the gate trench 5, the removed first dielectric layer 6 is only a part of the first dielectric layer 6 covering the first sidewall 19, and the first dielectric layer 6 remaining at the bottom of the gate trench 5 may be a part or all of the first dielectric layer 6 covering the bottom of the gate trench 5, so that the gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5, and at the same time, a part or all of the first dielectric layer 6 at the bottom of the gate trench 5 can be retained. In the present embodiment, the first dielectric layer 6 covering the first sidewall 19 and having the same depth as the second dielectric layer 7 is removed, i.e., the first dielectric layer 6 between the first sidewall 19 and the second dielectric layer 7 is removed, so that an empty region is formed in the region, and all the first dielectric layer 6 at the bottom of the gate trench 5 is remained. In this embodiment, the above-mentioned process of removing part of the first dielectric layer 6 can be specifically implemented as follows: coating a photoresist 17 on the surface of the SiC epitaxial layer 2, and performing patterning processing on the photoresist 17 by adopting a photoetching process to form a patterned photoresist 17; according to the patterned photoresist 17, a wet etching back process is used to remove a part of the first dielectric layer 6 covering the first sidewall 19, and at least the first dielectric layer 6 covering the bottom of the gate trench 5 is remained (as shown in fig. 12). It should be noted that the silicon nitride (the second dielectric layer 7) can prevent the removal of the first dielectric layer 6 covering the second sidewall 20 when the above-mentioned portion of the first dielectric layer 6 covering the first sidewall 19 is removed.
In this embodiment, the step S8 of filling the filler between the gate oxide layer 9 and the second dielectric layer 7 to form the gate 8 may specifically refer to: depositing polysilicon doped with phosphorus, wherein the implantation dosage can be 1E20 atomic number per square centimeter, forming a polysilicon gate in the region between the gate oxide layer 9 and the second dielectric layer 7, and removing the polysilicon on the surface of the SiC epitaxial layer 2.
Through the process, the first dielectric layer 6 and the second dielectric layer 7 which are left in the gate trench 5 can form a thick oxide layer for protecting the gate oxide layer 9, so that the electric field at the bottom of the gate trench 5 is reduced, the distribution of the electric field at the bottom of the gate trench 5 in a reverse cut-off state is optimized, and the reliability of a device is improved; moreover, the thick oxide layers (the remaining first dielectric layer 6 and the second dielectric layer 7) at the bottom and the side wall of the gate trench 5 can greatly reduce gate charges and optimize the switching characteristics of the device.
In the method for manufacturing the trench type SiC MOSFET device provided in this embodiment, a SiC epitaxial layer 2 is grown on a SiC substrate 1; forming a body region 3 on the SiC epitaxial layer 2; performing source injection on the body region 3 to form a source electrode 4; forming a gate trench 5 in the body region 3 by etching, wherein the bottom of the gate trench 5 is positioned in a drift region of the SiC epitaxial layer 2, and a first side wall 19 of the gate trench 5 penetrates through the source 4 or is in contact with the source 4; depositing to form a first dielectric layer 6 and a second dielectric layer 7, wherein the first dielectric layer 6 covers the first side wall 19, the second side wall 20 and the bottom of the gate trench 5, and the second dielectric layer 7 is filled in a hollow area between the first side wall 19 and the second side wall 20 of the gate trench 5; removing part of the first dielectric layer 6 covering the first side wall 19, and at least reserving the first dielectric layer 6 covering the bottom of the gate trench 5 to form a vacant area; growing a gate oxide layer 9 on the surface of the first side wall 19 exposed out of the vacant area; and filling filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8. The method comprises the steps of forming a first dielectric layer 6 and a second dielectric layer 7 in a gate trench 5 through deposition, growing a gate oxide layer 9 on the surface of a first side wall 19 exposed out of a vacant region after removing part of the first dielectric layer 6 covering the first side wall 19 and at least reserving the first dielectric layer 6 covering the bottom of the gate trench 5 to form the vacant region, and filling filler between the gate oxide layer 9 and the second dielectric layer 7 to form a gate 8; by the filling mode of the gate trench 5, the first dielectric layer 6 and the second dielectric layer 7 which are left in the gate trench can form a thick oxide layer for protecting the gate oxide layer 9, so that the electric field at the bottom of the gate trench 5 is reduced, the distribution of the electric field at the bottom of the gate trench 5 in a reverse cut-off state is optimized, and the reliability of a device is improved; in addition, the thick oxide layers (the first dielectric layer 6 and the second dielectric layer 7 remaining in the gate trench) at the bottom and the side wall of the gate trench 5 can greatly reduce gate charges and optimize the switching characteristics of the device. Furthermore, the filling mode of the gate trench 5 does not need to precisely control the depth of the body region 3 and strictly control the position of the gate 8 in the gate trench 5, so that the manufacturing process is simple, the requirements on equipment and machines are low, and the manufacturability is high.
Another embodiment of the present application provides a trench type SiC MOSFET device structure, which is manufactured by the trench type SiC MOSFET device manufacturing method provided in the above embodiment, and as shown in fig. 2, the trench type SiC MOSFET device structure includes:
an SiC epitaxial layer 2 on the SiC substrate 1;
a body region 3 located in the SiC epitaxial layer 2;
a source 4 located in the body region 3;
a gate trench 5 located in the body region 3, wherein the bottom of the gate trench 5 is located in a drift region of the SiC epitaxial layer 2, and a first sidewall 19 of the gate trench 5 penetrates through the source 4 or is in contact with the source 4;
a gate oxide layer 9 grown on said first sidewall 19 of said gate trench 5;
the first dielectric layer 6 covers the bottom of the gate trench 5 and the surface of the second side wall 20;
a second dielectric layer 7 filled in the gate trench 5 and contacting the first dielectric layer 6;
and the grid electrode 8 is filled in the grid groove 5 and is positioned between the grid oxide layer 9 and the second dielectric layer 7.
In this embodiment, the trench SiC MOSFET device structure further includes: a P + region 10 formed by injecting P + into the body region 3; a source ohmic contact layer formed on the surface of the source 4 and the corresponding position of the P + region 10; a contact hole 12 formed on the surface of the source ohmic contact layer, and a source electrode 13 filled in the contact hole 12.
In the trench SiC MOSFET device structure provided in this embodiment, the gate oxide layer 9 is grown on the first sidewall 19 of the gate trench 5; the first dielectric layer 6 covers the bottom of the gate trench 5 and the surface of the second sidewall 20; the second dielectric layer 7 is filled in the gate trench 5 and is in contact with the first dielectric layer 6; the gate 8 is filled in the gate trench 5 and located between the gate oxide layer 9 and the second dielectric layer 7. According to the gate trench filling mode, the first dielectric layer 6 and the second dielectric layer 7 in the gate trench form a thick oxide layer for protecting the gate oxide layer 9, so that the electric field at the bottom of the gate trench 5 is reduced, the distribution of the electric field at the bottom of the gate trench 5 in a reverse cut-off state is optimized, and the reliability of a device is improved; moreover, the thick oxide layers (the first dielectric layer 6 and the second dielectric layer 7) at the bottom and the side wall of the gate trench 5 can greatly reduce gate charges and optimize the switching characteristics of the device.
It should be noted that in the examples and description of this patent, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
Although the present application has been described with reference to the preferred embodiments, it is not intended to limit the present application, and those skilled in the art can make variations and modifications without departing from the spirit and scope of the present application, therefore, the scope of the present application should be determined by the claims that follow.
Claims (10)
1. A manufacturing method of a groove type SiC MOSFET device is characterized by comprising the following steps:
forming a SiC epitaxial layer on a SiC substrate;
forming a body region on the SiC epitaxial layer;
performing source injection on the body region to form a source electrode;
forming a gate trench in the body region by etching, wherein the bottom of the gate trench is positioned in a drift region of the SiC epitaxial layer, and a first side wall of the gate trench penetrates through the source electrode or is in contact with the source electrode;
depositing to form a first dielectric layer and a second dielectric layer, wherein the first dielectric layer covers the first side wall, the second side wall and the bottom of the gate trench, and the second dielectric layer is filled in a hollow area between the first side wall and the second side wall of the gate trench;
removing part of the first dielectric layer covering the first side wall, and at least reserving part of the first dielectric layer covering the bottom of the gate trench to form a vacant region;
growing a gate oxide layer on the surface of the first side wall exposed out of the vacant area;
and filling filler between the gate oxide layer and the second dielectric layer to form a gate.
2. The method of claim 1, wherein after source implanting the body region and before forming a gate trench in the body region by etching, the method further comprises: performing P + injection on the body region to form a P + region;
after filling polysilicon between the gate oxide layer and the second dielectric layer, the method further comprises: and forming Nisalicide on the surfaces of the source electrode and the corresponding position of the P + region to obtain a source electrode ohmic contact layer.
3. The method of claim 2, further comprising:
forming a contact hole on the surface of the source ohmic contact layer;
and filling metal in the contact hole to form a source electrode.
4. The method of claim 1, wherein the depositing forms a first dielectric layer and a second dielectric layer, comprising:
depositing silicon oxide to enable the silicon oxide to cover the surface of the SiC epitaxial layer and the side wall and the bottom of the gate groove;
depositing silicon nitride on the upper surface of the silicon oxide so that the silicon nitride is filled in the remaining area of the gate trench;
and removing the silicon nitride and the silicon oxide in the region outside the gate trench, and reserving the silicon nitride and the silicon oxide in the gate trench, wherein the silicon oxide in the gate trench forms the first dielectric layer, and the silicon nitride in the gate trench forms the second dielectric layer.
5. The method of claim 4, wherein the removing the silicon nitride and the silicon oxide outside the gate trench comprises:
removing the silicon nitride on the top in a CMP or dry back etching mode, and removing the silicon nitride higher than the SiC epitaxial layer in the gate trench;
and removing the silicon oxide higher than the SiC epitaxial layer by adopting a CMP mode.
6. The method of claim 1, wherein removing the portion of the first dielectric layer covering the first sidewall and leaving at least the first dielectric layer covering the bottom of the gate trench comprises:
coating photoresist on the surface of the SiC epitaxial layer, and carrying out patterning treatment on the photoresist by adopting a photoetching process to form patterned photoresist;
and removing part of the first dielectric layer covering the first side wall by adopting a wet back etching process according to the patterned photoresist, and at least reserving the first dielectric layer covering the bottom of the gate trench.
7. The method of claim 1 or 6, wherein the removing part of the first dielectric layer covering the first sidewall and at least remaining the first dielectric layer covering the bottom of the gate trench comprises:
and removing the first dielectric layer which covers the first side wall and has the same depth as the second dielectric layer.
8. The method of claim 1, wherein filling a filler between the gate oxide layer and the second dielectric layer to form a gate electrode comprises:
and depositing polycrystalline silicon, forming a polycrystalline silicon gate in a region between the gate oxide layer and the second dielectric layer, and removing the polycrystalline silicon on the surface of the SiC epitaxial layer.
9. A trench type SiC MOSFET device structure, comprising:
a SiC epitaxial layer on the SiC substrate;
a body region located in the SiC epitaxial layer;
a source located in the body region;
the gate trench is positioned in the body region, the bottom of the gate trench is positioned in a drift region of the SiC epitaxial layer, and a first side wall of the gate trench penetrates through the source electrode or is in contact with the source electrode;
a gate oxide layer grown on the first side wall of the gate trench;
the first dielectric layer covers the bottom of the gate groove and the surface of the second side wall;
the second dielectric layer is filled in the gate trench and is in contact with the first dielectric layer;
and the grid electrode is filled in the grid groove and positioned between the grid oxide layer and the second dielectric layer.
10. The trench SiC MOSFET device structure of claim 9, further comprising:
a P + region formed after P + implantation is carried out on the body region;
a source ohmic contact layer formed on the surface of the source and the corresponding position of the P + region;
the contact hole is formed on the surface of the source ohmic contact layer, and the source metal is filled in the contact hole.
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