CN111430453A - RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof - Google Patents
RC-IGBT chip with good reverse recovery characteristic and manufacturing method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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Abstract
The invention relates to an RC-IGBT chip with good reverse recovery characteristics, wherein a second P-type base region which forms ohmic contact with an emitter electrode is arranged between adjacent emitter trench regions in an FRD region of the RC-IGBT chip, P-type Schottky junction regions which form Schottky contact with the emitter electrode are arranged on two sides of the second P-type base region, the depth of the second P-type base region is greater than that of the P-type Schottky junction regions, the doping concentration of the P-type Schottky junction regions is lower than that of the second P-type base region, and the doping concentration of the first P-type base region is equal to that of the second P-type base region. The RC-IGBT chip with good reverse recovery characteristics has smaller reverse recovery current, and in addition, the invention also relates to a manufacturing method of the RC-IGBT chip.
Description
Technical Field
The invention relates to an IGBT chip, in particular to an RC-IGBT chip with good reverse recovery characteristic. The invention also relates to a manufacturing method of the RC-IGBT chip.
Background
The RC-IGBT is a semiconductor chip integrating a free-wheeling diode FRD inside an IGBT device. In the existing RC-IGBT chip, the excess carriers at the PN junction in the FRD region are more, so that the reverse recovery current is larger, and the reverse recovery characteristic of the diode is worse.
Disclosure of Invention
In order to solve the above technical problems, an object of the present invention is to provide an RC-IGBT chip with good reverse recovery characteristics and a method for manufacturing the same, in which the reverse recovery current is low.
The RC-IGBT chip with good reverse recovery characteristics comprises an IGBT region and an FRD region, wherein the IGBT region and the FRD region respectively comprise an N-type drift region formed by a semiconductor substrate, an N-type field termination region positioned on the back of the N-type drift region and a collector positioned below the N-type field termination region, a P-type collector region is arranged between the N-type field termination region and the collector in the IGBT region, an N-type region is arranged between the N-type field termination region and the collector in the FRD region, an accumulation region is arranged on the surface of the N-type drift region in the IGBT region, a plurality of gate groove regions and virtual groove regions are further arranged in the IGBT region, the bottom ends of the gate groove regions are positioned in the N-type drift region, a plurality of emission groove regions with the bottom ends positioned in the N-type drift region are arranged in the FRD region, an insulating film positioned on the surface of the gate groove regions and a gate electrode positioned above the insulating film are arranged in the gate groove regions, and a virtual, the emitting trench region is internally provided with an insulating film positioned on the surface of the emitting trench region and an emitting gate electrode above the insulating film, insulating medium layers positioned on the surface of a semiconductor substrate are arranged above the gate electrode, a virtual gate electrode and the emitting gate electrode, a first P-type base region positioned above an accumulation region is arranged in the IGBT region, an N + emitting region is arranged on the surface of the first P-type base region, a contact region positioned below the N + emitting region is further arranged in the first P-type base region, an emitting electrode electrically connected with the contact region is arranged on the surface of the IGBT region, a gate metal layer connected with the gate electrode is further arranged on the surface of the IGBT region, and the virtual gate electrode in the IGBT region is electrically connected with the emitting electrode, and: a second P-type base region in ohmic contact with the emitter electrode is arranged between adjacent emitter trench regions in the FRD region, P-type Schottky junction regions in Schottky contact with the emitter electrode are arranged on two sides of the second P-type base region, the depth of the second P-type base region is larger than that of the P-type Schottky junction regions, the doping concentration of the P-type Schottky junction regions is lower than that of the second P-type base region, and the doping concentration of the first P-type base region is equal to that of the second P-type base region.
By the scheme, the RC-IGBT chip with good reverse recovery characteristics is formed by respectively implanting different ions into the P-type Schottky junction region of the FRD region and the second P-type base region of the FRD region by using different masks; the doping concentration of the P-type Schottky junction region of the FRD region is lower than that of the second P-type base region of the FRD region; under the condition of ensuring the voltage resistance of the diode, the P-type Schottky junction region of the FRD region can adopt lower doping concentration, and the shallow P-type Schottky junction is favorable for increasing potential barrier, reducing the reverse recovery current and reverse recovery loss of the diode, improving the reverse recovery characteristic of the diode and enhancing the robustness of the device;
a manufacturing method of the RC-IGBT chip uses a mask for ion implantation only on the middle part of the FRD region and the IGBT region, so that a first P-type base region in the IGBT region and a second P-type base region in the FRD region are formed.
Furthermore, according to the manufacturing method of the RC-IGBT chip, the first P-type base region and the second P-type base region are subjected to boron ion implantation, and the concentration of the implanted boron ions is 2E13-3E13cm-2The implantation energy is 80-120 Kev.
Furthermore, the manufacturing method of the RC-IGBT chip of the invention utilizes the mask which does not perform ion implantation in the IGBT region but only performs ion implantation in the P-type Schottky junction region in the FRD region to perform ion implantation, thereby forming a shallow P-type Schottky junction region in the FRD region.
Furthermore, the method for manufacturing the RC-IGBT chip carries out boron ion implantation on the P-type Schottky junction region, and the concentration of the implanted boron ions is 1E12-1E13cm-2The implantation energy is 60-80 Kev.
By means of the scheme, the manufacturing method of the RC-IGBT chip carries out ion implantation on the P-type Schottky junction region and the second P-type base region through different masks respectively, so that a shallow P-type Schottky junction region and a deeper second P-type base region are formed, and reverse recovery current of the RC-IGBT chip is small.
The foregoing description is only an overview of the technical solutions of the present invention, and in order to make the technical solutions of the present invention more clearly understood and to implement them in accordance with the contents of the description, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Drawings
FIG. 1 is a schematic diagram of the front structure of the RC-IGBT chip of the invention;
fig. 2 is a cross-sectional view of an IGBT region;
fig. 3 is a sectional view of the FRD region.
Detailed Description
The following detailed description of embodiments of the present invention is provided in connection with the accompanying drawings and examples. The following examples are intended to illustrate the invention but are not intended to limit the scope of the invention.
Referring to fig. 1 to 3, the RC-IGBT chip with good reverse recovery characteristics according to the present invention includes an IGBT region and an FRD region, both the IGBT region and the FRD region include an N-type drift region formed by a semiconductor substrate 100, an N-type field stop region 210 located on the back of the N-type drift region, and a collector 5 located below the N-type field stop region, a P-type collector region 220 is disposed between the N-type field stop region and the collector in the IGBT region, an N-type collector region 230 is disposed between the N-type field stop region and the collector in the FRD region, an accumulation region 11 is disposed on the surface of the N-type drift region in the IGBT region, a plurality of gate trench regions 12 and a dummy trench region 32 having bottom ends located in the N-type drift region are further disposed in the IGBT region, a plurality of emitter trench regions 22 having bottom ends located in the N-type drift region are disposed in the FRD region, an insulating film 13 located on the surface of the gate trench regions and a gate electrode 14 located above the insulating film are disposed in the gate trench region, an insulating film 33 and, be equipped with the emitter gate electrode 24 that is located the insulating film 23 and the insulating film top on emitter trench district surface in the emitter trench district, the gate electrode, the top of virtual gate electrode and emitter gate electrode all is equipped with the insulating medium layer 17 that is located the semiconductor substrate surface, be equipped with the first P type base region 15 that is located accumulation district top in the IGBT district, the surface of first P type base region is equipped with N + emitter region 16, and still be equipped with the contact region 19 that is located N + emitter region below in the first P type base region, IGBT district surface is equipped with the emitter electrode 3 of being connected with contact region 19 electricity, the surface in IGBT district still is provided with the grid metal layer of being connected with the gate electrode, virtual gate electrode and the emitter electrode electricity in the IGBT district are connected: a second P-type base region 25 which forms ohmic contact with the emitter electrode 3 is arranged between the adjacent emitter groove regions 22 in the FRD region, P-type Schottky junction regions 26 which form Schottky contact with the emitter electrode are arranged on two sides of the second P-type base region, the depth of the second P-type base region is larger than that of the P-type Schottky junction regions, the doping concentration of the P-type Schottky junction regions is lower than that of the second P-type base region, and the doping concentration of the first P-type base region is equal to that of the second P-type base region.
The specific manufacturing method of the RC-IGBT chip of the invention is described as follows:
(1) taking an N-type RC-IGBT device as an example, an N-type single crystal silicon material or an N-type epitaxial silicon material is adopted as a semiconductor substrate material and serves as a drift region of the RC-IGBT device.
(2) Neglecting the forming process of the terminal region, a cellular structure of the RC-IGBT device is formed in the active region.
(3) An accumulation region 11 is formed in the device active region of the semiconductor substrate 100 by ion implantation and high-temperature drive-in. The accumulation region 11 is formed only in the IGBT region, and the accumulation region is not formed in the FRD region.
(4) The gate trench region 12, the emitter trench region 22, and the dummy trench region 32 are formed in the surface of the semiconductor substrate 100 by photolithography and reactive ion etching. The IGBT region is provided with a gate groove region 12 and a virtual groove region 32, and the gate groove region 12 and the virtual groove region 32 can be formed according to a certain proportion of 1: n is set. An emission trench region 22 is formed in the FRD region. The groove regions may be arranged at equal intervals or at unequal intervals. Specifically, the semiconductor substrate 100 is grown on the surface with a thickness of
The silicon dioxide barrier layer is used as a barrier layer for etching the groove; etching the silicon dioxide barrier layer by using the photoetching mask to form a silicon dioxide barrier layer pattern; then removing the photoresist; etching the silicon substrate by using the silicon dioxide barrier layer pattern as a mask, namely deeply digging a plurality of grooves to form a gate groove region 12, an emission groove region 22 and a virtual groove region 32; and removing the residual silicon dioxide barrier layer by wet etching. Wherein, the depth of the groove is 3-7um, and the cross section width is 0.8-1.5 um.
(5) Growing a layer of compact on the inner wall of each groove regionAnd higher-performance insulating films 13, 23, and 33. Specifically, a sacrificial oxide layer is grown on the inner wall of each groove area through high-temperature oxidation, and then the sacrificial oxide layer is corroded by a wet method, so that the insulating film is smooth and flat; and growing an insulating film on the inner wall of each groove region through high-temperature oxidation. Wherein the thickness of the insulating film is
The operation steps are to reduce crystal defects and impurities, so that an insulating film with better compactness is grown to be used as a gate oxide film of an MOS structure;
(6) a layer of polysilicon is deposited on the surface of the semiconductor substrate 100 and doped to form N-type polysilicon. Specifically, polysilicon is deposited on the surface of the semiconductor substrate 100 by a high-temperature furnace tube and is subjected to in-situ doping to form N-type polysilicon, the thickness of the polysilicon is 0.5-2um, and the concentration of the polysilicon is 1E20cm-3(ii) a And then activating the polysilicon at high temperature of 950 ℃ for 30 minutes.
(7) And performing reactive ion etching on the polycrystalline silicon on the surface of the semiconductor substrate 100, wherein the etching thickness is 0.5-2um, and only the polycrystalline silicon in each groove area, on the PAD (PAD for grid electrode) and the BUS (BUS for grid electrode) channel is reserved. Thereby forming gate electrode 14, dummy gate electrode 34, and emitter gate electrode 24. Wherein the gate electrode 14 is formed in the gate trench region 12, the dummy gate electrode 34 is formed in the dummy trench region 32, and the emitter gate electrode 24 is formed in the emitter trench region 22.
(8) Ion implantation is performed in the entire surface of the gap between the gate trench region 12 and the dummy trench region 32, and in the middle of the gap of the emitter trench region 22. Specifically, a mask for ion implantation of the FRD region middle portion and the IGBT region is used, thereby forming the first P-type base region 15 in the IGBT region and the second P-type base region 25 in the FRD region. Wherein the concentration of the implanted boron ions is 2E13-3E13cm-2The implantation energy is 80-120 Kev.
(9) Performing high-temperature well pushing for a long time to form a first P-type base region 15 and a second P-type base region 25;
(10) ion implantation is performed in the gap at both ends of the emitter trench region 22. Specifically, the use is not performed in the IGBT regionIon implantation is performed only for the mask of ion implantation of the P-type schottky junction region in the FRD region, thereby forming the P-type schottky junction region 26 in the FRD region. Wherein the concentration of the implanted boron ions is 1E12-1E13cm-2The implantation energy is 60-80 Kev. The P-type Schottky junction region of the FRD region and the second P-type base region of the FRD region are formed by using different masks and respectively injecting different ions; the doping concentration of the P-type Schottky junction region of the FRD region is lower than that of the second P-type base region of the FRD region; under the condition of ensuring the voltage resistance of the diode, the P-type Schottky junction region of the FRD region can adopt lower doping concentration, and the shallow P-type Schottky junction is favorable for increasing potential barrier, reducing the reverse recovery current and reverse recovery loss of the diode, improving the reverse recovery characteristic of the diode and enhancing the robustness of the device;
(11) performing high-temperature drive-in for a short time to form a P-type Schottky junction region 26 of the FRD region; the junction depth of the P-type schottky junction region 26 is much smaller than the second P-type base region 25 due to the shorter well pull-in time.
(12) An N + emitter region 16 is formed on the upper surface of the P-type base region 15 in the IGBT region through ion implantation and high-temperature drive-in. Specifically, an implantation window of an N + emission region is formed by using a photolithographic mask, using a mask for not performing ion implantation in the FRD region but only performing ion implantation in the IGBT region; and injecting high-energy arsenic ions into the injection window of the N + emitter region and carrying out high-temperature well pushing, so that an N + emitter region 16 is formed on the upper surface of the P-type base region in the IGBT region. Wherein the implantation dosage of arsenic ion is 1E15-8E15cm-2The implantation energy is 80-120 Kev.
(13) An insulating dielectric layer 17 is deposited on the surface of the semiconductor substrate and reflowed to be planarized. The thickness of the insulating medium layer is 1-1.5 um; the insulating medium layer can be formed by stacking a plurality of layers of insulating media;
(14) the insulating dielectric layer 17 is etched in the IGBT region and the semiconductor substrate is etched down, forming contact trenches 18. Specifically, a mask which is not used for etching the FRD region but is only used for etching the IGBT region is used for etching the insulating medium layer 17 on the surface of the N + emission region 16 in the IGBT region to form a contact window and etching the semiconductor substrate downwards to form a contact groove 18 with the downward depth of 0.3-0.5 um; contact trenches 18 are located in the gaps between each trench region.
(15) Boron ions are implanted multiple times into the N + emitter region through the contact trench 18 to form a P + highly doped region, i.e., a contact region 19. The P + contact region of the IGBT region is formed by a plurality of boron ion injection processes, the thickness of the P + contact region is thicker when the number of boron ion injection is larger, and a hole is easier to be extracted when the device is turned off, so that latch-up is inhibited;
(16) the insulating dielectric layer 17 is etched in the FRD region to form contact trenches 28. Specifically, a mask which is not used for etching the IGBT area but is only used for etching the FRD area is used for etching the insulating medium layer 17 on the surface of the FRD area to form the contact groove 28, at the moment, the lower part of the contact groove 28 of the FRD area is in the same level with the surface of the semiconductor substrate, namely, the contact groove 28 of the FRD area does not extend into the semiconductor substrate, the semiconductor substrate is not etched downwards in the FRD area to form a shallow groove, hole injection is reduced, and the reverse recovery performance of the diode is improved.
(17) And depositing emitter metal on the surface of the device and forming an emitter electrode 3 and a gate metal layer 4 by etching. Specifically, a metal film with the thickness of 1-5um is deposited on the surface of the device; then forming an emitter electrode 3 and a gate metal layer 4 by etching; the emitter electrode 3 and the gate metal layer 4 are isolated from each other by an insulating dielectric layer 17. The metal is aluminum/silicon alloy or aluminum/silicon/copper alloy or other materials, the thickness is 1-5um, and the high-doped silicon and the metal form ohmic contact through heating alloying, so that the contact resistance is reduced. And P-type Schottky contact is formed between the shallow P-type silicon and the metal, so that the potential barrier is increased, the hole injection is reduced, and the reverse recovery current of the diode is reduced.
(18) And after the front metallization of the power device is completed, turning over the chip and thinning the back.
(19) Forming an N-type field stop region 210 on the back surface of the semiconductor substrate by phosphorus ion implantation and a high-temperature drive-in process; the doping concentration of the N-type field stop region 210 is 1E15-1E17 cm-3The junction depth is 1-3um, so that the compromise characteristic of the IGBT can be improved, and the current trailing time when the IGBT is turned off is reduced.
(20) Forming a back P-type collector region 220 on the back side of the semiconductor substrate by boron ion implantation and a high-temperature drive-in process; wherein the doping concentration of the P-type collector region 220 is 1E18-5E19 cm-3The junction depth is 0.5-1um, so as to control the hole emission efficiency. The P-type collector region 220 is formed only in the IGBT region.
(21) A back N-type collector region 230 is formed on the back surface of the semiconductor substrate by phosphorus ion implantation and a high-temperature drive-in process. The N-type collector region 230 is formed only in the FRD region.
(22) And carrying out back metallization on the RC-IGBT device to form a back collector 5.
The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, it should be noted that, for those skilled in the art, many modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.
Claims (5)
1. An RC-IGBT chip with good reverse recovery characteristics comprises an IGBT region and an FRD region, wherein the IGBT region and the FRD region respectively comprise an N-type drift region formed by a semiconductor substrate (100), an N-type field termination region (210) positioned on the back of the N-type drift region and a collector (5) positioned below the N-type field termination region, a P-type collector region (220) is arranged between the N-type field termination region and the collector in the IGBT region, an N-type collector region (230) is arranged between the N-type field termination region and the collector in the FRD region, an accumulation region (11) is arranged on the surface of the N-type drift region in the IGBT region, a plurality of gate groove regions (12) and a virtual groove region (32) with bottom ends positioned in the N-type drift region are further arranged in the IGBT region, a plurality of emission groove regions (22) with bottom ends positioned in the N-type drift region are arranged in the FRD region, an insulating film (13) positioned on the surface of the gate groove regions and a gate electrode, an insulating film (33) positioned on the surface of the virtual groove region and a virtual gate electrode (34) positioned above the insulating film are arranged in the virtual groove region, an insulating film (23) positioned on the surface of the emitting groove region and an emitting gate electrode (24) positioned above the insulating film are arranged in the emitting groove region, insulating medium layers (17) positioned on the surface of the semiconductor substrate are arranged above the gate electrode, the virtual gate electrode and the emitting gate electrode, a first P-type base region (15) positioned above the accumulation region is arranged in the IGBT region, an N + emitting region (16) is arranged on the surface of the first P-type base region, a contact region (19) positioned below the N + emitting region is further arranged in the first P-type base region, an emitting electrode (3) electrically connected with the contact region (19) is arranged on the surface of the IGBT region, a gate metal layer connected with the gate electrode is further arranged on the surface, the method is characterized in that: a second P-type base region (25) which forms ohmic contact with the emitter electrode (3) is arranged between adjacent emitter trench regions (22) in the FRD region, P-type Schottky junction regions (26) which form Schottky contact with the emitter electrode are arranged on two sides of the second P-type base region, the depth of the second P-type base region is larger than that of the P-type Schottky junction regions, the doping concentration of the P-type Schottky junction regions is lower than that of the second P-type base region, and the doping concentration of the first P-type base region is equal to that of the second P-type base region.
2. A method for manufacturing the RC-IGBT chip according to claim 2, characterized in that: and forming a first P-type base region (15) in the IGBT region and a second P-type base region (25) in the FRD region by using a mask for ion implantation of only the middle part of the FRD region and the IGBT region.
3. The method of manufacturing an RC-IGBT chip according to claim 2, characterized in that: boron ion implantation is carried out on the first P-type base region and the second P-type base region, and the concentration of the implanted boron ions is 2E13-3E13cm-2The implantation energy is 80-120 Kev.
4. The method of manufacturing an RC-IGBT chip according to claim 3, characterized in that: and performing ion implantation by using a mask which is not used for performing ion implantation in the IGBT region but only used for performing ion implantation in the P-type Schottky junction region in the FRD region, thereby forming a shallow P-type Schottky junction region (26) in the FRD region.
5. The method of manufacturing an RC-IGBT chip according to claim 4, wherein: for P type Schottky junctionThe region is implanted with boron ions at a concentration of 1E12-1E13cm-2The implantation energy is 60-80 Kev.
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| CN112018174A (en) * | 2020-08-19 | 2020-12-01 | 广东美的白色家电技术创新中心有限公司 | Semiconductor device, manufacturing method thereof and household appliance |
| CN114464676A (en) * | 2022-01-25 | 2022-05-10 | 上海擎茂微电子科技有限公司 | Reverse conducting IGBT |
| CN114899147A (en) * | 2022-07-12 | 2022-08-12 | 深圳芯能半导体技术有限公司 | RC-IGBT device and preparation method thereof |
| CN115832039A (en) * | 2022-12-09 | 2023-03-21 | 宁波达新半导体有限公司 | Reverse conducting IGBT device |
| CN116190420A (en) * | 2023-02-24 | 2023-05-30 | 上海林众电子科技有限公司 | Fast recovery diode structure and preparation method thereof |
| TWI836801B (en) * | 2022-03-28 | 2024-03-21 | 日商日立功率半導體股份有限公司 | Semiconductor device, manufacturing method of semiconductor device, and power conversion device |
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| CN116190420A (en) * | 2023-02-24 | 2023-05-30 | 上海林众电子科技有限公司 | Fast recovery diode structure and preparation method thereof |
| CN116190420B (en) * | 2023-02-24 | 2024-03-26 | 上海林众电子科技有限公司 | Fast recovery diode structure and preparation method thereof |
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