CN108598153B - Soft recovery power semiconductor diode and preparation method thereof - Google Patents
Soft recovery power semiconductor diode and preparation method thereof Download PDFInfo
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- CN108598153B CN108598153B CN201810696368.4A CN201810696368A CN108598153B CN 108598153 B CN108598153 B CN 108598153B CN 201810696368 A CN201810696368 A CN 201810696368A CN 108598153 B CN108598153 B CN 108598153B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 350
- 238000011084 recovery Methods 0.000 title claims abstract description 75
- 238000002360 preparation method Methods 0.000 title abstract description 12
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
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Abstract
The invention provides a soft recovery power semiconductor diode and a preparation method thereof, wherein the diode comprises the following components: an active region and a termination region; the active region includes: the semiconductor device comprises a first semiconductor layer, a second semiconductor layer, a first semiconductor region and a first electrode. The first semiconductor layer is provided with a first conductive type and is formed in a first region of the drift layer; a second semiconductor layer having a second conductivity type formed in the first region of the drift layer; a first semiconductor region having the second conductivity type and formed through the first semiconductor layer and the second semiconductor layer; the concentration of the doped charge in the first semiconductor region is similar to the concentration of the doped charge in the first semiconductor layer. The invention has the advantages of reducing forward conduction voltage drop of the diode, improving breakdown voltage and the like while ensuring the soft recovery characteristic of the diode.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a soft recovery power semiconductor diode and a preparation method thereof.
Background
Semiconductor diodes, which have forward conduction and reverse blocking characteristics, are widely used in applications such as inverter welders, automotive electronics, motor drive systems, and other energy conversion devices. Their unidirectional conductivity can play a different role in various circuits, the most widely used of which is for freewheeling in shutdown circuits. For turning off freewheeling of a power device such as an IGBT (insulated gate bipolar transistor), a diode with soft recovery characteristics is required to avoid oscillation in a loop caused by hard turning off, resulting in damage to the power device.
Diodes having soft recovery characteristics can be generally classified into schottky structures and PIN structures according to the operating principle. The simple Schottky diode has the advantages of small conduction voltage drop and quick reverse recovery time because of being a multi-sub device, but has the defects of low breakdown voltage, high-temperature leakage, low avalanche resistance and the like. Novel fast recovery diodes combining schottky and PIN structures have been proposed at home and abroad, such as junction barrier control rectifier JBS (JBS: junction Barrier Controlled Schottky Rectifier), hybrid PIN/schottky rectifier MPS (MPS: mered P-i-N/Schottky Rectifier), and the like, and have the characteristics of low forward voltage drop, short reverse recovery time, low leakage current, and the like. However, since the schottky structure is included, the breakdown voltage still cannot reach more than 400V, and meanwhile, the high-temperature electric leakage is also larger, which makes the schottky structure not applicable to some high-voltage high-power supply systems.
The fast recovery PIN diode has the advantages of high breakdown voltage, high avalanche resistance, strong antistatic ability and small high-temperature leakage current, and is widely applied to high-voltage systems. The diode must undergo a reverse recovery process when transitioning from a forward biased state to a reverse biased state. In the forward biased state, the I-region of the PIN diode stores a very high concentration of minority carriers, which must be purged from the I-region in order to reduce the current to zero, which requires a reverse recovery time. In order to reduce the reverse recovery time, heavy metal doping techniques are mostly used to reduce minority carrier lifetime acquisition. However, the faster reverse recovery can generate a larger current rising rate, on one hand, the current can be caused to oscillate in the fast recovery process, the electromagnetic interference (EMI) problem is generated, and meanwhile, under the action of stray inductance, obvious voltage spikes are generated, and the reliability of a circuit is affected.
Disclosure of Invention
The invention provides a soft recovery power semiconductor diode and a preparation method thereof, which aim to achieve the effects of reducing forward conduction voltage drop of the diode, improving breakdown voltage and the like while ensuring the soft recovery characteristic of the diode.
The embodiment of the invention provides a soft recovery power semiconductor diode, which comprises the following components: an active region and a termination region; the active region includes: a first semiconductor layer having a first conductivity type and formed in a first region of the drift layer; the drift layer has the first conductivity type and is covered on the substrate with the first conductivity type; a second semiconductor layer having a second conductivity type formed in the first region of the drift layer and located on a side of the first semiconductor layer away from the substrate; the first conductivity type is different from the second conductivity type; at least one first semiconductor region having the second conductivity type and formed through the first semiconductor layer and the second semiconductor layer; the side of the first semiconductor region, which is close to the substrate, does not exceed the side of the first semiconductor layer, which is close to the substrate; in the case of a plurality of first semiconductor regions, a first spacing region is arranged between two adjacent first semiconductor regions; a first electrode disposed on a side of the second semiconductor layer and the first semiconductor region away from the substrate; wherein the concentration of the doped charge in the first semiconductor region is similar to the concentration of the doped charge in the first semiconductor layer.
In one embodiment, the soft-recovery power semiconductor diode further comprises: a second electrode which is arranged on one side of the substrate far from the drift layer; and a buffer layer which is arranged between the substrate and the drift layer in a covering manner and has the first conductivity type.
In one embodiment, the active region further comprises: a third semiconductor layer having the second conductivity type, formed in the first region of the drift layer, on a side of the second semiconductor layer away from the substrate, filled in the first spacer region and contacting the first semiconductor region; the third semiconductor layer has a concentration of doped charge greater than a concentration of doped charge of the second semiconductor layer, and the second semiconductor layer has a concentration of doped charge greater than a concentration of doped charge of the first semiconductor region.
In one embodiment, the terminal area includes: the combined structure of the field limiting ring and the field plate is arranged on one side, far away from the substrate, of the second region of the drift layer; the second region of the drift layer adjoins the first region of the drift layer.
In one embodiment, the combined structure of the field limiting ring and the field plate comprises: at least one second semiconductor region, a field oxide layer, and a second region of the polysilicon layer; the terminal area further includes: a second region of the oxide layer; the second semiconductor region is provided with the second conductivity type, is formed in the second region of the drift layer and is close to one side of the drift layer, which is far away from the substrate; in the case that the number of the second semiconductor regions is plural, a second interval region is provided between two adjacent second semiconductor regions; the field oxide layer is covered on the edge area of each second semiconductor area and each second interval area; a second region of the oxide layer covering an edge region of the field oxide layer and a portion of the second semiconductor region not covered by the field oxide layer; and the second region of the polysilicon layer is covered on the second region of the oxide layer.
In one embodiment, the active region further comprises: the first areas of the oxide layer are covered on the first semiconductor areas; the first region of the polysilicon layer is covered between the first region of the oxide layer and the first electrode; the ratio of the width of the polysilicon and the window in the polysilicon layer is in the range of 0.2 to 0.6.
In one embodiment, the ratio of the total amount of doped charges in the first semiconductor region to the total amount of doped charges in the first semiconductor layer ranges from 0.9 to 1.1.
In one embodiment, the first semiconductor region has a thickness in the range of 3 μm to 12 μm; and/or the thickness of the first semiconductor layer ranges from 1 μm to 4 μm; and/or the thickness of the second semiconductor layer ranges from 2 μm to 5 μm; and/or the thickness of the third semiconductor layer ranges from 0.2 μm to 1 μm.
In one embodiment, the first semiconductor region has a concentration of doping charges ranging from 8e13cm -3 ～4e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the first semiconductor layer has a concentration of doping charge in the range of 1e14cm -3 ～2e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the second semiconductor layer has a concentration of doping charge in the range of 3e15cm -3 ～3e17cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or the third semiconductor layer has a concentration of doping charges ranging from 1e18cm -3 ～1e20cm -3 。
The embodiment of the invention also provides a preparation method of the soft recovery power semiconductor diode, which comprises the following steps: forming a drift layer having a first conductivity type on a substrate having the first conductivity type by epitaxial growth; performing thermal oxidation on the drift layer to form an initial field oxide layer; photoetching and etching the initial field oxide layer based on a first preset pattern to form a field oxide layer containing at least one field oxide region; the at least one field oxide region is located in a second region of the drift layer; in the case of a plurality of field oxide regions, a spacing region is arranged between two adjacent field oxide regions; ion-implanting the drift layer with a dopant of a second conductivity type based on the field oxide layer including at least one field oxide region to form at least one second semiconductor region of the second conductivity type in a region of the second region of the drift layer not covered by the field oxide region, and to form an initial semiconductor layer of the second conductivity type in a first region of the drift layer; the second conductivity type is different from the first conductivity type; the first region of the drift layer is adjacent to the second region of the drift layer; depositing an oxide layer and a polysilicon layer on the initial semiconductor layer, the at least one field oxide region and the at least one second semiconductor region in sequence; photoetching and etching the oxide layer and the polysilicon layer based on a second preset pattern to form a first region provided with a first set window oxide layer and a first region of the polysilicon layer above the initial semiconductor layer, and forming a second region provided with a second set window oxide layer and a second region of the polysilicon layer above the second semiconductor region; the second setting window is positioned above the field oxidation region; ion implanting the initial semiconductor layer with a impurity having the first conductivity type, forming a second semiconductor layer having the second conductivity type at the first set window, and forming a first semiconductor layer having the first conductivity type under the second semiconductor layer, and forming a first semiconductor region from a portion of the initial semiconductor layer under a second region of the oxide layer; a lower surface of the first semiconductor region is not lower than a lower surface of the first semiconductor layer; the concentration of the doped charge in the first semiconductor region is similar to that of the doped charge in the first semiconductor layer; ion implanting the second semiconductor layer with a impurity having the second conductivity type, forming a third semiconductor layer having the second conductivity type in an upper region of the second semiconductor layer; depositing a metal on the third semiconductor layer and the first region of the polysilicon layer to form a second electrode; a metal is deposited on a lower surface of the substrate to form a first electrode.
According to the soft recovery power semiconductor diode and the preparation method thereof, the first semiconductor layer with the first conductivity type is arranged on one side of the second semiconductor layer with the second conductivity type, so that the injection efficiency of PN junctions in the diode can be reduced, the carrier concentration of a base region of the diode near the PN junctions can be kept at a lower level, the reverse recovery maximum current of the diode can be reduced, and the device is guaranteed to have soft recovery characteristics. And the first semiconductor region is penetrated in the first semiconductor layer and the second semiconductor layer, so that the surface of the first semiconductor region, which is close to the substrate, is not lower than the surface of the first semiconductor layer, which is close to the substrate, and the doped charge concentration of the first semiconductor region is similar to that of the first semiconductor layer, therefore, the carrier concentration of the N-region can be increased when the diode is conducted in the forward direction, the conduction voltage drop is reduced, the electric field distribution of the active region is balanced when the diode is blocked in the reverse direction, the leakage current is reduced, and the breakdown voltage is improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:
FIG. 1 is a schematic diagram of a soft-recovery power semiconductor diode according to an embodiment of the present invention;
FIG. 2 is a graph comparing reverse blocking BV simulation curves of a prior art diode and a diode of the present invention;
FIG. 3 is a graph comparing forward conduction simulation curves of a prior diode and a diode of the present invention;
FIG. 4 is a schematic flow chart of a method for manufacturing a soft recovery power semiconductor diode according to an embodiment of the invention;
FIGS. 5-11 are schematic diagrams illustrating a process for fabricating a soft-recovery power semiconductor diode according to an embodiment of the present invention;
FIG. 12 is a graph showing the forward conduction characteristics of a 600V soft fast recovery diode according to an embodiment of the present invention;
FIG. 13 is a reverse breakdown characteristic of a 600V soft fast recovery diode according to an embodiment of the present invention;
FIG. 14 is a reverse recovery curve of a 600V soft fast recovery diode according to an embodiment of the present invention;
fig. 15 is an avalanche test plot of a 600V soft fast recovery diode in accordance with an embodiment of the present invention.
Symbol description:
1 to a substrate;
2 to a buffer layer;
3 to a drift layer;
31 to a first region of the drift layer;
32 to a second region of the drift layer;
4 to a first semiconductor layer;
5 to a first semiconductor region;
5' to a second semiconductor region;
6 to a second semiconductor layer;
7 to a third semiconductor layer;
8-field oxide layer;
9 to a first region of the oxide layer;
a second region of 9' to a second oxide layer;
10-a first region of the polysilicon layer;
a second region of 10' to the polysilicon layer;
c1 to active region;
c2 to a terminal region;
111 to a first electrode;
112 to a second electrode;
ws to a first spacer region;
w9 to the second interval region.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the embodiments of the present invention will be described in further detail with reference to the accompanying drawings. The exemplary embodiments of the present invention and their descriptions herein are for the purpose of explaining the present invention, but are not to be construed as limiting the invention.
Fig. 1 is a schematic structural diagram of a soft recovery power semiconductor diode according to an embodiment of the present invention. Referring to fig. 1, the soft-recovery power semiconductor diode of some embodiments may include: an active region C1 and a termination region C2. The active region C1 may be used as a main portion of the forward conduction operation of the diode, and the termination region C2 may be used to boost the reverse withstand voltage of the device.
The active region C1 may include: a first semiconductor layer 4, a second semiconductor layer 6, at least one first semiconductor region 5 and a first electrode 111. The termination region C2 and the active region C1 may be formed by similar processes, and some of the constituent parts of the termination region C2 may have the same or similar structure as the corresponding parts of the active region C1, so that one skilled in the art may recognize one or more implementations of the termination region C2 by describing the active region C1 in combination with the function of the termination region C2.
Referring again to fig. 1, the soft-recovery power semiconductor diode further includes a substrate and a drift layer. The substrate may comprise a first region 11 of the substrate and a second region 12 of the substrate, and the drift layer may comprise a first region 31 of the drift layer and a second region 32 of the drift layer. The first semiconductor layer 4, the second semiconductor layer 6, the first semiconductor regions 5 and the first electrode 111 may be disposed over the first region 11 of the substrate and the first region 31 of the drift layer.
The first semiconductor layer 4 has a first conductivity type and is formed in the first region 31 of the drift layer; the drift layer has the first conductivity type and is covered on the substrate having the first conductivity type. The first conductivity type may be, for example, N-type or P-type. The first semiconductor layer 4 having the first conductivity type may be obtained by ion-implanting the drift layer with impurities of the first conductivity type. In order to obtain a first semiconductor layer 4 of said first conductivity type, the concentration of the doping charge may be in the range of 1e14cm, for example -3 ～2e16cm -3 . Further, the thickness of the first semiconductor layer 4 may be set according to the device requirements, for example, the thickness may range from 1 μm to 4 μm.
The first conductivity type of the substrate can be obtained by doping, for example, a silicon wafer with an impurity of the first conductivity type, for example, doping boron element can obtain P type, and doping, for example, phosphorus element can obtain N type. To obtain a substrate of the first conductivity type, the concentration of the doping charge is in a range such as May be 5e18cm -3 ～8e19cm -3 . Further, the thickness of the substrate may be set as desired, and for example, the thickness may range from 50 μm to 300 μm. The drift layer may be formed by epitaxial growth. The first conductivity type of the drift layer may be obtained by doping or ion implanting a deposited, e.g. silicon material with impurities of the first conductivity type. In order to obtain a drift layer of the first conductivity type, the concentration of the doping charge may be in the range of, for example, 4e13cm -3 ～1e15cm -3 . Further, the thickness of the drift layer may be set as desired, and for example, the thickness may range from 10 μm to 100 μm.
The second semiconductor layer 6 has the second conductivity type, is formed in the first region 31 of the drift layer, and is located on a side of the first semiconductor layer 4 remote from the substrate. The first semiconductor layer 4 having the first conductivity type may be obtained by ion implantation of the upper surface of the first semiconductor layer 4 with impurities of the second conductivity type. The concentration of the doping charge of the second semiconductor layer 6 may be in the range of 3e15cm -3 ～3e17cm -3 . Further, the thickness of the second semiconductor layer 6 may be set according to the device requirements, for example, the thickness may range from 2 μm to 5 μm. The first conductivity type is different from the second conductivity type, for example, when the first conductivity type is N-type, the second conductivity type may be P-type, and when the first conductivity type is P-type, the second conductivity type may be N-type.
The first semiconductor regions 5 have the second conductivity type and are formed through the first semiconductor layer 4 and the second semiconductor layer 6; the side of the first semiconductor region 5, which is close to the substrate, does not exceed the side of the first semiconductor layer 4, which is close to the substrate; in the case where the number of the first semiconductor regions 4 is plural, a first spacing region Ws is provided between two adjacent first semiconductor regions 5. The first semiconductor regions 5 having the second conductivity type may be obtained by ion implantation using impurities of the second conductivity type. The concentration of the doping charges in the first semiconductor regions 5 may be 8e13cm -3 ～4e16cm -3 . The thickness of the first semiconductor regions 5 may be set according to the device requirements, for example, in the range of 3 μm to 12 μm. The first spacing regions Ws of different adjacent two of the first semiconductor regions 5 may be the same or different.
By penetrating the first semiconductor region 5 to the first semiconductor layer 4 and the second semiconductor layer 6 such that the side of the first semiconductor region 5 near the substrate does not exceed (or is not lower than) the side of the first semiconductor layer 4 near the substrate, the materials of the first semiconductor layer 4 and the second semiconductor layer 6 can be made to surround the first semiconductor region 5. Then, the first semiconductor regions 5 may be alternately arranged with both the first semiconductor layers 4 and the second semiconductor layers 6 with the first spacing region Ws between two adjacent first semiconductor regions 5. In case of comprising only one first semiconductor region 5, both sides of the first semiconductor region 5 may be surrounded by a stacked structure of the first semiconductor layer 4 and the second semiconductor layer 6.
Wherein the concentration of the doped charges in the first semiconductor region 5 is similar to the concentration of the doped charges in the first semiconductor layer 4. "close" may for example mean that the concentration of the doping charge of the second conductivity type in the first semiconductor region 5 and the concentration of the doping charge of the first conductivity type in the first semiconductor layer 4 are of one order, and the doping charge concentration ratio may be in the range of more than 0.5 and less than 1.5. In other embodiments, the ratio of the total amount of the doped charges in the first semiconductor region 5 to the total amount of the doped charges in the first semiconductor layer 4 may be in the range of 0.9 to 1.1, in other words, the ratio of the total amount of the doped charges having the second conductivity type in the first semiconductor region 5 to the total amount of the doped charges having the first conductivity type in all the first semiconductor layers 4 may be in the range of 0.9 to 1.1.
A first electrode 111, the first electrode 111 being arranged on a side of the second semiconductor layer 6 and the first semiconductor region 5 remote from the substrate. The first electrode 111 may be an anode or a cathode, for example, when the first conductivity type is N-type, the first electrode 111 is an anode. The first electrode 111 may be formed by depositing a metal.
In this embodiment, by disposing the first semiconductor layer having the first conductivity type on the side of the second semiconductor layer having the second conductivity type, which is close to the substrate, injection efficiency of the PN junction in the diode can be reduced, so that the carrier concentration of the base region of the diode near the PN junction can be kept at a low level, the maximum current of reverse recovery of the diode can be reduced, and the device can be ensured to have soft recovery characteristics. And the first semiconductor region is penetrated in the first semiconductor layer and the second semiconductor layer, the side, close to the substrate, of the first semiconductor region does not exceed the side, close to the substrate, of the first semiconductor layer, and the concentration of doped charges in the first semiconductor region is similar to that of doped charges in the first semiconductor layer, so that the carrier concentration of an N-region can be increased when the diode is conducted in the forward direction, the conduction voltage drop is reduced, the electric field distribution of the active region is balanced when the diode is blocked in the reverse direction, the leakage current is reduced, the breakdown voltage is improved, the problem caused by the existence of the first semiconductor layer is solved, and the forward conduction voltage drop of the diode is reduced and the breakdown voltage is improved while the soft recovery characteristic of the diode is ensured.
In some embodiments, referring again to fig. 1, the soft-recovery power semiconductor diode may comprise: and a buffer layer. The buffer layer is arranged between the substrate and the drift layer in a covering mode, and has the first conductivity type. The buffer layer may comprise a first region 21 of the buffer layer and a second region 22 of the buffer layer. The first region 21 of the buffer layer is located between the first region 11 of the substrate and the first region 31 of the drift layer, and the second region 22 of the buffer layer is located between the second region 12 of the substrate and the second region 32 of the drift layer. The buffer layer may be formed by epitaxial growth. The silicon material may be doped or ion-implanted with impurities of the first conductivity type, for example, resulting in a buffer layer having the first conductivity type. The concentration range of the doping charge of the buffer layer can be 2e14cm -3 ～1e16cm -3 . Further, the thickness of the buffer layer may be set according to the device requirements, for example, the thickness of the buffer layer ranges from 3 μm to 30 μm. In this embodiment, a buffer layer is provided in the active region C1, which is advantageous for better carrier transport.
In some embodiments, referring again to fig. 1, the soft-recovery power semiconductor diode may comprise: a second electrode 112. The second electrode 112 is disposed on a side of the substrate away from the drift layer. The second electrode 112 may be a cathode or an anode, for example, when the first conductivity type is N-type, the second electrode 112 is a cathode. The second electrode 112 may be formed by depositing a metal. The backside of the substrate may be thinned to a desired thickness prior to depositing the second electrode 112.
In some embodiments, referring again to fig. 1, the active region C1 may further include: a third semiconductor layer 7. The third semiconductor layer 7 has the second conductivity type, is formed in the first region 31 of the drift layer, is positioned on the side of the second semiconductor layer 6 away from the substrate, is filled in the first interval region and contacts the first semiconductor region 5; the concentration of the doping charge of the third semiconductor layer 7 is greater than the concentration of the doping charge of the second semiconductor layer 6, and the concentration of the doping charge of the second semiconductor layer 6 is greater than the concentration of the doping charge of the first semiconductor region 5. Doping or ion implantation with impurities of the second conductivity type may be performed to obtain the third semiconductor layer 7 having the second conductivity type. The concentration of the doping charge of the third semiconductor layer 7 may be in the range of 1e18cm -3 ～1e20cm -3 . Further, the thickness of the third semiconductor layer 7 may be set according to the device requirements, for example, the thickness of the third semiconductor layer 7 ranges from 0.2 μm to 1 μm. The third semiconductor layer 7 has high doping concentration, so that the contact resistance can be reduced, and the current capability can be improved.
In some embodiments, referring again to fig. 1, the termination area C1 may include: and a combined structure of the field limiting ring and the field plate. The combined structure of the field limiting ring and the field plate is arranged at one side of the second region 32 of the drift layer, which is far away from the substrate; the second region 32 of the drift layer adjoins the first region 31 of the drift layer. The field limiting ring helps to increase the voltage division of the main junction in the diode device and the field plate helps to suppress the effects of surface charge effects. Therefore, the termination region C1 of this embodiment can enhance the reverse withstand voltage capability of the diode device, enhancing avalanche withstand.
In some embodiments, referring again to fig. 1, the combined structure of the field limiting ring and the field plate in the termination region C1 may include: at least one second semiconductor region 5', a field oxide layer 8 and a second region 10' of the polysilicon layer. The terminal area C1 may further include: a second region 9' of the oxide layer.
Wherein the second semiconductor regions 5' having the second conductivity type are formed in the drift layer second region 32 and close to a side of the drift layer away from the substrate; in the case where the number of the second semiconductor regions 5 'is plural, a second spacing region W9 is provided between two adjacent second semiconductor regions 5'. The second semiconductor regions 5 'may be formed by the same process step as the first semiconductor regions 5, and the second semiconductor regions 5' may be the same or similar to the first semiconductor regions 5, having similar or identical parameters or forming means, such as structure shape, dimension, doping concentration, etc. The second semiconductor region 5' and the first semiconductor region 5 are formed by the same process, so that the device manufacturing process can be simplified. The second spacing regions W9 between different adjacent two of the second semiconductor regions 5' may be the same or different. The field oxide layer 8 is disposed to cover the edge region of each of the second semiconductor regions 5' and each of the second spacing regions W9. The field oxide layer 8 may be formed by thermal oxidation and then by an etching process. The second region 9 'of the oxide layer covers the edge region of the field oxide layer 8 and the portion of the second semiconductor region 5' not covered by the field oxide layer 8. The second region 10 'of the polysilicon layer overlies the second region 9' of the oxide layer. The field oxide layer 8 and the second region 9' of the oxide layer may be formed by thermal oxidation followed by deposition of polysilicon and then may be subjected to an etching process.
In some embodiments, referring again to fig. 1, the active region C1 may further include: a first region 9 of the oxide layer and a first region 10 of the polysilicon layer. The first regions 9 of the oxide layer are disposed over each of the first semiconductor regions 5. The first region 10 of the polysilicon layer is arranged between the first region 9 of the oxide layer and the first electrode 111. In this embodiment, by providing the first region 9 of the oxide layer and the first region 10 of the polysilicon layer in the active region C1, not only the first semiconductor region 5 can be blocked from being improperly ion-implanted, but also the second region 9 'of the oxide layer and the second region 10' of the polysilicon layer can be formed in the same process, so that the manufacturing flow can be saved.
The polysilicon layer 10 may be provided with a window, and a ratio of the width Wp of the polysilicon in the polysilicon layer 10 to the width Ws of the window may be set according to requirements of the diode device, for example, a ratio of the width Wp of the polysilicon in the polysilicon layer (including the first region 10 of the polysilicon layer and the second region 10' of the polysilicon) to the width Ws of the window may range from 0.2 to 0.6. The ratio of the widths of the polysilicon and the windows in the first region 10 of the polysilicon layer may be the same or different than the ratio of the widths of the polysilicon and the windows in the second region 10' of the polysilicon.
In one embodiment, referring to fig. 1, the soft recovery power semiconductor diode mainly includes: an active region C1 and a termination region C2. The active region C1 includes a cathode metal (second electrode 112), a first region 11 of an n+ substrate, a first region 21 of an N-type buffer layer located above the first region 11 of the substrate, a first region 31 of an N-drift layer located above the first region 21 of the buffer layer, regions of an N-type first semiconductor layer 4 and a P-type first semiconductor region 5 located above the first region 31 of the drift layer, regions of a p+ type second semiconductor layer 6 located above the first semiconductor layer 4, regions of a p++ third semiconductor layer 7 located above the second semiconductor layer 6, an oxide layer first region 9 and a polysilicon layer first region 10 located above the first semiconductor region 5, and an anode metal (first electrode 111); the first semiconductor regions 5 are respectively connected with the first semiconductor layer 4, the second semiconductor layer 6 and the third semiconductor layer 7, and are alternately distributed in the active region C1.
The P-type first semiconductor region 5 in the active region C1 may be surrounded by the N-type first semiconductor layer 4, the p+ second semiconductor layer 6, and the p++ third semiconductor layer 7, and may be alternately repeated within the active region C1.
The first region 9 of the oxide layer and the first region 10 of the polysilicon layer of the active region C1 are located above the P-type first semiconductor region 5, and the first region 10 of the polysilicon layer may be directly connected to the anode metal.
The lower boundary of the doped layer of the P-type first semiconductor region 5 in the active region is not lower than the lower boundary of the N-type first semiconductor layer 4, and the ratio Qp/Qn of the total amount Qp of the doped charges of the P-type first semiconductor region 5 to the total amount Qn of the doped charges of the N-type first semiconductor layer 4 may be in the range of 0.9-1.1.
The ratio Wp/Ws of the polysilicon width Wp of the first region 10 of the active region polysilicon layer to the window Ws may range from 0.2 to 0.6.
The doping concentration of the N+ substrate region can be in the range of 5e 18-8 e19cm -3 The thickness may range from 50 to 300 μm.
The doping concentration range of the N-type buffer layer region can be 2e 14-1 e16cm -3 The thickness may range from 3 to 30 μm.
The doping concentration range of the N-drift layer can be 4e 13-1 e15cm -3 The thickness may range from 10 to 100 μm.
The doping concentration of the N-type first semiconductor layer 4 can be in the range of 1e 14-2 e16cm -3 The thickness may range from 1 to 4 μm.
The doping concentration of the P-type first semiconductor region 5 and the second semiconductor region 5' can be in the range of 8e 13-4 e16cm -3 The thickness may range from 3 to 12 μm.
The doping concentration of the P+ second semiconductor layer 6 may be in the range of 3e 15-3 e17cm -3 The thickness may range from 2 to 5 μm.
The doping concentration of the P++ third semiconductor layer 7 can be in the range of 1e 18-1 e20cm -3 The thickness may range from 0.2 to 1 μm.
The thickness of the field oxide layer 8 may be in the range ofThe thickness of the first region 9 of the oxide layer and the second region 9' of the oxide layer may be in the range +.>The thickness of the first region 10 of the polysilicon layer and the second region 10' of the polysilicon layer may be in the range +.>
The introduced P-type first semiconductor region 5 can increase the carrier concentration of the N-region in the forward conduction state, reduce the conduction voltage drop, balance the electric field distribution of the active region in the reverse blocking state, reduce the leakage current and improve the breakdown voltage. Further, the termination region C2 is a field-limiting-ring-added polycrystalline field plate structure formed by the second semiconductor region 5', the field oxide layer 8 and the second region 10' of the polycrystalline silicon layer, so that the breakdown stability of the device can be ensured.
Fig. 2 is a comparison graph of reverse blocking BV simulation curves of a conventional diode and a diode of the present invention, and fig. 3 is a comparison graph of forward conduction simulation curves of a conventional diode and a diode of the present invention, as shown in fig. 2 and 3, compared with a conventional diode structure, the diode structure of the present invention has a higher breakdown voltage and a lower conduction voltage drop (solid line is a simulation result of the diode of the present invention and dotted line is a simulation result of the conventional diode) under the same N-type buffer layer region and N-drift layer condition, thereby satisfying higher voltage application, and simultaneously having lower conduction loss and improving efficiency of a power supply system.
Based on the same inventive concept as the soft recovery power semiconductor diode shown in fig. 1, the embodiments of the present application also provide a method for manufacturing a soft recovery power semiconductor diode, as described in the following embodiments. The principle of solving the problem of the preparation method of the soft recovery power semiconductor diode is similar to that of the soft recovery power semiconductor diode, so that the implementation of the preparation method of the soft recovery power semiconductor diode can be referred to the implementation of the soft recovery power semiconductor diode, and repeated parts are omitted.
In some embodiments, a method for manufacturing a soft recovery power semiconductor diode may include:
step S101: forming a drift layer having a first conductivity type on a substrate having the first conductivity type by epitaxial growth;
step S102: performing thermal oxidation on the drift layer to form an initial field oxide layer;
step S103: photoetching and etching the initial field oxide layer based on a first preset pattern to form a field oxide layer containing at least one field oxide region; the at least one field oxide region is located in a second region of the drift layer; in the case of a plurality of field oxide regions, a spacing region is arranged between two adjacent field oxide regions;
Step S104: ion-implanting the drift layer with a dopant of a second conductivity type based on the field oxide layer including at least one field oxide region to form at least one second semiconductor region of the second conductivity type in a region of the second region of the drift layer not covered by the field oxide region, and to form an initial semiconductor layer of the second conductivity type in a first region of the drift layer; the second conductivity type is different from the first conductivity type; the first region of the drift layer is adjacent to the second region of the drift layer;
step S105: depositing an oxide layer and a polysilicon layer on the initial semiconductor layer, the at least one field oxide region and the at least one second semiconductor region in sequence;
step S106: photoetching and etching the oxide layer and the polysilicon layer based on a second preset pattern to form a first region of the oxide layer and a first region of the polysilicon layer with a first setting window above the initial semiconductor layer, and a second region of the oxide layer and a second region of the polysilicon layer with a second setting window above the second semiconductor region; the second setting window is positioned above the field oxidation region;
Step S107: ion implanting the initial semiconductor layer with a impurity having the first conductivity type, forming a second semiconductor layer having the second conductivity type at the first set window, and forming a first semiconductor layer having the first conductivity type under the second semiconductor layer, and forming a first semiconductor region from a portion of the initial semiconductor layer under a second region of the oxide layer; a lower surface of the first semiconductor region is not lower than a lower surface of the first semiconductor layer; the concentration of the doped charge in the first semiconductor region is similar to that of the doped charge in the first semiconductor layer;
step S108: ion implanting the second semiconductor layer with a impurity having the second conductivity type, forming a third semiconductor layer having the second conductivity type in an upper region of the second semiconductor layer;
step S109: depositing a metal on the third semiconductor layer and the first region of the polysilicon layer to form a second electrode; a metal is deposited on a lower surface of the substrate to form a first electrode.
The first predetermined pattern may be designed according to the coverage of the field oxide region to be formed. The initial semiconductor layer is formed in the step S104, and the initial semiconductor layer is divided into a first semiconductor layer and a second semiconductor layer having different doping concentrations in the step S107, and the second semiconductor layer is further divided into a second semiconductor layer and a third semiconductor layer having different doping concentrations in the step S108. And the doping concentrations of the first semiconductor region and the first semiconductor layer obtained through the steps are similar.
In the above step S104, the ion implantation dose may be 2e 12-1 e14cm -2 The energy may be 80keV to 300keV. In the above step S107, the ion implantation dose may be 2e 11-5 e12cm -2 The energy may be 180keV to 2MeV. In the above step S108, the ion implantation dose may be 1e 15-1 e16cm -2 The energy may be 40KeV to 80KeV.
In some embodiments, the first semiconductor region has a doping concentration ranging from 8e13cm -3 ～4e16cm -3 . In some embodiments, the first semiconductor layer has a doping concentration ranging from 1e14cm -3 ～2e16cm -3 . In some embodiments, the second semiconductor layer has a doping concentration ranging from 3e15cm -3 ～3e17cm -3 . In some embodiments, the third semiconductor layer has a doping concentration ranging from 1e18cm -3 ～1e20cm -3 。
In some embodiments, before step S101, that is, before forming the drift layer with the first conductivity type, the method for manufacturing a soft recovery power semiconductor diode may further include: a buffer layer having the first conductivity type is formed on the substrate by epitaxial growth.
In some embodiments, before step S108, the method for manufacturing a soft recovery power semiconductor diode may further include: annealing is performed to diffuse the impurities.
The following describes the fabrication of soft-recovery power semiconductor diodes according to some embodiments of the present invention in one embodiment. Wherein the preparation conditions or preparation modes in each step can be recombined according to the needs. Fig. 4 is a flow chart of a method for manufacturing a soft recovery power semiconductor diode according to an embodiment of the invention. Fig. 5 to 10 are schematic views illustrating a process for manufacturing a soft recovery power semiconductor diode according to an embodiment of the present invention. Referring to fig. 4 to 10, the method for manufacturing the soft recovery power semiconductor diode of this embodiment may include: step 1: epitaxially growing an N-type buffer layer 2 and an N-drift layer 3 on a substrate 1 at a temperature of 1000-1180 ℃; step 2: under the oxidation environment of 1000-1100 ℃ to form A field oxide layer (FOX) 8; step 3: the ion implantation dosage is 2e 12-1 e14cm after the steps of gluing, exposure, wet etching, photoresist removal and the like -2 P-type impurities with energy of 80-300 keV; step 4: depositing a layer thickness in the range +.>Oxide layer (SOX) (first region 9 comprising oxide layer and second region 9' comprising oxide layer) and thickness in the range +.>Poly (comprising a first region 10 of the polysilicon layer and a second region 10' of the polysilicon layer); step 5: selectively corroding partial oxide layer and polysilicon layer by the steps of gluing, exposing, dry etching and the like, wherein the ion implantation dosage is 2e 11-5 e12cm respectively -2 N-type impurities with energy of 180 keV-2 MeV; step 6: at 1150-1250 deg.c, N 2 Under the environment, push trap shapeForming PN junction; step 7: the common injection dosage is 1e 15-1 e16cm on the surface of the wafer -2 P-type impurities with energy of 40-80 KeV form a P++ region 7; step 8: and thinning and depositing metal on the back surface of the wafer to form cathode contact. More specifically, it may include:
step 01: at 1000-1180deg.C, can be at H 2 And N 2 In the environment, an N-type buffer layer 2 region and an N-drift layer 3 are epitaxially formed on an N+ type substrate 1, and a cross-sectional view of the obtained structure is shown in FIG. 5; wherein, the temperature and the atmosphere environment can be selected according to the requirement.
Step 02: thermal growth at 1000-1100 deg.C in oxidizing environmentA cross-sectional view of the resulting structure of the field oxide layer 8 is shown in fig. 6; wherein, the temperature and the thickness can be selected according to the requirement.
Step 03: the ACT mask plate can be used to obtain the field oxide layer 8 with the cross section shown in figure 7 through the steps of gluing, exposing, wet etching, photoresist removing and the like, and then the implantation dosage is 2e 12-1 e14cm -2 Boron impurity ions (P-type) with energy of 80-300 keV to obtain P-type doped region, the cross section of which is shown in figure 7; other types of masks may be selected as desired.
Step 04: depositing a layer of a thickness in the range ofIs in the range of oxide layer SOX and thicknessA cross-sectional view of the resulting structure is shown in fig. 8; the thicknesses of the oxide layer SOX and the polysilicon layer Poly may be selected as needed.
Step 05: can utilize a Poly mask plate to selectively etch partial oxide layer SOX and polysilicon layer Poly by the steps of gluing, exposing, dry etching and the like, and the injection dosage is 2e 11-5 e12cm respectively -2 The energy is 180keV to ultra high2MeV of phosphorus (N-type) impurity ions, and a cross-sectional view of the resulting structure is shown in FIG. 9. The mask plate type, the implantation dosage and the energy can be selected according to the requirement.
Step 06: at 1150-1250 deg.c, N 2 In the environment, impurity diffusion is carried out, a PN junction is formed by pushing a well, and a cross section of the formed structure is shown in figure 10. The temperature and the atmosphere may be selected as desired.
Step 07: the common injection dosage is 1e 15-1 e16cm on the surface of the wafer -2 P-type impurities with energy of 40-80 KeV are formed into a P++ third semiconductor layer 7 region, and front surface metallization can be performed, so that a cross-sectional view of the formed structure is shown in FIG. 11; the bolus dose and energy may be selected as desired.
Step 08: the wafer backside may be thinned and metal deposited to form a cathode contact, resulting in a structure shown in cross-section in fig. 1.
Fig. 12 is a forward conduction characteristic of a 600V soft-fast recovery diode according to an embodiment of the present invention, fig. 13 is a reverse breakdown characteristic of the 600V soft-fast recovery diode according to an embodiment of the present invention, fig. 14 is a reverse recovery curve of the 600V soft-fast recovery diode according to an embodiment of the present invention, and fig. 15 is an avalanche test curve of the 600V soft-fast recovery diode according to an embodiment of the present invention. As can be seen from fig. 12, the diode device forward conduction voltage drop is 1.2V. As can be seen from fig. 13, the diode device breakdown voltage 725V. As can be seen from fig. 14, the reverse recovery characteristic of the diode device is good. As can be seen from fig. 15, the avalanche current of the diode device reaches 50A. Therefore, in the soft-fast recovery diode structure of the embodiment of the present invention, the first semiconductor region 5 is respectively connected with the first semiconductor layer 4, the second semiconductor layer 6 and the third semiconductor layer 7, and is alternately distributed in the active region C1, so as to balance the electric field distribution and provide the breakdown voltage of the device. The termination region C2 is a field-limiting-ring-added polycrystalline field plate structure formed by the second semiconductor region 5', the field oxide layer 8 and the second region 10' of the polycrystalline silicon layer, so that the breakdown stability of the device can be ensured. The diode has the advantages of simple manufacturing process, high breakdown voltage, low reverse electric leakage, reduced forward conduction voltage, high avalanche resistance, small reverse recovery charge, soft reverse recovery characteristic and the like.
In summary, according to the soft recovery power semiconductor diode and the preparation method thereof provided by the embodiment of the invention, the injection efficiency of the PN junction in the diode can be reduced by arranging the first semiconductor layer with the first conductivity type on one side of the second semiconductor layer with the second conductivity type, so that the carrier concentration of the base region of the diode near the PN junction can be kept at a lower level, the reverse recovery maximum current of the diode can be reduced, and the device is ensured to have soft recovery characteristics. And the first semiconductor region is penetrated in the first semiconductor layer and the second semiconductor layer, so that the surface of the first semiconductor region, which is close to the substrate, is not lower than the surface of the first semiconductor layer, which is close to the substrate, and the doped charge concentration of the first semiconductor region is similar to that of the first semiconductor layer, therefore, the carrier concentration of the N-region can be increased when the diode is conducted in the forward direction, the conduction voltage drop is reduced, the electric field distribution of the active region is balanced when the diode is blocked in the reverse direction, the leakage current is reduced, and the breakdown voltage is improved.
In the description of the present specification, reference to the terms "one embodiment," "one particular embodiment," "some embodiments," "for example," "an example," "a particular example," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. The order of steps involved in the embodiments is illustrative of the practice of the invention, and is not limited and may be suitably modified as desired.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (9)
1. A soft-recovery power semiconductor diode, comprising: an active region and a termination region;
the active region includes:
a first semiconductor layer having a first conductivity type and formed in a first region of the drift layer; the drift layer has the first conductivity type and is covered on the substrate with the first conductivity type;
a second semiconductor layer having a second conductivity type formed in the first region of the drift layer and located on a side of the first semiconductor layer away from the substrate; the first conductivity type is different from the second conductivity type;
at least one first semiconductor region having the second conductivity type and formed through the first semiconductor layer and the second semiconductor layer; the side surface of the first semiconductor region, which is close to the substrate, is not lower than the side surface of the first semiconductor layer, which is close to the substrate; in the case of a plurality of first semiconductor regions, a first spacing region is arranged between two adjacent first semiconductor regions;
A third semiconductor layer having the second conductivity type, formed in the first region of the drift layer, on a side of the second semiconductor layer away from the substrate, filled in the first spacer region and contacting the first semiconductor region; the third semiconductor layer has a concentration of doped charge greater than that of the second semiconductor layer, and the second semiconductor layer has a concentration of doped charge greater than that of the first semiconductor region;
a first electrode disposed on a side of the second semiconductor layer and the first semiconductor region away from the substrate;
wherein a ratio of a concentration of the doping charge in the first semiconductor region to a concentration of the doping charge in the first semiconductor layer is in a range of more than 0.5 and less than 1.5.
2. The soft-recovery power semiconductor diode of claim 1, further comprising:
a second electrode which is arranged on one side of the substrate far from the drift layer;
and a buffer layer which is arranged between the substrate and the drift layer in a covering manner and has the first conductivity type.
3. The soft-recovery power semiconductor diode of claim 1, wherein the termination region comprises:
The combined structure of the field limiting ring and the field plate is arranged on one side, far away from the substrate, of the second region of the drift layer; the second region of the drift layer adjoins the first region of the drift layer.
4. A soft-recovery power semiconductor diode as claimed in claim 3, wherein the combined structure of the field limiting ring and the field plate comprises: at least one second semiconductor region, a field oxide layer, and a second region of the polysilicon layer; the terminal area further includes: a second region of the oxide layer;
the second semiconductor region is provided with the second conductivity type, is formed in the second region of the drift layer and is close to one side of the drift layer, which is far away from the substrate; in the case that the number of the second semiconductor regions is plural, a second interval region is provided between two adjacent second semiconductor regions;
the field oxide layer is covered on the edge area of each second semiconductor area and each second interval area;
a second region of the oxide layer covering an edge region of the field oxide layer and a portion of the second semiconductor region not covered by the field oxide layer;
and the second region of the polysilicon layer is covered on the second region of the oxide layer.
5. The soft-recovery power semiconductor diode of claim 4, wherein the active region further comprises:
The first areas of the oxide layer are covered on the first semiconductor areas;
the first region of the polysilicon layer is covered between the first region of the oxide layer and the first electrode;
the ratio of the width of the polysilicon and the window in the polysilicon layer is in the range of 0.2 to 0.6.
6. The soft-recovery power semiconductor diode of claim 1, wherein a ratio of a total amount of doped charge in the first semiconductor region to a total amount of doped charge in the first semiconductor layer is in a range of 0.9 to 1.1.
7. A soft-recovery power semiconductor diode as defined in claim 1,
the thickness of the first semiconductor region ranges from 3 μm to 12 μm; and/or
The thickness of the first semiconductor layer ranges from 1 μm to 4 μm; and/or
The thickness of the second semiconductor layer ranges from 2 μm to 5 μm; and/or
The thickness of the third semiconductor layer ranges from 0.2 μm to 1 μm.
8. A soft-recovery power semiconductor diode as defined in claim 1,
the concentration range of the doped charge of the first semiconductor region is 8e13 cm -3 ～4e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The concentration of the doped charge of the first semiconductor layer is 1e14 cm -3 ～2e16cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The concentration range of the doped charge of the second semiconductor layer is 3e15 cm -3 ～3e17 cm -3 The method comprises the steps of carrying out a first treatment on the surface of the And/or
The third semiconductor layer has a concentration of doping charges ranging from 1e18 cm -3 ～1e20 cm -3 。
9. A method of fabricating a soft-recovery power semiconductor diode, comprising:
forming a drift layer having a first conductivity type on a substrate having the first conductivity type by epitaxial growth;
performing thermal oxidation on the drift layer to form an initial field oxide layer;
photoetching and etching the initial field oxide layer based on a first preset pattern to form a field oxide layer containing at least one field oxide region; the at least one field oxide region is located in a second region of the drift layer; in the case of a plurality of field oxide regions, a spacing region is arranged between two adjacent field oxide regions;
ion-implanting the drift layer with a dopant of a second conductivity type based on the field oxide layer including at least one field oxide region to form at least one second semiconductor region of the second conductivity type in a region of the second region of the drift layer not covered by the field oxide region, and to form an initial semiconductor layer of the second conductivity type in a first region of the drift layer; the second conductivity type is different from the first conductivity type; the first region of the drift layer is adjacent to the second region of the drift layer;
Depositing an oxide layer and a polysilicon layer on the initial semiconductor layer, the at least one field oxide region and the at least one second semiconductor region in sequence;
photoetching and etching the oxide layer and the polysilicon layer based on a second preset pattern to form a first region provided with a first set window oxide layer and a first region of the polysilicon layer above the initial semiconductor layer, and forming a second region provided with a second set window oxide layer and a second region of the polysilicon layer above the second semiconductor region; the second setting window is positioned above the field oxidation region;
ion implanting the initial semiconductor layer with a impurity having the first conductivity type, forming a second semiconductor layer having the second conductivity type at the first set window, and forming a first semiconductor layer having the first conductivity type under the second semiconductor layer, and forming a first semiconductor region from a portion of the initial semiconductor layer under a second region of the oxide layer; a lower surface of the first semiconductor region is not lower than a lower surface of the first semiconductor layer; the ratio of the concentration of the doped charge in the first semiconductor region to the concentration of the doped charge in the first semiconductor layer is in the range of more than 0.5 and less than 1.5;
Ion implanting the second semiconductor layer with a impurity having the second conductivity type, forming a third semiconductor layer having the second conductivity type in an upper region of the second semiconductor layer;
depositing a metal on the third semiconductor layer and the first region of the polysilicon layer to form a second electrode; a metal is deposited on a lower surface of the substrate to form a first electrode.
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| CN201810696368.4A Active CN108598153B (en) | 2018-06-29 | 2018-06-29 | Soft recovery power semiconductor diode and preparation method thereof |
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| JP2000323488A (en) * | 1999-05-10 | 2000-11-24 | Fuji Electric Co Ltd | Diode and manufacture thereof |
| CN1441968A (en) * | 2000-06-26 | 2003-09-10 | 快捷半导体有限公司 | Soft recovery power diode and related method |
| CN101536194A (en) * | 2006-11-03 | 2009-09-16 | 克里公司 | Power switching semiconductor devices including rectifying junction-shunts |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2000323488A (en) * | 1999-05-10 | 2000-11-24 | Fuji Electric Co Ltd | Diode and manufacture thereof |
| CN1441968A (en) * | 2000-06-26 | 2003-09-10 | 快捷半导体有限公司 | Soft recovery power diode and related method |
| CN101536194A (en) * | 2006-11-03 | 2009-09-16 | 克里公司 | Power switching semiconductor devices including rectifying junction-shunts |
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