JP6780335B2 - Manufacturing method of reverse blocking MOS type semiconductor device and reverse blocking MOS type semiconductor device - Google Patents

Description

The present invention relates to a reverse blocking MOS (Metal Oxide Semiconductor) type semiconductor device and a method for manufacturing a reverse blocking MOS type semiconductor device.

In recent years, in power conversion circuits for performing AC (alternating current) / AC conversion, AC / DC (direct current) conversion, DC / AC conversion, etc. using semiconductor elements, DC smoothing composed of electrolytic capacitors and DC reactors, etc. A matrix converter is known as a direct link type conversion circuit that can eliminate the need for a circuit. Since this matrix converter is used under AC voltage, a plurality of switching devices mounted on the matrix converter require bidirectional switching devices capable of controlling current in the forward and reverse directions.

Recently, from the viewpoints of circuit miniaturization, weight reduction, high efficiency, high-speed response, low cost, etc., the bidirectional switching device has been replaced with two reverse blocking IGBTs (Insulated Gate Bipolar Transistors: Insulated Gate Bipolar Transistors). ) Is attracting attention as an anti-parallel connection configuration. This is because the reverse parallel connection configuration of the reverse blocking IGBT has an advantage that a diode for blocking the reverse voltage can be eliminated. That is, the reverse blocking IGBT refers to a device having a characteristic that the reverse withstand voltage is set to the same level as the forward withstand voltage and the withstand voltage reliability is also improved.

On the other hand, in a normal IGBT used in a conventional power conversion circuit, an effective reverse withstand voltage is not required like a normal transistor or MOSFET having no reverse withstand voltage, so that the reverse withstand voltage is in order in the normal IGBT. An IGBT having a performance that is lower than the withstand voltage and has low withstand voltage reliability was sufficient.

FIG. 15 is a cross-sectional view showing the configuration of a reverse blocking IGBT having a conventional structure. This reverse blocking IGBT has a planar type MOS gate structure included in the active region 110 through which the main current flows in the central portion on the surface side of the silicon semiconductor substrate of the device chip, and has a withstand voltage structure region outside the active region 110. Has 120. Further, a p-type separation region 31 is provided at a position surrounding the outer periphery of the pressure-resistant structure region 120 to connect both main surfaces with a diffusion region of a conductive type different from the conductive type of the semiconductor substrate.

Each semiconductor region of the reverse blocking IGBT of the conventional structure described above will be briefly described. The active region 110 includes a semiconductor substrate (n ^- type drift region) 1, a p-type base region 2, an n ⁺ -type emitter region 3, a gate insulating film 4, a gate electrode 5, an interlayer insulating film 6, an emitter electrode 9, and a p-type collector. This is a region that serves as a main current path for a vertical IGBT including a region 10, a collector electrode 11, and the like. The p-type separation region 31 is a p-type diffusion region formed at a depth equal to or greater than a depth reaching the p-type collector region 10 on the back surface side from the front surface of the semiconductor substrate 1 by thermal diffusion of boron (B). Due to the p-type separation region 31, the end portion of the pn junction surface between the p-type collector region 10 and the n ^- type drift region 1 which are reverse withstand voltage junctions becomes the chip side end surface 12 which becomes the cutting surface at the time of chipping. Since it is not exposed and is exposed on the surface 13 of the pressure-resistant structure portion 120 protected by the interlayer insulating film 6, the reverse pressure resistance reliability can be improved.

However, the reverse blocking type IGBT requires a high temperature and long time heat diffusion drive treatment for forming the p-type separation region 31. For example, when the wafer thickness of the reverse blocking IGBT withstand voltage class 600V to 1200V is about 50 to 180 μm, the thermal diffusion drive processing time is about 100 hours at 1300 ° C. (when the diffusion depth is about 100 μm) at the withstand voltage 600V. At 1200 V, it takes about 300 hours at 1300 ° C. (when the diffusion depth is about 200 μm). For this reason, a large amount of interstitial oxygen is introduced into the semiconductor substrate, an oxygen donor phenomenon occurs, and oxygen precipitates and crystal defects are formed. As a result, the reverse leakage current when a reverse voltage is applied in the vicinity of the pn junction in the semiconductor substrate 1 becomes larger than that of a normal IGBT, the interlayer insulating film 6 is liable to cause thermal deterioration, and the withstand voltage reliability is lowered. ..

It is known that such a reverse blocking IGBT tends to increase the reverse leakage current in the semiconductor substrate when a reverse voltage is applied. Moreover, in the case of the reverse blocking IGBT, there is a problem that the reverse leakage current is particularly likely to lead to thermal runaway. The reason will be explained. As shown in FIG. 15, the reverse leakage current of the reverse blocking IGBT is obtained from the reverse withstand voltage pn junction (pn junction between the n ^- type drift region 1 and the p-type collector region 10) when a reverse voltage is applied to the semiconductor device having the pn junction. Of the pairs of electrons 50 and holes 51 generated in the extending depletion layer, the holes 51 flow into the collector electrode 11, and the electrons 50 flow to the emitter electrode 9 via the p-type base region 2. On the other hand, the reverse blocking IGBT has a layer structure of a parasitic bipolar transistor in its internal layer structure (the p-type base region 2 in FIG. 15 is the emitter, the n ^- type drift region 1 is the base, and the p-type collector region 10 is the collector. It has a pnp transistor).

As described above, the reverse blocking IGBT has a reverse withstand voltage junction having a large reverse leakage current and incorporates a parasitic transistor. Therefore, the electron current of the reverse leakage current (electron hole pair) becomes the base current of the parasitic transistor. Correspondingly, the holes 51 are injected from the p-type base region 2 toward the n ^- type drift region 1 and reach the reverse withstand voltage pn junction, so that the reverse leakage current is amplified. As described above, in the reverse blocking IGBT, the originally large reverse leakage current when the reverse voltage is applied is further rapidly increased by the parasitic transistor, and thermal runaway is likely to occur.

In order to reduce such back leakage current, increase the switching speed, and improve the reverse recovery tolerance, the lifetime control has been performed by irradiating the entire surface of the substrate with an electron beam, but the electron beam irradiation amount ( When the dose amount) is increased, the on-voltage, which has a trade-off relationship, deteriorates, so there is a limit to the lifetime control by electron beam irradiation.

Therefore, a method for injecting (irradiating) charged particles such as protons (hydrogen (H) ions) and helium (He) ions has become known for controlling the lifetime of local minority carriers in semiconductor devices. (See, for example, Patent Document 1). Injecting such charged particle ions into a silicon semiconductor substrate with high energy causes inelastic collisions with electrons in the crystal and elastic collisions with atomic nuclei. In particular, in an elastic collision with an atomic nucleus, silicon atoms are repelled from the lattice points, causing a large number of crystal defects. At the same time, the lifetime of the place where this crystal defect is generated can be locally reduced.

That is, in this method of injecting charged particles, for example, the depth (position) from the surface of the silicon semiconductor substrate is changed by selecting the injection energy of ions, and the amount of crystal defects, that is, the life is changed by changing the injection amount of ions. The feature is that the degree of decrease in time can be controlled. Such charged particles include not only protons and helium ions but also electron beam irradiation, except that defects are formed on the entire substrate when the electron beam is irradiated. When a proton or helium ion other than the electron beam irradiation is irradiated, a defect can be formed only in a predetermined region in the substrate as described above.

For example, in the method of Patent Document 1, a lifetime control region in which crystal defects are generated by helium ion irradiation is formed. FIG. 16 is an enlarged cross-sectional perspective view of a main part for explaining the positional relationship between the p-type base region and the lifetime control region of the reverse blocking IGBT of the conventional structure. As shown in FIG. 16, a width w2 that is substantially the same as or slightly wider than the short side width w1 of the p-type base region 2 along the surface direction (x-axis direction of FIG. 16) of the surface striped pattern of the p-type base region 2. By irradiating the helium ion irradiation region 32 having helium ions with helium ions, the lifetime control region 30 is formed at a predetermined depth indicated by hatching.

Since the lifetime control region 30 reduces the lifetime of electron-hole pairs generated in the depletion layer near the p-type base region 2 and the residual carriers that are abundant near the pn junction, the emitter electrode 9 is subjected to a reverse voltage. The number of electrons 50 that flow in and are eliminated is reduced, and the number of holes 51 that are injected from the p-type base region 2 into the n ^- type drift region 1 is also reduced, that is, the back leakage current is reduced.

Japanese Unexamined Patent Publication No. 2014-90072

However, since the lifetime control region of the conventional structure is formed at a position including the pn junction between the p-type base region 2 and the n ^- type drift region 1, the pn junction surface is damaged by helium ion irradiation, and the pn junction surface is damaged. Crystal defects occur in the junction. Due to the crystal defect of the pn junction surface, the forward leakage current of the reverse blocking IGBT is significantly increased, and there is a problem that the reverse blocking IGBT is likely to cause thermal runaway.

In order to solve the problems caused by the above-mentioned prior art, the present invention is a reverse blocking MOS type semiconductor device and a reverse blocking that can reduce damage to a pn junction and reduce forward leakage current while reducing back leakage current. An object of the present invention is to provide a method for manufacturing a MOS type semiconductor device.

In order to solve the above-mentioned problems and achieve the object of the present invention, the reverse blocking MOS type semiconductor device according to the present invention has the following features. The reverse blocking MOS type semiconductor device includes a second conductive type base region, a first conductive type emitter region, a MOS gate structure, a second conductive type separation region, and a lifetime control region by irradiation of charged particle ions. And. The second conductive type base region is selectively provided on the surface layer of one main surface of the first conductive type semiconductor substrate. The first conductive type emitter region is selectively provided on the surface in the base region. The MOS gate structure includes a gate electrode provided via a gate insulating film on the surface of the base region sandwiched between the emitter region and the surface layer of the region made of the semiconductor substrate. The second conductive type separation region surrounds the base region with a pressure resistant structure region interposed therebetween, and is provided so as to extend from one main surface to the other main surface. The lifetime control region by irradiation of charged particle ions is in the range corresponding to the lower layer of the plane pattern of the base region in the main surface direction of the semiconductor substrate, and the base region and the semiconductor in the depth direction of the semiconductor substrate. It is selectively provided in a range corresponding to a region including a pn junction surface with a substrate. The area of the lifetime control region is 20% to 80% of the area of the base region. The base region has a striped planar pattern portion on the one main surface of the semiconductor substrate. The lifetime control region is arranged so as to overlap the plane pattern on one corner portion side of the bottom surface of the base region, and the lifetime control region includes the one corner portion of the bottom surface of the base region. , The other corner is not included.

Further, the reverse blocking MOS type semiconductor device according to the present invention is characterized in that, in the above-described invention, the short side width of the lifetime control region is narrower than the short side width of the plane pattern.

Further, in the reverse blocking MOS type semiconductor device according to the present invention, when the short side width of the lifetime control region is w4 and the short side width of the plane pattern is w1 in the above-described invention, 0.2 ≦ It is characterized in that w4 / w1 ≦ 0.8 is satisfied.

The inverse blocking MOS-type semiconductor device according to the present invention, in the invention described above, the MOS gate structure, a trench reaching the semiconductor substrate through said emitter region and said base region, said gate within said trench characterized in that it comprises a, and the gate electrode provided via an insulating film.

Further, the reverse blocking MOS type semiconductor device according to the present invention is characterized in that, in the above-described invention, the charged particle ion is a helium ion.

Further, in the reverse blocking MOS type semiconductor device according to the present invention, in the above-described invention, the range in the depth direction of the lifetime control region is the base region with reference to the peak position of the range distribution curve of the irradiation helium ion. It is characterized in that it is 80% to 120% of the depth of.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a reverse blocking MOS semiconductor device according to the present invention has the following features. First, on one main surface of a first conductivity type semiconductor substrate, a step of selectively forming an isolation region of a second conductivity type. Next, a step of selectively forming a base region of a second conductivity type in a surface layer of said one main surface of the semiconductor substrate. Next, a step of selectively forming the first conductive type emitter region on the surface in the base region is performed. Next, a step of forming a MOS gate structure including a gate electrode on the surface of the base region sandwiched between the emitter region and the surface layer of the region made of the semiconductor substrate is performed via a gate insulating film. Next, in the main surface direction of the semiconductor substrate, a region corresponding to the lower layer of the plane pattern of the base region, and in the depth direction of the semiconductor substrate, a region including the pn junction surface between the base region and the semiconductor substrate. A step of selectively forming a lifetime control region by irradiation with charged particle ions is performed in the range corresponding to. Then, the so isolation region spanning from said one main surface to the other main surface, a step of cutting said semiconductor substrate from the other principal surface side. Here, the area of the lifetime control region is 20% to 80% of the area of the base region. The base region has a shape having a striped flat pattern portion on one of the main surfaces of the semiconductor substrate. The lifetime control region is arranged so as to overlap the plane pattern on one corner portion side of the bottom surface of the base region, and the lifetime control region includes the one corner portion of the bottom surface of the base region. , Arrange so as not to include the other corner.

Further, in the method for manufacturing a reverse blocking MOS type semiconductor device according to the present invention, in the above-described invention, the charged particle ion is a helium ion, and the acceleration energy of the helium ion is a value selected from the range of 1 to 30 MeV. The dose amount of the helium ion is 1 × 10 ¹¹ / cm ^{2 to} 3 × 10 ¹¹ / cm ² and is a value selected from the range.

According to the above-mentioned invention, in the reverse blocking IGBT, the lifetime of electron-hole pairs generated in the depletion layer near the p-type base region and the lifetime of many residual carriers near the pn junction are reduced by the lifetime control region. When a reverse voltage is applied, fewer electrons flow into the emitter electrode and are eliminated, and correspondingly fewer holes are injected from the p-type base region into the n ^- type drift region, that is, the back leakage current becomes smaller. .. Further, since the area of the portion irradiated with helium ions is 20% to 80% of the area of the p-type base region, the damage given to the pn junction can be reduced and the forward leakage current can be reduced. Therefore, it is possible to reduce the occurrence of thermal runaway of the reverse blocking IGBT.

According to the method for manufacturing a reverse blocking MOS type semiconductor device and a reverse blocking MOS type semiconductor device according to the present invention, it is possible to reduce the damage to the pn junction and reduce the forward leakage current while reducing the back leakage current. It works.

It is sectional drawing which shows the structure of the reverse blocking IGBT which concerns on Embodiment 1. FIG. FIG. 5 is an enlarged cross-sectional perspective view of a main part for explaining the positional relationship between the p-type base region and the helium ion irradiation region of the reverse blocking IGBT according to the first embodiment (No. 1). FIG. 2 is an enlarged cross-sectional perspective view of a main part for explaining the positional relationship between the p-type base region and the helium ion irradiation region of the reverse blocking IGBT according to the first embodiment (No. 2). FIG. 3 is an enlarged cross-sectional perspective view of a main part for explaining the positional relationship between the p-type base region and the helium ion irradiation region of the reverse blocking IGBT according to the first embodiment (No. 3). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 1 (the 1). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 1 (the 2). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 1 (the 3). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 1 (the 4). It is a relationship diagram of the area of the helium ion irradiation of the reverse blocking IGBT and the reverse leakage current. It is a relationship diagram of the area of helium ion irradiation of the reverse blocking IGBT and the forward leakage current. It is sectional drawing which shows the structure of the reverse blocking IGBT which concerns on Embodiment 2. FIG. It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 2 (the 1). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 2 (the 2). It is sectional drawing which shows typically the state in the manufacturing process of the reverse blocking IGBT which concerns on Embodiment 2 (the 3). It is sectional drawing which shows the structure of the reverse blocking IGBT of a conventional structure. FIG. 5 is an enlarged cross-sectional perspective view of a main part for explaining the positional relationship between the p-type base region and the lifetime control region of the reverse blocking IGBT of the conventional structure.

Hereinafter, preferred embodiments of the reverse blocking MOS semiconductor device and the method for manufacturing the reverse blocking MOS semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. When the notation of n and p including + and-is the same, it indicates that the concentrations are close, and the concentrations are not necessarily the same. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted. In addition, the accompanying drawings described in the examples are not drawn with accurate scales and dimensional ratios for easy viewing or understanding.

(Embodiment 1)
FIG. 1 is a cross-sectional view showing the configuration of the reverse blocking IGBT according to the first embodiment. The reverse blocking IGBT of the first embodiment has an active region 110 including a planar type MOS gate structure and the like in the central portion of the device chip on the surface 13 side of the silicon semiconductor substrate. In a device having a withstand voltage of 600 V, this active region 110 is a p-type base region (second conductive type) having a depth of 3 μm on the surface 13 side of an n ^- type drift region (first conductive type semiconductor substrate) 1 having a thickness of 95 μm. Base region) 2, n ⁺ type emitter region (first conductive type emitter region) 3 with a depth of less than 1 μm, a gate insulating film 4, a MOS gate structure consisting of a gate electrode 5, an interlayer insulating film 6, and the like. This is a region serving as a main current path of a vertical reverse blocking IGBT including an emitter electrode 9 made of an aluminum (Al) alloy film or the like, a p-type collector region 10 on the back surface side, and a collector electrode 11.

Further, the active region 110 has a lifetime control region 30 (hatched portion) composed of helium ion irradiation controlled in a local range, which is a feature of the present invention. Further, the reverse blocking IGBT of the present invention is arranged so as to surround the pressure-resistant structure region 120 on the outer periphery of the active region 110, and has a p-conductive diffusion region different from the n-conductive type of the semiconductor substrate between both main surfaces. It has a p-type separation region 31 to be connected.

The lifetime control region 30 is formed by helium ion irradiation from the surface 13 side of the n ^- type drift region 1. As described above, since the helium ion irradiation can form a defect only in a predetermined region in the substrate, the lifetime control region 30 is formed only in the predetermined region of the silicon semiconductor substrate. Specifically, the lifetime control region 30, n ^- the type drift region 1 in the front surface direction (x-axis direction), the range corresponding to the lower layer of the planar pattern of the p-type base region 2, n ^- -type In the depth direction (y-axis direction) of the drift region 1, it is provided in a range corresponding to a region including a pn junction surface between the n ^- type drift region 1 and the p-type base region 2.

In the above-mentioned helium ion irradiation, the pressure-resistant structure region 120 and the p-type separation region 31 surrounding the n ^- drift region 1 between the p-base regions 2 and the outer periphery of the active region 110 are shielded with a mask or the like, and helium ion irradiation is performed as much as possible. It is preferable not to do. This is because helium irradiation to the n ^- drift region 1 and the pressure resistant structure region 120 may worsen the on-voltage. Further, when the p-type separation region 31 is irradiated with helium ions, the pn junction between the p-type separation region 31 and the n ^- drift region 1 is damaged and the back leakage current becomes large, so it is preferable not to irradiate the p-type separation region 31. ..

Next, the helium ion irradiation region 32 will be described in detail. The helium ion irradiation region 32 is a region where helium ions are irradiated when the reverse blocking IGBT is manufactured (manufactured). 2 to 4 are enlarged cross-sectional perspective views of a main part for explaining the positional relationship between the p-type base region and the helium ion irradiation region of the reverse blocking IGBT according to the first embodiment. Helium ion irradiation is performed using a cyclotron device, as is already well known. In addition, the aperture pattern for helium ion irradiation can be accurately patterned with a photoresist. In the first embodiment, the p-type base region 2 has a short side (a side in the x-axis direction of the plane pattern portion) and a long side (plane pattern) on the front surface (main surface) side of the n ^- type drift region 1. It has a striped plane pattern portion including a side in the z-axis direction of the portion).

As shown in FIGS. 2 to 4, the helium ion irradiation region 32 is present only in a part of the striped pattern on the surface of the p-type base region 2. Specifically, the area of the helium ion irradiation region 32 is 20% to 80% of the area of the p-type base region 2. The specific shape of the helium ion irradiation region 32 is shown in FIGS. 2 to 4.

In the example of FIG. 2, the helium ion irradiation region 32 is arranged so as to overlap the striped plane pattern, and the helium ion irradiation region 32 and the region not irradiated with helium ions are arranged in the long side direction of the striped plane pattern. , Alternately repeated. Here, the length of the helium ion irradiation region 32 is t1. The distance t2 between the helium ion irradiation region 32 and the region not irradiated with helium ions can be selected from a value in which the area of the helium ion irradiation region 32 is 20% to 80% of the area of the p-type base region 2. it can. Further, the length t1 is preferably 10 μm or more, for example, because the dimensional tolerance accuracy in manufacturing is low when the length is 10 μm or less. If it is 100 μm or more, the damage to the pn junction due to helium ion irradiation is concentrated in a part, and the holes reinjected from the p-type base region 2 to the n ^- type drift region 1 are concentrated in a part, so it is 100 μm or less. Is preferable. Therefore, the length t1 is preferably 10 μm to 100 μm.

Further, the width w2 of the helium ion irradiation region 32 preferably has a width w2 that is substantially the same as or slightly wider than the short side width w1 of the p-type base region 2. In this case, since both corner portions of the pn junction at the bottom of the p-type base region 2 are included in the lifetime control region 30, it is possible to alleviate the concentration of the back leakage current that tends to occur at the corner portions. Further, although w1 <w2 in FIG. 2, the larger w2 than w1, the greater the adverse effect on the increase in the on-voltage, so it is preferable that w2 = w1.

Further, it is preferable to provide a plurality of helium ion irradiation regions 32. This is because if there is only one helium ion irradiation region 32, the pn junction region damaged by the helium ion irradiation becomes long, and the region where the current does not easily flow becomes long, so that the forward leakage current does not easily decrease. On the contrary, as the number of the helium ion irradiation regions 32 increases, the region of the pn junction damaged by the helium ion irradiation becomes shorter, so that the current easily flows and the forward leakage current can be reduced.

In the example of FIG. 3, the helium ion irradiation region 32 is arranged so as to overlap the striped plane pattern, and the width w3 of the helium ion irradiation region 32 is narrower than the short side width w1 of the p-type base region 2. .. The width w3 can be selected from those satisfying w3 ≦ 0.8 × w1 and w3 ≧ 0.2 × w1. In this case, the helium ion irradiation region 32 has a simpler mask for forming the helium ion irradiation region 32 than the helium ion irradiation region 32 of FIG. 2, and the formation man-hours can be reduced.

In the example of FIG. 4, the helium ion irradiation region 32 is arranged so as to overlap the striped plane pattern, and the lifetime control region 30 is arranged so as to include any one corner of the bottom surface of the p-type base region 2. Will be done. In FIG. 4, the lifetime control region 30 includes a corner portion on the left bottom surface of the p-type base region 2. The width w4 of the helium ion irradiation region 32 is narrower than the short side width w1 of the p-type base region 2. The width w4 can be selected from those satisfying w4 ≦ 0.8 × w1 and w4 ≧ 0.2 × w1. In this case, as in the case of FIG. 3, the mask for forming the helium ion irradiation region 32 is simplified, and the lifetime control region 30 is the corner portion of any one of the bottom surfaces of the p-type base region 2. Therefore, it is possible to alleviate the concentration of the back leakage current that tends to occur at the corner portion.

(Manufacturing method of reverse blocking IGBT according to the first embodiment)
Next, a method of manufacturing the reverse blocking IGBT according to the first embodiment will be described. 5 to 8 are cross-sectional views schematically showing a state in the middle of manufacturing the reverse blocking IGBT according to the first embodiment. Here, a method of manufacturing a reverse blocking IGBT having a withstand voltage of 1200 V will be described. As shown in FIG. 5, an initial oxide film 101 having a thickness of 500 μm or more and a specific resistance of 80 Ω cm is formed on the surface of an FZ (Floating Zone) silicon substrate 100 having a thickness of about 0.8 μm to 2.5 μm.

Next, the initial oxide film 101 is selectively etched with an annular pattern surrounding the outer periphery of the active region and the pressure resistant structure region to form the MOS gate structure in the central portion of each device chip region in the silicon substrate 100. , An opening 20 for separation and diffusion having a width of 170 μm is formed. The state up to this point is shown in FIG.

Next, boron, which is a p-type impurity, is ion-implanted from the opening 20 using the initial oxide film 101 as a mask. After the boron ion implantation, the initial oxide film 101 used as the dopant mask is removed. Next, heat treatment is performed at a high temperature (1300 ° C.) for a long time (300 hours to 330 hours) in an oxidizing atmosphere to form a p-type separation region 31 having a depth of about 200 μm. Due to the p-type separation region 31, the end portion of the pn junction surface between the p-type collector region 10 and the n ^- type drift region 1 which are reverse withstand voltage junctions is exposed to the chip side end surface 12 which is the cutting surface at the time of chipping. Instead, it is exposed on the surface 13 of the pressure-resistant structure portion 120 protected by the insulating film, so that the reverse pressure resistance reliability can be improved. The state up to this point is shown in FIG. Although all the p-type separation regions 31 are formed by the diffusion step here, a V-type groove may be formed first and then boron may be implanted by ion implantation around the groove.

Next, after removing the oxide film formed on the surface of the substrate during the formation of the p-type separation region 31, the oxide film is reattached, and the oxide film and / or the deposited polysilicon film is used to diffuse the depth in a predetermined pattern. The p-type base region 2, n ⁺ -type emitter region 3, gate insulating film 4, gate electrode 5, interlayer insulating film 6, emitter electrode 9 and the like having a size of 2 μm to 10 μm, for example, 3 μm, are known in the same manner as a normal planar gate type IGBT. Form by method. Next, helium ion irradiation is selectively performed along the surface pattern of the p-type base region 2 as shown in FIGS. 2 to 4 in order to form the lifetime control region 30 which is a feature of the present invention. At this time, the lifetime control region 30 is formed in the region sandwiching the pn junction surface on the bottom surface of the p-type base region 2 in the depth direction of the helium ion acceleration energy. Further, since helium ions have more mass than protons, the width of the ion implantation region tends to be wider in the depth direction. Therefore, the lifetime control region 30 can be formed widely in the depth direction by helium ion implantation.

Specifically, to give an example of helium ion irradiation conditions, for example, helium with an acceleration energy of 23 MeV so that the pn junction surface on the bottom surface of the p-type base region 2 having a diffusion depth of 3 μm has a peak of helium ion irradiation. Irradiate ions. This acceleration energy can be selected from, for example, about 1.0 to 30 MeV depending on the depth of the p-type base region 2. Further, the range in the depth direction of the lifetime control region 30 is 80% to 120% of the depth of the p-type base region 2 with reference to the peak position of the range distribution curve of the irradiated helium ion. The dose amount of helium ion shall be in the range of 1 × 10 ¹¹ cm ^{2 to} 3 × 10 ¹¹ cm ² . As a result, the lifetime control region 30 having a width of about 0.6 μm is formed above and below the position of the depth of the p-type base region 2. The state up to this point is shown in FIG.

Next, the back surface of the silicon substrate 100 is scraped to make the thickness of the silicon substrate 100 about 180 μm, and the p-type separation region 31 is exposed on the scraped surface 21. The state up to this point is shown in FIG. Next, boron with a dose amount of 1 × 10 ¹³ / cm ² was ion-implanted and low-temperature annealing was performed at about 350 ° C. for about 1 hour, and the peak concentration of activated boron was about 1 × 10 ¹⁷ / cm ³ . A p-type collector layer 10 having a thickness of about 1 μm is formed. The p-type collector layer 10 on the back surface and the p-type separation region 31 are electrically connected. When the silicon substrate 1 is cut into each device chip after forming the collector electrode 11 similar to the conventional one, the reverse blocking IGBT according to the present invention shown in FIG. 1 is manufactured.

Next, the reverse leakage current and the forward leakage current of the reverse blocking IGBT according to the first embodiment will be described. FIG. 9 is a diagram showing the relationship between the area of helium ion irradiation of the reverse blocking IGBT and the back leakage current. FIG. 9 is a result of applying a reverse voltage to the reverse blocking IGBT and the conventional reverse blocking IGBT according to the first embodiment and measuring the reverse current. In FIG. 9, the horizontal axis shows the ratio of the area of the region irradiated with helium ions to the area of the p-type base region 2 (hereinafter, abbreviated as He irradiation area / p-type base area). The unit is%. The vertical axis indicates the reverse leakage current. The unit is μA.

Further, in FIG. 9, when the He irradiation area / p-type base area = 0%, it is an example of the reverse blocking IGBT of the prior art in which the helium ion irradiation is not performed. In this case, it can be seen that the back leakage current is as high as 60 μA. Further, when He irradiation area / p-type base area = 100%, it is an example of the reverse blocking IGBT of the prior art in which the entire surface of the p-type base region is irradiated with helium ions. In this case, it can be seen that the back leakage current is as low as 10 μA. On the other hand, when the He irradiation area / p-type base area = 20%, 50%, and 80%, it is an example of the reverse blocking IGBT according to the first embodiment. In this case, it can be seen that the back leakage current is 10 μA, which is as low as that of the conventional technique in which the entire surface of the p-type base region is irradiated with helium ions. From this, it can be seen that the back leakage current can be sufficiently reduced even if the He irradiation area / p-type base area is set to 20% to 80%.

FIG. 10 is a diagram showing the relationship between the area of helium ion irradiation of the reverse blocking IGBT and the forward leakage current. FIG. 10 is a result of applying a forward voltage to the reverse blocking IGBT and the conventional reverse blocking IGBT according to the first embodiment and measuring the forward current. In FIG. 10, the horizontal axis represents the He irradiation area / p-type base area. The unit is%. The vertical axis indicates the forward leakage current. The unit is μA.

Further, in FIG. 10, when the He irradiation area / p-type base area = 0%, it is an example of the reverse blocking IGBT of the prior art in which the helium ion irradiation is not performed. In this case, since there is no damage to the pn junction, it can be seen that the forward leakage current is as low as about 0 μA. Further, when He irradiation area / p-type base area = 100%, it is an example of the reverse blocking IGBT of the prior art in which the entire surface of the p-type base region is irradiated with helium ions. In this case, it can be seen that the forward leakage current is as high as 2.0 μA because the pn junction is damaged. On the other hand, when the He irradiation area / p-type base area = 20%, 50%, and 80%, it is an example of the reverse blocking IGBT according to the first embodiment. In this case, since the damage of the pn junction is reduced, it can be seen that the forward leakage current is as low as 1.0 μA. From this, it can be seen that the forward leakage current can be sufficiently reduced by setting the He irradiation area / p-type base area to 20% to 80%.

As described above, according to the first embodiment, the reverse blocking IGBT has a large number of electron-hole pairs generated in the depletion layer near the p-type base region and residual carriers near the pn junction due to the lifetime control region. Since the lifetime of is reduced, less electrons flow into the emitter electrode and are eliminated when a reverse voltage is applied, and correspondingly fewer holes are injected from the p-type base region into the n ^- type drift region. That is, the back leakage current becomes small. Further, since the area of the portion irradiated with helium ions is 20% to 80% of the area of the p-type base region, the damage given to the pn junction can be reduced and the forward leakage current can be reduced. Therefore, it is possible to reduce the occurrence of thermal runaway of the reverse blocking IGBT.

(Embodiment 2)
FIG. 11 is a cross-sectional view showing the configuration of the reverse blocking IGBT according to the second embodiment. The reverse blocking IGBT according to the second embodiment differs from the reverse blocking IGBT according to the first embodiment in that it has a trench structure. Further, the reverse blocking IGBT according to the second embodiment also has a pressure resistant structure region and a p-type separation region, similarly to the reverse blocking IGBT according to the first embodiment. However, since the structure of the pressure-resistant structure region and the p-type separation region is the same as that of the first embodiment, only the active region is shown in FIG.

As shown in FIG. 11, in the reverse blocking IGBT according to the second embodiment, the n ^- type drift region 1 is deposited on the first main surface (front surface) of the n-type semiconductor substrate 41. A p-type base region 2 is provided on the surface of the n ^- type drift region 1 opposite to the n-type semiconductor substrate 41 side. Inside the p-type base region 2, n ⁺ -type emitter region 42 and p ⁺ -type contact region 43 is selectively provided on the first main surface side. Further, the n ⁺ type emitter region 42 and the p ⁺ type contact region 43 are in contact with each other.

A trench structure is formed on the first main surface side (p-type base region 2 side) of the n-type semiconductor substrate 41. Specifically, the trench 45 penetrates the n ⁺ type emitter region 42 and the p-type base region 2 from the surface opposite to the n-type semiconductor substrate 41 side of the p-type base region 2 and n ^- type drift. Reach area 1. A gate insulating film 4 is formed on the bottom and side walls of the trench 45 along the inner wall of the trench 45, and a gate electrode 5 is formed inside the gate insulating film 4 in the trench 45. The gate electrode 5 is insulated from the n ^- type drift region 1 and the p-type base region 2 by the gate insulating film 4.

The interlayer insulating film 44 is provided on the entire surface of the n-type semiconductor substrate 41 on the first main surface side so as to cover the gate electrode 5 embedded in the trench 45. The emitter electrode 9 is in contact with the n ⁺ type emitter region 42 and the p ⁺ type contact region 43 through a contact hole opened in the interlayer insulating film 44. The emitter electrode 9 is electrically insulated from the gate electrode 5 by the interlayer insulating film 44. A collector electrode 11 is provided on the second main surface (back surface) of the n-type semiconductor substrate 41.

Further, the lifetime control region 30 is provided in a range corresponding to a region including a pn junction surface between the upper surface of the n ^- type drift region 1 and the bottom surface of the p-type base region 2 between the trench 45 and the trench 45. The ratio of the area of the lifetime control region 30 to the area of the p-type base region 2 is 20% to 80% as in the first embodiment. The specific shape of the helium ion irradiation region 32 for forming the lifetime control region 30 is also the same as that of the first embodiment.

(Manufacturing method of reverse blocking IGBT according to the second embodiment)
Next, a method of manufacturing the reverse blocking IGBT according to the second embodiment will be described. 12 to 14 are cross-sectional views schematically showing a state in the middle of manufacturing the reverse blocking IGBT according to the second embodiment.

First, the n-type semiconductor substrate 41 is prepared. Then, an n ^- type drift region 1 is epitaxially grown on the first main surface of the n-type semiconductor substrate 41 while doping an n-type impurity, for example, a nitrogen atom (N). The state up to this point is shown in FIG.

Next, the p-type base region 2 is epitaxially grown on the surface of the n ^- type drift region 1 while doping a p-type impurity, for example, an aluminum (Al) atom. Next, a mask (not shown) having a desired opening is formed on the surface of the p-type base region 2 by a photolithography technique, for example, with an oxide film. Then, using this oxide film as a mask, n-type impurities such as phosphorus (P) are ion-implanted by the ion implantation method. As a result, the n ⁺ type emitter region 42 is formed in a part of the surface layer of the p-type base region 2.

Next, the mask used during ion implantation to form the n ⁺ type emitter region 42 is removed. Then, a mask (not shown) having a desired opening is formed on the surface of the p-type base region 2 by a photolithography technique, for example, with an oxide film, and the p-type is formed on the surface of the p-type base region 2 using this oxide film as a mask. Impurities such as aluminum are ion-implanted. As a result, the p ⁺ type contact region 43 is formed in a part of the surface region of the p-type base region 2. Subsequently, the mask used during ion implantation to form the p ⁺ type contact region 43 is removed. The order of ion implantation for forming the n ⁺ type emitter region 42 and ion implantation for forming the p ⁺ type contact region 43 may be interchanged. The state up to this point is shown in FIG.

Next, heat treatment (annealing) is performed to activate, for example, the n ⁺ type emitter region 42 and the p ⁺ type contact region 43. As described above, each ion implantation region may be activated collectively by one heat treatment, or may be activated by heat treatment each time ion implantation is performed.

Next, on the p-type base region 2 of the surface (i.e. the surface of the n ⁺ -type emitter region 42 and p ⁺ -type contact region 43), the mask, for example, an oxide film (not shown) having a desired opening by photolithography formed To do. Then, using this oxide film as a mask, a trench 45 that penetrates the n ⁺ type emitter region 42 and the p-type base region 2 and reaches the n ^- type drift region 1 is formed by dry etching or the like. Subsequently, the mask used to form the trench 45 is removed.

Next, the gate insulating film 4 is formed along the surfaces of the n ⁺ type emitter region 42 and the p ⁺ type contact region 43, and the bottom and side walls of the trench 45. The gate insulating film 4 may be formed by heat treatment at a temperature of about 1000 ° C. in an oxygen atmosphere. Further, the gate insulating film 4 may be formed by a method of depositing by a chemical reaction such as high temperature oxidation (HTO).

Next, a polycrystalline silicon layer doped with, for example, a phosphorus atom is formed on the gate insulating film 4. This polycrystalline silicon layer is formed so as to fill the inside of the trench 45. The gate electrode 5 is formed by patterning the polycrystalline silicon layer and leaving it inside the trench 45.

Next, for example, phosphorus glass is formed with a thickness of about 1 μm so as to cover the gate insulating film 4 and the gate electrode 5, to form the interlayer insulating film 44. By patterning and selectively removing the interlayer insulating film 44 and the gate insulating film 4, a contact hole is formed to expose the n ⁺ type emitter region 42 and the p ⁺ type contact region 43. Then, heat treatment (reflow) is performed to flatten the interlayer insulating film 44.

Next, a conductive film to be the emitter electrode 9 is formed in the contact hole and on the interlayer insulating film 44. This conductive film is selectively removed, leaving the emitter electrode 9 only in, for example, the contact hole.

Next, helium ion irradiation is selectively performed along the surface pattern of the p-type base region 2 as shown in FIGS. 2 to 4 in order to form the lifetime control region 30 which is a feature of the present invention. At this time, the lifetime control region 30 is formed in the region sandwiching the pn junction surface on the bottom surface of the p-type base region 2 in the thickness direction of the helium ion acceleration energy. Next, a collector electrode 11 made of, for example, a nickel (Ni) film is formed on the second main surface of the n-type semiconductor substrate 41. As described above, the reverse blocking IGBT shown in FIG. 11 is completed.

As described above, according to the method for manufacturing the reverse blocking IGBT and the reverse blocking IGBT according to the second embodiment, the same effect as the manufacturing method for the reverse blocking IGBT and the reverse blocking IGBT according to the first embodiment can be obtained. Can be done.

In the above, in the present invention, the first conductive type is n-type and the second conductive type is p-type in each embodiment, but in the present invention, the first conductive type is p-type and the second conductive type is n-type. The same holds true.

As described above, the method for manufacturing the reverse blocking IGBT and the reverse blocking IGBT according to the present invention is useful for the reverse blocking MOS type semiconductor device such as the reverse blocking IGBT used for the power conversion device and the manufacturing method thereof.

1 n ^- type drift region 2 p-type base region 3 n ⁺ -type emitter region 4 Gate insulating film 5 Gate electrode 6 Interlayer insulating film 9 Emitter electrode 10 p-type collector region 11 Collector electrode 12 Chip side end face 13 Surface 21 Shaving surface 30 Life Time control region 31 p-type separation region 32 helium ion injection region 41 n-type semiconductor substrate 42 n ⁺ emitter region 43 p ⁺ contact region 44 interlayer insulating film 45 trench 50 electrons 51 holes 100 silicon substrate 101 initial oxide film 110 active region 120 Pressure-resistant structure area

Claims (8)

A second conductive type base region selectively provided on the surface layer of one main surface of the first conductive type semiconductor substrate, and a second conductive type base region.
A first conductive type emitter region selectively provided on the surface in the base region,
A MOS gate structure including a gate electrode provided via a gate insulating film on the surface of the base region sandwiched between the emitter region and the surface layer of the region made of the semiconductor substrate.
A second conductive type separation region is provided around the outer periphery of the base region with a pressure resistant structure region sandwiched between the main surface and the other main surface.
In the main surface direction of the semiconductor substrate, it corresponds to a range corresponding to the lower layer of the plane pattern of the base region, and in the depth direction of the semiconductor substrate, it corresponds to a region including a pn junction surface between the base region and the semiconductor substrate. A lifetime control region by irradiation of charged particle ions, which is selectively provided in the range,
With
Area of the lifetime control region Ri between 20% and 80% der of the area of the base region,
The base region has a striped planar pattern portion on the one main surface of the semiconductor substrate.
The lifetime control region is arranged so as to overlap the plane pattern on one corner portion side of the bottom surface of the base region, and the lifetime control region includes the one corner portion on the bottom surface of the base region. , A reverse blocking MOS type semiconductor device characterized in that it is arranged so as not to include the other corner portion . The reverse blocking MOS type semiconductor device according to claim 1, wherein the short side width of the lifetime control region is narrower than the short side width of the plane pattern. The second aspect of the present invention is characterized in that 0.2 ≦ w4 / w1 ≦ 0.8 is satisfied when the short side width of the lifetime control region is w4 and the short side width of the plane pattern is w1. Reverse blocking MOS type semiconductor device. The MOS gate structure is characterized by including a trench that penetrates the emitter region and the base region and reaches the semiconductor substrate, and the gate electrode provided inside the trench via the gate insulating film. The reverse blocking MOS semiconductor device according to any one of claims 1 to 3. The reverse blocking MOS semiconductor device according to any one of claims 1 to 4, wherein the charged particle ion is a helium ion. 5. The range of the lifetime control region in the depth direction is 80% to 120% of the depth of the base region with reference to the peak position of the range distribution curve of the irradiated helium ion. The reverse blocking MOS type semiconductor device described in 1. A step of selectively forming a second conductive type separation region on one main surface of the first conductive type semiconductor substrate, and
A step of selectively forming a second conductive type base region on the surface layer of the one main surface of the semiconductor substrate, and
A step of selectively forming a first conductive type emitter region on the surface in the base region, and
A step of forming a MOS gate structure including a gate electrode on the surface of the base region sandwiched between the emitter region and the surface layer of the region made of the semiconductor substrate via a gate insulating film.
In the main surface direction of the semiconductor substrate, it corresponds to a range corresponding to the lower layer of the plane pattern of the base region, and in the depth direction of the semiconductor substrate, it corresponds to a region including a pn junction surface between the base region and the semiconductor substrate. A process of selectively forming a lifetime control region by irradiation of charged particle ions in the range,
A step of scraping the semiconductor substrate from the other main surface side so that the separation region extends from the one main surface to the other main surface.
Including
The area of the lifetime control region is 20% to 80% of the area of the base region.
The base region has a shape having a striped flat pattern portion on one of the main surfaces of the semiconductor substrate.
The lifetime control region is arranged so as to overlap the plane pattern on one corner portion side of the bottom surface of the base region, and the lifetime control region includes the one corner portion on the bottom surface of the base region. A method for manufacturing a reverse blocking MOS type semiconductor device, which comprises arranging the semiconductor device so as not to include the other corner portion. The charged particle ion is a helium ion,
The acceleration energy of the helium ion is a value selected from the range of 1 to 30 MeV, and the dose amount of the helium ion is 1 × 10. ¹¹ / Cm ² ~ 3x10 ¹¹ / Cm ² The method for manufacturing a reverse blocking MOS semiconductor device according to claim 7, wherein the value is selected from the range of.

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