CN110854072B - Manufacturing process of low electromagnetic interference power device terminal structure - Google Patents
Manufacturing process of low electromagnetic interference power device terminal structure Download PDFInfo
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H—ELECTRICITY
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
Abstract
The invention provides a manufacturing process of a terminal structure of a low electromagnetic interference power device, wherein the terminal structure manufactured by the process comprises the following steps: the semiconductor device comprises a metalized drain electrode, a first conductive type semiconductor substrate, a first conductive type semiconductor epitaxial layer, a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring, a first conductive type stop ring, a second conductive type semiconductor field limiting ring, a first dielectric layer, a second dielectric layer, a third dielectric layer, a conductive field plate, a resistor and a metalized source electrode which are sequentially stacked from bottom to top. According to the invention, the HK dielectric layer can be introduced between the field limiting ring and the field plate, the MIS capacitor structure is formed by the semiconductor field limiting ring, the HK dielectric layer and the field plate, and the semiconductor field limiting ring, the HK dielectric layer and the field plate are connected in series with the adjacent polysilicon resistor, so that an RC absorption network is formed between the high potentials of the source electrode and the drain electrode, dv/dt and di/dt generated by a power device in a quick switch can be effectively inhibited, and EMI noise is relieved.
Description
Technical Field
The invention relates to the field of power semiconductor devices, in particular to a manufacturing process of a power device terminal structure.
Background
In general, a typical application environment of a power device is a switching power supply, in order to meet the miniaturization requirement of the switching power supply, the switching frequency and the power density of the power device are continuously increased, and modularization and functional integration can increase the power density of electronic components, but an increasingly complex internal electromagnetic environment can also be generated. Under the condition of fast switching conversion, the voltage and the current of the power device change rapidly in a short time to generate high dv/dt and di/dt, which become a strong electromagnetic interference source.
In the aspect of electromagnetic interference (EMI) suppression technology, firstly, high-frequency and high-amplitude electromagnetic interference is weakened from the aspect of circuit conduction paths, for example, common-mode interference and differential-mode interference can be effectively suppressed through the design of an EMI filter, but only high-frequency noise in a certain frequency band can be filtered. And secondly, the parasitic capacitance is improved from the aspect of device design, but the switching loss of the device is easily increased or the process steps of the device are easily increased.
Disclosure of Invention
The present invention aims to address at least one of the above-mentioned deficiencies of the prior art.
In order to achieve the above objects, an object of the present invention is to provide a method of manufacturing a power device termination structure having reduced electromagnetic interference. In addition, another object of the present invention is to provide a method for manufacturing a power device termination structure with reduced electromagnetic interference, and to provide the method with good compatibility.
In order to achieve the above object, the present invention provides a manufacturing process of a terminal structure of a low electromagnetic interference power device, wherein the manufacturing process comprises the following steps: growing a first conductive type semiconductor epitaxial layer on a first conductive type semiconductor substrate; spin-coating photoresist, injecting second conductive type ions or the ionic compound with the photoresist after exposure and development, removing the photoresist, pushing the junction in a diffusion furnace through high-temperature diffusion after cleaning, and activating impurities to form a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring and a second conductive type semiconductor field limiting ring on the upper part of the first conductive type semiconductor epitaxial layer; removing and cleaning photoresist, rotationally coating photoresist, exposing and developing, injecting first conductive type ions or a compound of the first conductive type ions with the photoresist, pushing the junction through high-temperature diffusion in a diffusion furnace after the photoresist is removed and cleaned, and activating impurities to form a first conductive type stop ring on the far end side of the upper part of the first conductive type semiconductor epitaxial layer, which is far away from the second conductive type semiconductor main junction; depositing to form an HK gate dielectric film, and depositing to form a field plate film; photoetching and etching, respectively removing redundant HK gate dielectric films and field plate films to correspondingly form a plurality of first dielectric layers and conductive field plates which are mutually separated, so that the plurality of mutually separated first dielectric layers respectively cover the upper surfaces of the second conductive type semiconductor equipotential ring, the first conductive type stop ring and the second conductive type semiconductor field limiting ring, and the upper surface of each first dielectric layer is correspondingly covered with one conductive field plate; depositing a second dielectric layer between every two first dielectric layers in the plurality of first dielectric layers which are separated from each other; forming a resistor on each second dielectric layer, and electrically connecting the resistors adjacent to each other in series with the conductive field plate; covering the upper surfaces of all resistors and the upper surfaces of all conductive field plates with a third dielectric layer; and metalizing to form a metalized source electrode and a metalized drain electrode, wherein the metalized source electrode is positioned above the second conductive type semiconductor main junction and is in direct contact with the second conductive type semiconductor main junction, and the metalized drain electrode is formed on one side of the first conductive type semiconductor substrate where the first conductive type semiconductor epitaxial layer is not grown.
Compared with the prior art, the invention has the beneficial effects that: the HK dielectric layer can be introduced between the field limiting ring and the field plate, the MIS capacitor structure is formed by the semiconductor field limiting ring, the HK dielectric layer and the field plate, and the semiconductor field limiting ring, the HK dielectric layer and the field plate are connected in series with the adjacent polysilicon resistor, so that an RC absorption network is formed between high potentials of a source electrode and a drain electrode, dv/dt and di/dt generated by a power device in a quick switch can be effectively inhibited, and EMI noise is relieved.
Drawings
Fig. 1 is a flow chart illustrating an exemplary embodiment of a process for manufacturing a termination structure of a low emi power device according to the present invention.
Fig. 2 is a schematic structural diagram illustrating a terminal structure of the low emi power device manufactured in fig. 1.
Fig. 3 shows an equivalent circuit diagram of an RC network of the termination structure of the low emi power device of fig. 2.
Fig. 4 to 11 are schematic flow charts illustrating an exemplary embodiment of a manufacturing process of a low emi power device termination structure according to the present invention.
The reference numerals are explained below:
a metalized drain 1, a first conductivity type semiconductor substrate 2, a first conductivity type semiconductor epitaxial layer 3, a second conductivity type semiconductor main junction 4, a second conductivity type semiconductor equipotential ring 5, second conductivity type semiconductor field limiting rings 61 and 62, a first conductivity type stop ring 7, first dielectric layers 81, 82, 805 and 807, conductive field plates 91, 92, 905 and 907, resistors 101, 102 and 103, a second dielectric layer 11, a metalized source 12, and a third dielectric layer 13.
Detailed Description
Hereinafter, the terminal structure of the low electromagnetic interference power device of the present invention will be described in detail with reference to exemplary embodiments.
Fig. 1 is a schematic flow diagram illustrating an exemplary embodiment of a process for fabricating a termination structure of a low emi power device in accordance with the present invention.
As shown in fig. 1, in an exemplary embodiment of the present invention, a manufacturing process of a low electromagnetic interference power device termination structure includes the following steps:
and S01, growing a first conduction type semiconductor epitaxial layer on the first conduction type semiconductor substrate. The first conductivity type semiconductor epitaxial layer may have a predetermined withstand voltage requirement and a predetermined thickness, for example, the predetermined withstand voltage requirement may be 600V or more; the predetermined thickness may be in a range of 30um to 40um. The doping level of the first conductive type semiconductor substrate may be greater than the doping level of the first conductive type semiconductor epitaxial layer. The doped element can be phosphorus, arsenic, antimony, etc. For example, the first conductive type semiconductor substrate may be heavily doped and may have a concentration of 1 × 10 19 cm -3 ~1×10 20 cm -3 (ii) a The epitaxial layer of the first conductivity type semiconductor may be lightly doped and may have a concentration ranging from 1 × 10 15 cm -3 ~1×10 16 cm -3 。
S02, photoresist is coated in a rotating mode, second conductive type ions or ionic compounds are injected with the photoresist after exposure and development, the photoresist is removed, after cleaning, junction pushing is carried out in a diffusion furnace through high-temperature diffusion, and impurities are activated to form a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring and a second conductive type semiconductor field limiting ring on the upper portion of the first conductive type semiconductor epitaxial layer. Here, it is also possible to form the second conductivity type semiconductor main junction first, and then form the second conductivity type semiconductor equipotential ring and the second conductivity type semiconductor field limiting ring.
S03, photoresist is removed and cleaned, photoresist is coated in a rotating mode, exposure and development are carried out, first conductive type ions or a compound of the first conductive type ions are injected with the photoresist, after the photoresist is removed and cleaned, junction pushing and impurity activation are carried out in a diffusion furnace through high-temperature diffusion, and a first conductive type stop ring is formed on the far end side, far away from a second conductive type semiconductor main junction, of the upper portion of the first conductive type semiconductor epitaxial layer.
And S04, depositing to form an HK gate dielectric film, and depositing to form a field plate film (for example, a polysilicon field plate film). In addition, the field plate film can be further subjected to compensation doping. For example, the field plate film is background doped p-type, followed by offset n-type doping to obtain a net p-type doped field plate film. Wherein the p-type background doping concentration is not more than 5 × 10 19 cm -3 N-type compensation doping concentration not more than 3 x 10 18 cm -3 . In addition, the thickness of the field plate film can be in the range of 0.5um to 1um.
S05, photoetching and etching are carried out, redundant HK gate dielectric films and field plate films are removed respectively, so that a plurality of first dielectric layers and conductive field plates which are separated from each other are correspondingly formed, the plurality of first dielectric layers which are separated from each other cover the upper surfaces of the second conductive type semiconductor equipotential rings, the first conductive type stop rings and the second conductive type semiconductor field limiting rings respectively, and one conductive field plate is correspondingly covered on the upper surface of each first dielectric layer. That is, a plurality of first dielectric layers which are separated from each other are correspondingly formed by the HK gate dielectric film; the conductive field plate is correspondingly formed by a field plate film.
S06, depositing a second dielectric layer between every two first dielectric layers in the plurality of spaced first dielectric layers, wherein the thickness of the second dielectric layer can be larger than that of the first dielectric layers.
And S07, forming a resistor on each second dielectric layer, and electrically connecting the resistors adjacent to each other in series with the conductive field plate. For example, the resistor may be a polysilicon resistor.
And S08, covering the upper surfaces of all resistors and the upper surfaces of all conductive field plates with a third dielectric layer.
And S09, metalizing to form a metalized source electrode and a metalized drain electrode, wherein the metalized source electrode is positioned above the second conductive type semiconductor main junction and is in direct contact with the second conductive type semiconductor main junction, and the metalized drain electrode is formed on one surface, not growing the first conductive type semiconductor epitaxial layer, of the first conductive type semiconductor substrate.
In an exemplary embodiment of the present invention, the low emi power device terminal structure shown in fig. 1 may be formed by sequentially stacking a metalized drain (hereinafter, may be referred to as a drain), a first conductive type semiconductor substrate (hereinafter, may be referred to as a substrate), a first conductive type semiconductor epitaxial layer (hereinafter, may be referred to as an epitaxial layer), a second conductive type semiconductor main junction (hereinafter, may be referred to as a main junction), a second conductive type semiconductor equipotential ring (hereinafter, may be referred to as an equipotential ring), a first conductive type stop ring (hereinafter, may be referred to as a stop ring), a second conductive type semiconductor field limiting ring (hereinafter, may be referred to as a field limiting ring), a first dielectric layer, a second dielectric layer, a third dielectric layer, a conductive field plate (hereinafter, may be referred to as a stop ring), a resistor, and a metalized source (hereinafter, may be referred to as a source) from bottom to top.
Specifically, a second conductivity type semiconductor main junction, a second conductivity type semiconductor equipotential ring, and a first conductivity type stop ring may be disposed on the first conductivity type semiconductor epitaxial layer; the second conductive type semiconductor main junction is directly contacted with the metalized source electrode which is positioned right above the second conductive type semiconductor main junction, and the second conductive type semiconductor main junction and the metalized source electrode can be positioned on the left side of the upper part of the first conductive type semiconductor epitaxial layer together. The second conductive type semiconductor equipotential ring is contacted with the second conductive type semiconductor main junction; the first conductivity type stop ring may be located on a side away from the main junction of the second conductivity type semiconductor (e.g., located outside the first conductivity type semiconductor)Right side of the upper portion of the epitaxial layer). Here, the first conductive type semiconductor substrate is doped more than the first conductive type semiconductor epitaxial layer. For example, the first conductivity type semiconductor substrate is heavily doped, and the first conductivity type semiconductor epitaxial layer is lightly doped. Wherein the first conductivity type ions may be phosphorus, arsenic, antimony, etc., and the typical concentration of the heavily doped first conductivity type semiconductor substrate is 1 × 10 19 cm -3 ~1×10 20 cm -3 Typical concentration range of the lightly doped first conductivity type semiconductor epitaxial layer is 1 × 10 15 cm -3 ~1×10 16 cm -3 。
The second conductive type semiconductor field limiting ring may be disposed on an upper portion of the first conductive type semiconductor epitaxial layer and between the second conductive type semiconductor equipotential ring and the first conductive type stop ring. Further, the number of the second conductive type semiconductor field limiting rings may be one or two or more spaced apart from each other.
The first dielectric layers which are separated from each other can respectively cover the upper surfaces of the second conductive type semiconductor equipotential ring, the first conductive type stop ring and the second conductive type semiconductor field limiting ring. The number of the first dielectric layers may be two plus the number of the second conductive type semiconductor field limiting rings. That is, one first dielectric layer is formed on the upper surfaces of the second conductivity type semiconductor equipotential ring, the first conductivity type stopper ring, and each of the second conductivity type semiconductor field limiting rings, the respective first dielectric layers being spaced apart from each other. The upper surface of each first dielectric layer can be correspondingly covered with a conductive field plate; and a second dielectric layer is arranged between every two first dielectric layers in the plurality of mutually-separated first dielectric layers. A resistor (e.g., a polysilicon resistor) may be disposed on the upper surface of each second dielectric layer to form a resistor between each two adjacent conductive field plates, and the two adjacent conductive field plates are physically separated from the resistor but electrically connected in series by, for example, a metal interconnect or a polysilicon interconnect. That is, the number of resistors is equal to the number of second dielectric layers, and the number of conductive field plates is equal to the number of first dielectric layers. The dielectric constant of the first dielectric layer can be higher than that of silicon dioxide, so that the size of the capacitor can be increased under the condition that the thickness of the dielectric layer is unchanged, and the switching oscillation of the device can be relieved. The second dielectric layer may have a thickness greater than the first dielectric layer.
A third dielectric layer covers the upper surfaces of all resistors and the upper surfaces of all conductive field plates. In addition, the third dielectric layer can also cover the upper surface of the outer leakage of the first dielectric layer and the upper surface of the outer leakage of the second dielectric layer.
Fig. 2 is a schematic structural diagram of another low emi power device termination structure fabricated in fig. 1.
As shown in fig. 2, a low emi power device termination structure according to another exemplary embodiment of the present invention may be formed by a metalized drain 1, a first conductive type semiconductor substrate 2, a first conductive type semiconductor epitaxial layer 3, a second conductive type semiconductor main junction 4, a second conductive type semiconductor equipotential ring 5, second conductive type semiconductor field limiting rings 61 and 62, a first conductive type stop ring 7, first dielectric layers 81, 82, 805, and 807, conductive field plates 91, 92, 905, and 907, resistors 101, 102, and 103, a second dielectric layer 11, a metalized source 12, and a third dielectric layer 13.
Specifically, the low electromagnetic interference power device terminal structure comprises a metalized drain electrode 1, a first conduction type semiconductor substrate 2, a first conduction type semiconductor epitaxial layer 3 and a metalized source electrode 12 which are sequentially stacked from bottom to top. The first conductivity type semiconductor epitaxial layer 3 has a second conductivity type semiconductor main junction 4, a second conductivity type semiconductor equipotential ring 5, and a first conductivity type stopper ring 7 on the upper portion. The main semiconductor junction 4 of the second conductivity type is in direct contact with the metalized source 12 directly above it.
The second conductivity type semiconductor equipotential ring 5 is in contact with the second conductivity type semiconductor main junction 4, and the first conductivity type stopper ring 7 is located on a distal side away from the second conductivity type semiconductor main junction 4. One or more second-conductivity-type semiconductor field limiting rings (marked as: 61, 62, … … n, n is a natural number, and n is more than or equal to 1) are arranged between the second-conductivity-type semiconductor equipotential ring 5 and the first-conductivity-type stop ring 7.
The upper surfaces of the equipotential ring 5 and the stop ring 7 are respectively covered with first dielectric layers (for example, HK dielectric layers (recorded as 805 and 807), the upper surfaces of the second conductive type semiconductor field limiting rings are respectively covered with first dielectric layers (for example, HK dielectric layers) (recorded as: 81, 82, … … 8n, n is a natural number, and n is more than or equal to 1), the upper surfaces of the HK dielectric layers are provided with field plates (recorded as: 905, 907, 91, 92 … … 9n, n is a natural number, and n is more than or equal to 1) with good conductive capability, the HK dielectric layers are generic dielectric materials with dielectric constants larger than silicon dioxide (K = 3.9), and the common HK dielectric layers (high-K materials) comprise nitrides, ferroelectric materials, metal oxides and the like.
A second dielectric layer 11 (for example, a thick dielectric layer) is arranged between the adjacent first dielectric layers, and the upper surface of the second dielectric layer 11 has a resistor (marked as 101, 102 … … 10n, n is a natural number and n is more than or equal to 1). And the adjacent resistors are electrically connected with the field plate through metal interconnection wires or polycrystalline interconnection wires. The resistor and the upper surface of the field plate are covered with a third dielectric layer 13. The dielectric constant of the first dielectric layer is higher than that of silicon dioxide. Here, the thickness of the second dielectric layer (e.g., thick dielectric layer) may be in a range of 0.5um to 2um.
Fig. 4 to 11 are schematic flow charts illustrating an exemplary embodiment of a manufacturing process of a low emi power device termination structure according to the present invention.
In yet another exemplary embodiment of the present invention, as shown in fig. 4 to 11, the manufacturing process of the low emi power device termination structure may be implemented by the following process.
First, as shown in fig. 4, a first conductive type epitaxial layer 3 (e.g., a lightly doped epitaxial layer of the first conductive type) satisfying a predetermined withstand voltage requirement and having a predetermined thickness is grown on a first conductive type semiconductor substrate 2 (e.g., a heavily doped semiconductor substrate of the first conductive type) by an epitaxial process. For example, the substrate and epitaxial layer material may be silicon (Si). For example, the predetermined withstand voltage requirement may be 600V or even higher; the predetermined thickness may be in a range of 30um to 40um.
As shown in fig. 5, a photoresist is spin-coated, exposed and developed, a second conductive type ion (such as boron or indium) or an ionic compound thereof is implanted with a photoresist, and after cleaning by photoresist stripping, junction pushing is performed by high temperature diffusion in a diffusion furnace, and impurities are activated to form a second conductive type semiconductor main junction 4.
As shown in FIG. 6, spin-coating photoresist, exposing and developing, injecting second conductive type ions or the ionic compound with the photoresist, removing the photoresist, cleaning, and performing high-temperature diffusion and junction pushing in a diffusion furnace to activate impurities to form a second conductive type equipotential ring 5 and field limiting rings 61, 62 … … n, wherein n is more than or equal to 1.
As shown in fig. 7, the photoresist is stripped and cleaned, then the photoresist is spin-coated, exposed and developed, the photoresist is implanted with ions of the first conductivity type (such as phosphorus, arsenic, antimony, etc.) or the ionic compound, after the photoresist is stripped and cleaned, the junction is pushed by high temperature diffusion in a diffusion furnace, and the impurities are activated to form a stop ring 7 of the first conductivity type, for example, a semiconductor stop ring of the first conductivity type.
And depositing to form an HK gate dielectric film with a predetermined thickness. For example, the HK gate dielectric film can have a thickness of 0.2um to 0.5um or less. The film can be obtained by sputtering a rare earth target and a titanium target in oxygen-containing gas on a substrate. And (3) depositing a polysilicon field plate with a preset thickness by using low-pressure chemical vapor deposition, and manufacturing the polysilicon field plate by using compensation doping. For example, polysilicon film is background doped p-type with boron, for example, and the polysilicon field plate material is net p-type doped after being doped n-type with phosphorus, for example. Wherein the background doping concentration with boron is not more than 5 × 10 19 cm -3 N-type compensation doping concentration not more than 3 x 10 18 cm -3 . For example, the predetermined thickness of the polysilicon field plate may be in the range of 0.5um to 1um.
As shown in fig. 8, the redundant HK dielectric layer and the polysilicon field plate are removed by photolithography and etching respectively; a dielectric layer 11 is deposited.
As shown in fig. 9, a polysilicon resistor is formed on the dielectric layer 11 and connected to the heavily doped polysilicon field plate.
As shown in fig. 10, a dielectric layer 13 covers the upper surfaces of the polysilicon field plate and the polysilicon resistor.
Finally, as shown in fig. 11, a source metal 12 and a drain metal 1 are metalized through metal sputtering and a silicon wafer back thinning process.
The operation mechanism of the exemplary embodiment of the present invention in fig. 2 or fig. 11 will be described below with the first conductivity type semiconductor being n-type silicon and the second conductivity type semiconductor being p-type silicon.
In the planar terminal structure, the junction depth is shallow and the curvature radius of the junction is small, resulting in a reduction in withstand voltage. The field limiting ring can effectively reduce a high electric field caused by the surface curvature effect of the planar junction, improve the breakdown voltage, and the field plate can effectively inhibit low breakdown caused by surface charges. The composite terminal structure combining the field limiting ring and the field plate effectively reduces the length of the terminal, increases the area utilization rate of the terminal, and improves the stability and reliability of the terminal structure. As shown in fig. 3, the second conductivity type semiconductor equipotential ring 5 is equipotential with the second conductivity type semiconductor main junction 4, and the second conductivity type semiconductor main junction 4 is in direct contact with the source 12, so the potential of the second conductivity type semiconductor equipotential ring 5 is the source potential; when the drain is under high voltage, the first conductivity type stop ring 7 is located outside the depletion region, so the potential of the first conductivity type stop ring 7 is the drain potential. The upper surface of the second conductive type semiconductor equipotential ring 5 is covered with a first dielectric layer and a field plate, and a metal-insulating layer-semiconductor structure (MIS capacitor structure) is formed by the semiconductor field limiting ring, the first dielectric layer and the field plate. The MIS structure is connected with a polysilicon resistor on the right side to form a resistor-capacitor (RC) absorption unit; and the RC unit is repeated above the field limiting rings (61, 62, … … 6n, n is more than or equal to 1) and the cut-off rings to form an RC absorption network which is placed between the drain potential and the source potential, so that the effective relief of drain terminal switching voltage and current oscillation is realized. Therefore, the composite terminal structure provided by the invention effectively relieves the electromagnetic interference problem of the device on the basis of improving the voltage resistance of the device; and the manufacturing method has strong compatibility, and does not add extra masks and excessive process steps.
In conclusion, the HK dielectric layer can be introduced between the field limiting ring and the field plate, the MIS capacitor structure is formed by the semiconductor field limiting ring, the HK dielectric layer and the field plate and is connected with the adjacent polysilicon resistor in series, so that an RC absorption network is formed between the high potentials of the source electrode and the drain electrode, dv/dt and di/dt generated by a power device in a quick switch can be effectively inhibited, and EMI noise is relieved. In addition, the field limiting ring and the main junction can be formed by diffusion at the same time, and the main junction and the field limiting ring can obtain higher breakdown voltage when the electric field intensity reaches the critical electric field at the same time, so that the voltage resistance of the device is enhanced on one hand, and the EMI noise is effectively inhibited on the other hand.
Although the present invention has been described above in connection with the exemplary embodiments and the accompanying drawings, it will be apparent to those of ordinary skill in the art that various modifications may be made to the above-described embodiments without departing from the spirit and scope of the claims.
Claims (4)
1. A manufacturing process of a terminal structure of a low electromagnetic interference power device is characterized by comprising the following steps:
s01, growing a first conductive type semiconductor epitaxial layer on a first conductive type semiconductor substrate, wherein the doping degree of the first conductive type semiconductor substrate is greater than that of the first conductive type semiconductor epitaxial layer, and the typical concentration of the first conductive type semiconductor substrate is 1 x 10 19 cm -3 ～1×10 20 cm -3 The typical concentration of the epitaxial layer of the first conductivity type semiconductor is 1 × 10 15 cm -3 ～1×10 16 cm -3 (ii) a The first conductive type semiconductor epitaxial layer has a preset voltage withstanding requirement and a preset thickness, the preset voltage withstanding requirement is over 600V, and the preset thickness is within the range of 30-40 um;
s02, photoresist is coated in a rotating mode, after exposure and development, second conductive type ions or second conductive type ionic compounds are injected with the photoresist, the photoresist is removed, after cleaning, the junction is pushed through high-temperature diffusion in a diffusion furnace, impurities are activated, so that a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring and a second conductive type semiconductor field limiting ring are formed on the upper portion of the first conductive type semiconductor epitaxial layer, and the second conductive type semiconductor main junction and the second conductive type semiconductor field limiting ring are formed through simultaneous diffusion;
s03, removing photoresist, cleaning, rotationally coating photoresist, exposing and developing, injecting first conductive type ions or a compound of the first conductive type ions with the photoresist, pushing junctions in a diffusion furnace through high-temperature diffusion after the photoresist is removed and cleaned, and activating impurities to form a first conductive type stop ring on the upper portion of the first conductive type semiconductor epitaxial layer on the far side away from the second conductive type semiconductor main junction;
s04, depositing to form an HK gate dielectric film, depositing to form a field plate film, carrying out p-type background doping on the field plate film, and carrying out n-type compensation doping to obtain a net p-type doped field plate film, wherein the p-type background doping concentration is not more than 5 x 10 19 cm -3 N-type compensation doping concentration not more than 3 x 10 18 cm -3 ；
S05, photoetching and etching, respectively removing redundant HK gate dielectric films and field plate films to correspondingly form a plurality of first dielectric layers and conductive field plates which are mutually separated, so that the plurality of mutually separated first dielectric layers respectively cover the upper surfaces of the second conductive type semiconductor equipotential ring, the first conductive type stop ring and the second conductive type semiconductor field limiting ring, and one conductive field plate is correspondingly covered on the upper surface of each first dielectric layer; the number of the second conductive type semiconductor field limiting rings is one or more than two which are mutually separated, and the dielectric constant of the first dielectric layer is higher than that of silicon dioxide;
s06, depositing a second dielectric layer between every two first dielectric layers in the plurality of first dielectric layers which are separated from each other; the thickness range of the second dielectric layer is 0.5-2 um, and the thickness of the second dielectric layer is larger than that of the first dielectric layer;
s07, forming a resistor on each second dielectric layer, and electrically connecting the resistors adjacent to each other in series with the conductive field plate;
s08, covering the third dielectric layer on the upper surfaces of all resistors and the upper surfaces of all conductive field plates;
s09, metalizing to form a metalized source and a metalized drain, wherein the metalized source is positioned above the second conductive type semiconductor main junction and is in direct contact with the second conductive type semiconductor main junction, and the metalized drain is formed on one surface, on which the first conductive type semiconductor epitaxial layer does not grow, of the first conductive type semiconductor substrate;
the terminal structure of the low electromagnetic interference power device obtained by the manufacturing process comprises: a metallized drain electrode, a first conductive type semiconductor substrate, a first conductive type semiconductor epitaxial layer, a second conductive type semiconductor main junction, a second conductive type semiconductor equipotential ring, a first conductive type stop ring, a second conductive type semiconductor field limiting ring, a first dielectric layer, a second dielectric layer, a third dielectric layer, a conductive field plate, a resistor and a metallized source electrode which are sequentially arranged in a stacking way from bottom to top,
the second conductive type semiconductor main junction, the second conductive type semiconductor equipotential ring and the first conductive type stopping ring are arranged on the upper portion of the first conductive type semiconductor epitaxial layer, the second conductive type semiconductor main junction is in direct contact with a metalized source electrode located right above the second conductive type semiconductor main junction, the second conductive type semiconductor equipotential ring is in contact with the second conductive type semiconductor main junction, and the first conductive type stopping ring is located on the far end side far away from the second conductive type semiconductor main junction;
the second conductive type semiconductor field limiting ring is arranged on the upper part of the first conductive type semiconductor epitaxial layer and is positioned between the second conductive type semiconductor equipotential ring and the first conductive type stop ring; the number of the second conduction type semiconductor field limiting rings is more than two;
the plurality of first dielectric layers which are separated from each other cover the upper surfaces of the equipotential ring, the stop ring and the second conduction type semiconductor field limiting ring respectively, a conductive field plate covers the upper surface of each first dielectric layer correspondingly, meanwhile, one second dielectric layer is arranged between every two first dielectric layers in the plurality of first dielectric layers which are separated from each other, a resistor is formed on the upper surface of each second dielectric layer correspondingly, so that a resistor is formed between every two adjacent conductive field plates, and the resistors which are adjacent to each other are electrically connected with the conductive field plates in series;
a third dielectric layer covers the upper surfaces of all resistors and the upper surfaces of all conductive field plates.
2. The process of manufacturing a termination structure of a low emi power device as claimed in claim 1, wherein the third dielectric layer further covers the upper surface of the outer drain of the first dielectric layer and the upper surface of the outer drain of the second dielectric layer.
3. The process of manufacturing a termination structure of a low emi power device as claimed in claim 1, wherein the resistor is a polysilicon resistor.
4. The process of manufacturing a termination structure for a low emi power device according to claim 1, wherein the series electrical connection is made through a metal interconnect or a poly interconnect.
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| CN115241183B (en) * | 2022-09-15 | 2023-01-24 | 北京芯可鉴科技有限公司 | Voltage clamped superjunction device and method of manufacture |
| CN115224024B (en) * | 2022-09-15 | 2023-01-24 | 北京芯可鉴科技有限公司 | Super junction device of integrated gate-drain capacitor and manufacturing method |
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| CN100565879C (en) * | 2008-01-08 | 2009-12-02 | 苏州硅能半导体科技股份有限公司 | A kind of deep groove large power MOS device and manufacture method thereof |
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