CN108321187A - A kind of terminal structure of with groove - Google Patents
A kind of terminal structure of with groove Download PDFInfo
- Publication number
- CN108321187A CN108321187A CN201810307605.3A CN201810307605A CN108321187A CN 108321187 A CN108321187 A CN 108321187A CN 201810307605 A CN201810307605 A CN 201810307605A CN 108321187 A CN108321187 A CN 108321187A
- Authority
- CN
- China
- Prior art keywords
- conduction type
- type
- terminal structure
- well region
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 claims abstract description 21
- 229910052751 metal Inorganic materials 0.000 claims abstract description 21
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 18
- 229910052760 oxygen Inorganic materials 0.000 claims description 18
- 239000001301 oxygen Substances 0.000 claims description 18
- 238000002161 passivation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 8
- 238000005516 engineering process Methods 0.000 abstract description 3
- 238000000407 epitaxy Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 6
- 230000015556 catabolic process Effects 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the manufacturing technology fields of semiconductor devices, it is related to a kind of terminal structure of with groove, include the collector electrode metal for drawing collector and the first conductive type epitaxial layer above the collector electrode metal, several the second conduction type field limiting rings of the second conduction type well region are set there are one the second conduction type well region and surround on first conductive type epitaxial layer surface, it is characterized in that, several grooves parallel to each other are set in the second conduction type well region, the grid oxide layer of the conductive polycrystalline silicon and the package conductive polycrystalline silicon positioned at center floating is equipped in the groove；The present invention increases the potential at main knot by increasing groove structure in well region, reduce the number of field limiting ring, and then reduce device terminal width, the present invention is while ensureing device voltage endurance capability, reduce device terminal area, and then the area of entire device is reduced, element manufacturing cost is reduced, cost performance is improved.
Description
Technical field
The present invention relates to a kind of terminal structure of semiconductor devices, the terminal structure of specifically a kind of with groove belongs to half
The manufacturing technology field of conductor device.
Background technology
In power semiconductor field, the design of terminal and the pressure resistance of device and reliability are closely bound up, and terminal is born
Voltage can be divided into lateral voltage and longitudinal voliage, determine longitudinal voliage principal element be device epitaxial layers thickness, determine
The principal element of lateral voltage is exactly device terminal width, and what the terminal structure of existing device was all made of at present is field limiting ring structure
Terminal the second conduction type is equipped in the collector electrode metal as shown in Fig. 2, by taking the terminal structure of IGBT device as an example
Epitaxial layer is equipped with the first conductive type buffer layer on second conductive type epitaxial layer, slow in first conduction type
It rushes layer and is equipped with the first conductive type epitaxial layer, set there are one the second conduction type on first conductive type epitaxial layer surface
Well region and several the second conduction type field limiting rings, the second conduction type field limiting ring are located at the periphery of terminal structure, and
The second conduction type well region is surrounded, potential determines device terminal structure at the main knot 10 at the second conductive type of trap area edge
Initial potential, initial potential is higher, terminal structure need field limiting ring number it is fewer, the width of terminal structure is got over
Narrow, the potential at the main knot 10 of current existing terminal structure is smaller, therefore laterally pressure resistance all relies on field limiting ring to terminal substantially,
For high-voltage product, it is necessary to increase field limiting ring to improve pressure resistance, considerably increase the area of device terminal so that active region area
Reduce, while increasing production cost, in addition, laterally pressure-resistant efficiency of this terminal structure close to several field limiting rings of active area
It is relatively low.
Invention content
The purpose of the present invention is overcoming the deficiencies in the prior art, a kind of terminal structure of with groove is provided, is passed through
Increase groove structure in well region to increase the potential at main knot, reduce the number of field limiting ring, and then reduce device terminal width,
The present invention reduces device terminal area, and then reduce the area of entire device while ensureing device voltage endurance capability, drop
Low element manufacturing cost, improves cost performance.
To realize the above technical purpose, the technical scheme is that：A kind of terminal structure of with groove, including be used to draw
Go out the collector electrode metal of collector and the first conductive type epitaxial layer above the collector electrode metal, is led described first
Electric type epi-layer surface set there are one the second conduction type well region and surround the second conduction type well region several the
Two conduction type field limiting rings, which is characterized in that several grooves parallel to each other are set in the second conduction type well region,
The grid oxide layer of the conductive polycrystalline silicon and the package conductive polycrystalline silicon positioned at center floating is equipped in the groove.
Further, it is equipped with field oxygen layer on first conductive type epitaxial layer, is equipped in the field oxygen layer several
A field plate, one of field plate can be electrically connected by through-hole with the second conduction type well region, and floating state is may be alternatively provided as,
Remaining field plate can be electrically connected by through-hole with the second conduction type field limiting ring, and floating state is may be alternatively provided as.
Further, the second conduction type well region and the second conduction type field limiting ring are from first conduction type
Epi-layer surface extends to inside it, and active area and termination environment of the second conduction type well region across device.
Further, the side of active area is provided with emitter metal in termination environment, the emitter metal passes through
Through-hole in the oxygen layer of field is electrically connected with the second conduction type well region.
Further, passivation layer is covered on the termination environment surface.
Further, the second conduction type field limiting ring can be not provided with, and the field plate can not also be arranged.
Further, the depth of the groove can be more than the depth of the second conduction type well region.
Further, the terminal structure includes the terminal structure and p-type power semiconductor device of N-type power semiconductor
The terminal structure of part, for the terminal structure of N-type power semiconductor, first conduction type is N-type, and described second leads
Electric type is p-type, and for the terminal structure of P-type semiconductor device, the first conduction type is p-type, and the second conduction type is N-type.
Further, the device of the terminal structure of the with groove includes IGBT device and MOSFET element.
The present invention has the following advantages：
1）Compared with conventional terminal structure, the present invention includes conductive polycrystalline silicon by the way that several are arranged in the second conduction type well region
Groove so that the initial potential at the second main knot of conductive type of trap area edge significantly increases, in the identical situation of device pressure resistance
Under, the number of field limiting ring setting can be reduced, or even be not provided with, and substantially reduced the width of terminal structure, worked as chip area
One timing, terminal structure occupied area reduce, and active area occupied area increases, and device on-resistance can reduce；When active area face
Product is constant, and terminal width reduces so that entire chip area reduces, and reduces production cost, improves the cost performance of chip；
2）The manufacturing process of terminal structure of the present invention is compatible with prior art.
Description of the drawings
Attached drawing is to be used to provide further understanding of the present invention, an and part for constitution instruction, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the overlooking structure diagram of power semiconductor.
Fig. 2 is the structural schematic diagram of conventional terminal structure.
Fig. 3 is the structural schematic diagram of 1 with groove terminal structure of the embodiment of the present invention.
Fig. 4 is the structural schematic diagram of 2 with groove terminal structure of the embodiment of the present invention.
Fig. 5 is the structural schematic diagram of 3 with groove terminal structure of the embodiment of the present invention.
Fig. 6 is structure of the invention（Fig. 3）With traditional structure（Fig. 2）Surface potential distribution map when breakdown.
Reference sign：001-active area；002-termination environment；1-collector electrode metal；2-the second conduction type collection
Electrode district；3-the first conductive type buffer layer；4-the first conductive type epitaxial layer；5-the second conduction type field limiting ring；6—
Second conduction type well region；7-grooves；8-conductive polycrystalline silicons；9-grid oxide layers；10-main knots；11-emitter metals；12—
Field plate；13-field oxygen layer；14-passivation layers.
Specific implementation mode
With reference to specific drawings and examples, the invention will be further described.
The present invention is not limited to the following embodiments and the accompanying drawings, each figure of institute's reference is to be able to this hair in the following description
Bright content is understood and is arranged, i.e., the present invention is not limited to the device architecture that each figure is illustrated, is not only suitable for IGBT device,
It is suitable for MOSFET element again.
As shown in Figure 1, for semiconductor devices overlooking structure diagram, the semiconductor devices include active area 001 and
Surround the termination environment 002 of the active area 001.
As shown in figure 3, embodiment 1 is with IGBT device, and the first conduction type is N-type, and the second conduction type is that p-type is
Example, a kind of terminal structure of with groove includes the collector electrode metal 1 for drawing collector, in the collector electrode metal 1 according to
It is secondary to be equipped with p-type collector area 2, the N-type buffer layer 3 on the p-type collector area 2 and on the N-type buffer layer 3
N-type epitaxy layer 4 sets there are one P type trap zone 6 and surrounds several p-types of the P type trap zone 6 on 4 surface of the N-type epitaxy layer
Field limiting ring 5, the p-type field limiting ring 5 are located at the periphery of terminal structure, and the P type trap zone 6 and p-type field limiting ring 5 are from the N-type
4 surface of epitaxial layer extends to inside it, and active area 001 and termination environment 002 of the P type trap zone 6 across device, and feature exists
In in the P type trap zone 6, there are six the grooves 7 being mutually parallel for setting, and the depth of groove 7 is less than the depth of P type trap zone 6
Degree is equipped with the conductive polycrystalline silicon 8 for being located at center floating and the grid oxide layer for wrapping up the conductive polycrystalline silicon 8 in the groove 7
9；
The width of groove 7 is about 1 μm in the present embodiment 1, and 5 μm are spaced about between each groove 7；
It is equipped with field oxygen layer 13 in the N-type epitaxy layer 4, several field plates 12 are equipped in the field oxygen layer 13, one of them
Field plate 12 is electrically connected by through-hole with the P type trap zone 6, and remaining field plate 12 is electrically connected by through-hole with the p-type field limiting ring 5,
The side of active area 001 is provided with emitter metal 11 in the termination environment 002, the emitter metal 11 passes through field oxygen
Through-hole in layer 13 is electrically connected with the P type trap zone 6, and passivation layer 14 is covered on 002 surface of the termination environment；
If by taking MOSFET element as an example, N-type substrate is provided only between collector electrode metal 1 and N-type epitaxy layer 4.
As shown in figure 4, embodiment 2 is with IGBT device, and the first conduction type is N-type, and the second conduction type is that p-type is
Example, a P type trap zone 6 is provided only on 4 surface of the N-type epitaxy layer, is not provided with p-type field limiting ring 6, and the P type trap zone 6 is from described
4 surface of N-type epitaxy layer extends to inside it, and active area 001 and termination environment 002 of the P type trap zone 6 across device, special
Sign is, in the P type trap zone 6, is provided with 20 grooves being mutually parallel 7, and the depth of groove 7 is less than P type trap zone 6
Depth, the grid of conductive polycrystalline silicon 8 and package positioned at center the floating conductive polycrystalline silicon 8 are equipped in the groove 7
Oxygen layer 9；
It is equipped with field oxygen layer 13 in the N-type epitaxy layer 4, is set in the field oxygen layer 13 there are one field plate 12, the field plate 12
It is electrically connected with the P type trap zone 6 by through-hole, the side of active area 001 is provided with emitter gold in the termination environment 002
Belong to 11, the emitter metal 11 is electrically connected by the through-hole in field oxygen layer 13 with the P type trap zone 6, in the termination environment 002
Surface is covered with passivation layer 14.
As shown in figure 5, embodiment 3 is with IGBT device, and the first conduction type is N-type, and the second conduction type is that p-type is
Example, a P type trap zone 6 is provided only on 4 surface of the N-type epitaxy layer, is not provided with p-type field limiting ring 6, and the P type trap zone 6 is from described
4 surface of N-type epitaxy layer extends to inside it, and active area 001 and termination environment 002 of the P type trap zone 6 across device, special
Sign is, in the P type trap zone 6, is provided with multiple grooves 7 being mutually parallel, and the depth of groove 7 is less than P type trap zone 6
Depth is equipped with the conductive polycrystalline silicon 8 for being located at center floating and the grid oxygen for wrapping up the conductive polycrystalline silicon 8 in the groove 7
Layer 9.
In the present embodiment, it is equipped with field oxygen layer 13 in the N-type epitaxy layer 4, field plate is not provided in the field oxygen layer 13
12, the side of active area 001 is provided with emitter metal 11 in the termination environment 002, the emitter metal 11 passes through
Through-hole in the oxygen layer 13 of field is electrically connected with the P type trap zone 6, and passivation layer 14 is covered on 002 surface of the termination environment.
As shown in fig. 6, being the embodiment of the present invention 1 and traditional structure（Such as Fig. 2）Surface potential distribution in device breakdown
Figure.Six parallel grooves 7 are provided in embodiment 1 in the P type trap zone 6, as seen from the figure, the potential at the main knot of traditional structure 10
For 0V, and the potential at 1 main knot 10 of the embodiment of the present invention is about 200V, it means that the field limiting ring of structure of the invention is subjected to
Pressure resistance to lack 200V compared to the field limiting ring of traditional structure, so number ratio Fig. 2 of the field limiting ring of 1 structure of the embodiment of the present invention
The field limiting ring of middle traditional structure is 2 few, and therefore, in the case where bearing identical pressure resistance, structure of the invention can be substantially reduced end
The width of end structure, and then reduce production cost.
The present invention and its embodiments have been described above, description is not limiting, shown in attached drawing also only
It is one of embodiments of the present invention, practical structures are not limited thereto.All in all if those skilled in the art
It is enlightened by it, without departing from the spirit of the invention, is not inventively designed similar with the technical solution
Frame mode and embodiment, are within the scope of protection of the invention.
Claims (9)
1. a kind of terminal structure of with groove includes the collector electrode metal for drawing collector（1）And it is located at the collector
Metal（1）First conductive type epitaxial layer of top（4）, in first conductive type epitaxial layer（4）Surface sets that there are one the
Two conduction type well regions（6）And surround the second conduction type well region（6）Several the second conduction type field limiting rings（5）,
It is characterized in that, in the second conduction type well region（6）Interior several grooves parallel to each other of setting（7）, in the groove
（7）The interior conductive polycrystalline silicon being equipped with positioned at center floating（8）And the package conductive polycrystalline silicon（8）Grid oxide layer（9）.
2. a kind of terminal structure of with groove according to claim 1, which is characterized in that outside first conduction type
Prolong layer（4）It is equipped with field oxygen layer（13）, in the field oxygen layer（13）It is equipped with several field plates（12）, one of field plate（12）
Through-hole and the second conduction type well region can be passed through（6）Electrical connection, may be alternatively provided as floating state, remaining field plate（12）It can lead to
Cross through-hole and the second conduction type field limiting ring（5）Electrical connection, may be alternatively provided as floating state.
3. a kind of terminal structure of with groove according to claim 1, which is characterized in that the second conduction type well region
（6）And the second conduction type field limiting ring（5）From first conductive type epitaxial layer（4）Surface extends to inside it, and institute
State the second conduction type well region（6）Across the active area of device（001）The termination environment and（002）.
4. a kind of terminal structure of with groove according to claim 1, which is characterized in that in termination environment（002）It is close to have
Source region（001）Side be provided with emitter metal（11）, the emitter metal（11）Pass through field oxygen layer（13）Interior through-hole
With the second conduction type well region（6）Electrical connection.
5. a kind of terminal structure of with groove according to claim 1, which is characterized in that in the termination environment（002）Table
Face is covered with passivation layer（14）.
6. a kind of terminal structure of with groove according to claim 1, which is characterized in that second conduction type field limits
Ring（5）It can be not provided with, the field plate（12）It can not also be arranged.
7. a kind of terminal structure of with groove according to claim 1, which is characterized in that the groove（7）Depth can
More than the second conduction type well region（6）Depth.
8. a kind of terminal structure of with groove according to claim 1, which is characterized in that the terminal structure includes N-type
The terminal structure of the terminal structure and p-type power semiconductor of power semiconductor, for N-type power semiconductor
Terminal structure, first conduction type are N-type, and second conduction type is p-type, for the terminal of P-type semiconductor device
Structure, the first conduction type are p-type, and the second conduction type is N-type.
9. a kind of terminal structure of with groove according to claim 1, which is characterized in that the terminal structure of the with groove
Device include IGBT device and MOSFET element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810307605.3A CN108321187B (en) | 2018-04-08 | Terminal structure with groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810307605.3A CN108321187B (en) | 2018-04-08 | Terminal structure with groove |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN108321187A true CN108321187A (en) | 2018-07-24 |
| CN108321187B CN108321187B (en) | 2024-05-10 |
Family
ID=
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854072A (en) * | 2020-01-07 | 2020-02-28 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
| CN112071905A (en) * | 2020-09-07 | 2020-12-11 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN113764527A (en) * | 2021-09-06 | 2021-12-07 | 华羿微电子股份有限公司 | MOSFET device groove terminal and preparation method |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| US20110121386A1 (en) * | 2009-11-20 | 2011-05-26 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| CN102130150A (en) * | 2010-12-13 | 2011-07-20 | 成都方舟微电子有限公司 | Junction terminal structure of semiconductor device |
| US20120211831A1 (en) * | 2009-11-20 | 2012-08-23 | Force Mos Technology Co. Ltd. | Trench mosfet with trenched floating gates in termination |
| US20150187877A1 (en) * | 2013-12-27 | 2015-07-02 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
| CN207967001U (en) * | 2018-04-08 | 2018-10-12 | 无锡新洁能股份有限公司 | A kind of terminal structure of with groove |
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20110121386A1 (en) * | 2009-11-20 | 2011-05-26 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| US20120211831A1 (en) * | 2009-11-20 | 2012-08-23 | Force Mos Technology Co. Ltd. | Trench mosfet with trenched floating gates in termination |
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| CN102130150A (en) * | 2010-12-13 | 2011-07-20 | 成都方舟微电子有限公司 | Junction terminal structure of semiconductor device |
| US20150187877A1 (en) * | 2013-12-27 | 2015-07-02 | Samsung Electro-Mechanics Co., Ltd. | Power semiconductor device |
| CN207967001U (en) * | 2018-04-08 | 2018-10-12 | 无锡新洁能股份有限公司 | A kind of terminal structure of with groove |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854072A (en) * | 2020-01-07 | 2020-02-28 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
| CN112071905A (en) * | 2020-09-07 | 2020-12-11 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN112071905B (en) * | 2020-09-07 | 2021-05-25 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN113764527A (en) * | 2021-09-06 | 2021-12-07 | 华羿微电子股份有限公司 | MOSFET device groove terminal and preparation method |
| CN113764527B (en) * | 2021-09-06 | 2023-03-24 | 华羿微电子股份有限公司 | MOSFET device groove terminal and preparation method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10553713B2 (en) | Semiconductor device | |
| CN103367356B (en) | There is the semiconductor element of nitride layer | |
| EP2560206A1 (en) | Semiconductor device | |
| CN103258847B (en) | Reverse block (RB)-insulated gate bipolar transistor (IGBT) device provided with double-faced field stop with buried layers | |
| WO2021088232A1 (en) | Silicon carbide mosfet device and cell structure thereof | |
| US9871109B2 (en) | Semiconductor device | |
| CN109244136B (en) | Slot-bottom Schottky contact SiC MOSFET device | |
| CN104282686B (en) | Wide band gap semiconductor device | |
| CN107195678B (en) | A kind of superjunction IGBT of carrier storage enhancing | |
| JP4488935B2 (en) | High voltage semiconductor device | |
| CN101969068A (en) | Edge terminal structure of high-voltage power semiconductor device | |
| CN108538912B (en) | Trench step gate IGBT chip | |
| CN207183281U (en) | A kind of groove grid super node semiconductor devices of adjustable switch speed | |
| CN101771085A (en) | High-voltage semi-conductor device and manufacturing method thereof | |
| CN204130542U (en) | Power semiconductor | |
| JP5735611B2 (en) | SiC semiconductor device | |
| CN110444587A (en) | Terminal structure with buried layer | |
| CN207967001U (en) | A kind of terminal structure of with groove | |
| CN108321187A (en) | A kind of terminal structure of with groove | |
| CN109841666A (en) | Layout for needle-shaped unit groove MOSFET | |
| US20230006044A1 (en) | Cell structure of silicon carbide mosfet device, and power semiconductor device | |
| CN207818562U (en) | Semiconductor element and semiconductor device | |
| CN208352295U (en) | A kind of MOS control thyristor chip | |
| JP2018078153A (en) | Semiconductor device | |
| CN111244151B (en) | Super junction terminal structure of power semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant |