CN108321187B - Terminal structure with groove - Google Patents
Terminal structure with groove Download PDFInfo
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- CN108321187B CN108321187B CN201810307605.3A CN201810307605A CN108321187B CN 108321187 B CN108321187 B CN 108321187B CN 201810307605 A CN201810307605 A CN 201810307605A CN 108321187 B CN108321187 B CN 108321187B
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- well region
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- 239000002184 metal Substances 0.000 claims abstract description 23
- 229910052751 metal Inorganic materials 0.000 claims abstract description 23
- 239000004065 semiconductor Substances 0.000 claims abstract description 14
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 11
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 238000002161 passivation Methods 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 4
- 150000002739 metals Chemical class 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7398—Vertical transistors, e.g. vertical IGBT with both emitter and collector contacts in the same substrate side
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention belongs to the technical field of manufacturing of semiconductor devices, and relates to a terminal structure with a groove, which comprises collector metal for leading out the collector and a first conductive type epitaxial layer positioned above the collector metal, wherein a second conductive type well region and a plurality of second conductive type field limiting rings surrounding the second conductive type well region are arranged on the surface of the first conductive type epitaxial layer; the trench structure is added in the well region to increase the potential at the main junction, so that the number of field limiting rings is reduced, the width of a device terminal is further reduced, the area of the device terminal is reduced while the voltage endurance capability of the device is ensured, the area of the whole device is further reduced, the manufacturing cost of the device is reduced, and the cost performance is improved.
Description
Technical Field
The invention relates to a terminal structure of a semiconductor device, in particular to a terminal structure with a groove, and belongs to the technical field of manufacturing of semiconductor devices.
Background
In the field of power semiconductor devices, the design of terminals is closely related to the withstand voltage and reliability of the device, the voltage borne by the terminals can be divided into transverse voltage and longitudinal voltage, the main factor for determining the longitudinal voltage is the thickness of an epitaxial layer of the device, the main factor for determining the transverse voltage is the width of the terminal of the device, the terminal structures of the existing devices are all terminals of a field limiting ring structure, as shown in fig. 2, the terminal structures of IGBT devices are exemplified by collector metals, second conductive type epitaxial layers are arranged on collector metals, first conductive type buffer layers are arranged on the second conductive type epitaxial layers, first conductive type epitaxial layers are arranged on the first conductive type buffer layers, a second conductive type well region and a plurality of second conductive type field limiting rings are arranged on the surface of the first conductive type epitaxial layers, the second conductive type field limiting rings are positioned on the periphery of the terminal structures and surround the second conductive type well region, the potentials at the main junction 10 at the edges of the second conductive type well region are determined by the initial potentials of the terminal structures, the initial potentials of the device are high, the number of the terminal structures are smaller than the terminal structures, the terminal structures are required by the terminal structures, the terminal structures are narrower than the terminal structures, and the current field limiting rings are required by the terminal structures, and the terminal structures are required by the terminal structures are greatly reduced, and the cost of the terminal structures is greatly limited by the field limiting rings is greatly reduced.
Disclosure of Invention
The invention aims to overcome the defects in the prior art, and provides a terminal structure with a groove, wherein the potential at a main junction is increased by adding the groove structure in a well region, the number of field limiting rings is reduced, and then the width of a device terminal is reduced.
In order to achieve the technical purpose, the technical scheme of the invention is as follows: the terminal structure with the groove comprises collector metal for leading out the collector and a first conductive type epitaxial layer positioned above the collector metal, wherein a second conductive type well region and a plurality of second conductive type field limiting rings surrounding the second conductive type well region are arranged on the surface of the first conductive type epitaxial layer.
Further, a field oxide layer is disposed on the first conductive type epitaxial layer, a plurality of field plates are disposed on the field oxide layer, one of the field plates can be electrically connected with the second conductive type well region through a through hole, and can be set in a floating state, and the remaining field plates can be electrically connected with the second conductive type field limiting ring through a through hole, and can be set in a floating state.
Further, the second conductivity type well region and the second conductivity type field stop ring each extend from the first conductivity type epitaxial layer surface to the inside thereof, and the second conductivity type well region spans the active region and the termination region of the device.
Further, an emitter metal is arranged on one side, close to the active region, of the terminal region, and the emitter metal is electrically connected with the second conductive type well region through a through hole in the field oxide layer.
Further, a passivation layer is covered on the surface of the terminal area.
Further, the second conductivity type field limiting ring may not be provided, and the field plate may not be provided.
Further, the depth of the trench may be greater than the depth of the second conductivity type well region.
Further, the terminal structure comprises a terminal structure of an N-type power semiconductor device and a terminal structure of a P-type power semiconductor device, wherein the first conductive type is N-type for the terminal structure of the N-type power semiconductor device, the second conductive type is P-type, and the first conductive type is P-type and the second conductive type is N-type for the terminal structure of the P-type semiconductor device.
Further, the devices of the grooved termination structure include IGBT devices and MOSFET devices.
The invention has the following advantages:
1) Compared with the traditional terminal structure, the invention has the advantages that the plurality of grooves containing conductive polysilicon are arranged in the second conductive type well region, so that the initial potential at the edge main junction of the second conductive type well region is obviously increased, the number of field limiting rings arranged can be reduced or even not arranged under the condition that the device withstand voltage is the same, the width of the terminal structure is greatly reduced, the occupied area of the terminal structure is reduced when the area of a chip is fixed, the occupied area of an active region is increased, and the on resistance of the device is reduced; the area of the active area is unchanged, the width of the terminal is reduced, the area of the whole chip is reduced, the production cost is reduced, and the cost performance of the chip is improved;
2) The manufacturing process of the terminal structure of the invention is compatible with the existing process.
Drawings
The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification, illustrate the invention and together with the description serve to explain, without limitation, the invention. In the drawings:
fig. 1 is a schematic top view of a power semiconductor device.
Fig. 2 is a schematic structural view of a conventional terminal structure.
Fig. 3 is a schematic structural diagram of a grooved terminal structure according to embodiment 1 of the present invention.
Fig. 4 is a schematic structural diagram of a grooved terminal structure according to embodiment 2 of the present invention.
Fig. 5 is a schematic structural diagram of a grooved terminal structure according to embodiment 3 of the present invention.
Fig. 6 is a graph showing the surface potential profile of the inventive structure (fig. 3) and conventional structure (fig. 2) when they are broken down.
Reference numerals illustrate: 001-an active region; 002-a termination region; 1-collector metal; 2-a collector region of the second conductivity type; 3-a buffer layer of the first conductivity type; 4-an epitaxial layer of the first conductivity type; 5-a field limiting ring of the second conductivity type; 6-a second conductivity type well region; 7-a groove; 8-conductive polysilicon; 9-a gate oxide layer; 10-main junction; 11-emitter metal; 12-field plate; 13-a field oxide layer; 14-passivation layer.
Detailed Description
The invention will be further described with reference to the following specific drawings and examples.
The present invention is not limited to the following embodiments, and the drawings referred to in the following description are provided to make it possible to understand the content of the present invention, that is, the present invention is not limited to the device structures illustrated in the drawings, and is applicable to both IGBT devices and MOSFET devices.
As shown in fig. 1, a schematic top view of a semiconductor device includes an active region 001 and a terminal region 002 surrounding the active region 001.
As shown in fig. 3, in embodiment 1, an IGBT device is taken as an example, the first conductivity type is N type, the second conductivity type is P type, and a terminal structure with a trench includes a collector metal 1 for leading out a collector, a P-type collector region 2, an N-type buffer layer 3 located on the P-type collector region 2, and an N-type epitaxial layer 4 located on the N-type buffer layer 3 are sequentially disposed on the collector metal 1, a P-type well region 6 and a plurality of P-type field limiting rings 5 surrounding the P-type well region 6 are disposed on the surface of the N-type epitaxial layer 4, the P-type well region 6 and the P-type field limiting rings 5 are located at the periphery of the terminal structure, and the P-type well region 6 and the P-type field limiting rings 5 extend from the surface of the N-type epitaxial layer 4 to the inside thereof, and the P-type well region 6 spans the active region 001 and the terminal region 002 of the device, and is characterized in that six parallel trenches 7 are disposed in the P-type well region 6, the depth of the trenches 7 is smaller than the depth of the P-type well region 6, and a polysilicon layer 8 is disposed in the depth of the P-type well region 6, and the polysilicon layer 8 is located at the center of the conductive gate 8 and surrounds the polysilicon layer 8;
The width of the grooves 7 in this embodiment 1 is about 1 μm, and the pitch between the grooves 7 is about 5 μm;
a field oxide layer 13 is arranged on the N-type epitaxial layer 4, a plurality of field plates 12 are arranged on the field oxide layer 13, one of the field plates 12 is electrically connected with the P-type well region 6 through a through hole, the rest of the field plates 12 are electrically connected with the P-type field limiting ring 5 through a through hole, an emitter metal 11 is arranged on one side of the terminal region 002 close to the active region 001, the emitter metal 11 is electrically connected with the P-type well region 6 through a through hole in the field oxide layer 13, and a passivation layer 14 is covered on the surface of the terminal region 002;
in the case of MOSFET devices, only an N-type substrate is provided between the collector metal 1 and the N-type epitaxial layer 4.
As shown in fig. 4, in embodiment 2, in the IGBT device, the first conductivity type is N type, the second conductivity type is P type, only one P type well region 6 is provided on the surface of the N type epitaxial layer 4, no P type field limiting ring 6 is provided, the P type well region 6 extends from the surface of the N type epitaxial layer 4 to the inside thereof, and the P type well region 6 spans the active region 001 and the terminal region 002 of the device, and is characterized in that twenty trenches 7 parallel to each other are provided in the P type well region 6, the depth of the trenches 7 is smaller than the depth of the P type well region 6, and conductive polysilicon 8 floating in the central region and a gate oxide layer 9 wrapping the conductive polysilicon 8 are provided in the trenches 7;
The N-type epitaxial layer 4 is provided with a field oxide layer 13, the field oxide layer 13 is provided with a field plate 12, the field plate 12 is electrically connected with the P-type well region 6 through a through hole, one side of the terminal region 002, which is close to the active region 001, is provided with an emitter metal 11, the emitter metal 11 is electrically connected with the P-type well region 6 through a through hole in the field oxide layer 13, and the surface of the terminal region 002 is covered with a passivation layer 14.
As shown in fig. 5, embodiment 3 takes an IGBT device as an example, where the first conductivity type is N-type, the second conductivity type is P-type, only one P-type well region 6 is provided on the surface of the N-type epitaxial layer 4, no P-type field limiting ring 6 is provided, the P-type well region 6 extends from the surface of the N-type epitaxial layer 4 to the inside thereof, and the P-type well region 6 spans the active region 001 and the terminal region 002 of the device, and is characterized in that a plurality of trenches 7 parallel to each other are provided in the P-type well region 6, the depth of the trenches 7 is smaller than the depth of the P-type well region 6, and conductive polysilicon 8 floating in the central region and a gate oxide layer 9 wrapping the conductive polysilicon 8 are provided in the trenches 7.
In this embodiment, a field oxide layer 13 is disposed on the N-type epitaxial layer 4, a field plate 12 is not disposed on the field oxide layer 13, an emitter metal 11 is disposed on a side of the termination region 002 near the active region 001, the emitter metal 11 is electrically connected to the P-type well region 6 through a via hole in the field oxide layer 13, and a passivation layer 14 is covered on the surface of the termination region 002.
As shown in fig. 6, the surface potential distribution diagram of the device breakdown of the embodiment 1 and the conventional structure (as shown in fig. 2) of the present invention is shown. In embodiment 1, six parallel trenches 7 are disposed in the P-type well region 6, and as can be seen from the figure, the potential at the main junction 10 of the conventional structure is 0V, while the potential at the main junction 10 of embodiment 1 of the present invention is about 200V, which means that the field limiting ring of the structure of the present invention needs to withstand a withstand voltage of 200V less than that of the field limiting ring of the conventional structure, so that the number of field limiting rings of the structure of embodiment 1 of the present invention is 2 less than that of the field limiting ring of the conventional structure in fig. 2, and therefore, the structure of the present invention can significantly reduce the width of the terminal structure under the condition of withstanding the same withstand voltage, thereby reducing the production cost.
The invention and its embodiments have been described above with no limitation, and the actual construction is not limited to the embodiments of the invention as shown in the drawings. In summary, if one of ordinary skill in the art is informed by this disclosure, a structural manner and an embodiment similar to the technical solution should not be creatively devised without departing from the gist of the present invention.
Claims (8)
1. The terminal structure with the groove comprises collector metal (1) for leading out the collector and a first conductive type epitaxial layer (4) positioned above the collector metal (1), wherein a second conductive type well region (6) and a plurality of second conductive type field limiting rings (5) surrounding the second conductive type well region (6) are arranged on the surface of the first conductive type epitaxial layer (4), and the terminal structure is characterized in that a plurality of grooves (7) which are parallel to each other are arranged in the second conductive type well region (6), and conductive polysilicon (8) floating in a central region and a gate oxide layer (9) wrapping the conductive polysilicon (8) are arranged in the grooves (7).
2. A trench termination structure according to claim 1, characterized in that a field oxide layer (13) is provided on the first conductivity type epitaxial layer (4), that a number of field plates (12) are provided on the field oxide layer (13), wherein one field plate (12) is electrically connected to the second conductivity type well region (6) through a via, or is set in a floating state, and the remaining field plates (12) are electrically connected to the second conductivity type field stop ring (5) through a via, or are set in a floating state.
3. A trench termination structure according to claim 1, characterized in that the second conductivity type well region (6) and the second conductivity type field stop ring (5) each extend from the surface of the first conductivity type epitaxial layer (4) into the interior thereof, and the second conductivity type well region (6) spans the active region (001) and the termination region (002) of the device.
4. A trench termination structure according to claim 1, characterized in that an emitter metal (11) is provided at the side of the termination region (002) close to the active region (001), said emitter metal (11) being electrically connected to the well region (6) of the second conductivity type through a via in the field oxide layer (13).
5. A grooved termination structure according to claim 3, characterized in that the surface of the termination region (002) is covered with a passivation layer (14).
6. A trenched termination structure as claimed in claim 1, characterized in that the depth of the trench (7) is greater than the depth of the well region (6) of the second conductivity type.
7. The trenched termination structure of claim 1 wherein the termination structure comprises an N-type power semiconductor device termination structure and a P-type power semiconductor device termination structure, wherein the first conductivity type is N-type for the N-type power semiconductor device termination structure and the second conductivity type is P-type for the P-type semiconductor device termination structure, the first conductivity type is P-type and the second conductivity type is N-type.
8. The trenched termination structure of claim 1 wherein the devices of the trenched termination structure comprise IGBT devices and MOSFET devices.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810307605.3A CN108321187B (en) | 2018-04-08 | 2018-04-08 | Terminal structure with groove |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810307605.3A CN108321187B (en) | 2018-04-08 | 2018-04-08 | Terminal structure with groove |
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| Publication Number | Publication Date |
|---|---|
| CN108321187A CN108321187A (en) | 2018-07-24 |
| CN108321187B true CN108321187B (en) | 2024-05-10 |
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| CN201810307605.3A Active CN108321187B (en) | 2018-04-08 | 2018-04-08 | Terminal structure with groove |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110854072B (en) * | 2020-01-07 | 2022-11-04 | 四川立泰电子有限公司 | Manufacturing process of low electromagnetic interference power device terminal structure |
| CN112071905B (en) * | 2020-09-07 | 2021-05-25 | 上海陆芯电子科技有限公司 | Terminal structure of semiconductor device and insulated gate bipolar transistor |
| CN113764527B (en) * | 2021-09-06 | 2023-03-24 | 华羿微电子股份有限公司 | MOSFET device groove terminal and preparation method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| CN102130150A (en) * | 2010-12-13 | 2011-07-20 | 成都方舟微电子有限公司 | Junction terminal structure of semiconductor device |
| CN207967001U (en) * | 2018-04-08 | 2018-10-12 | 无锡新洁能股份有限公司 | A kind of terminal structure of with groove |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8564053B2 (en) * | 2009-11-20 | 2013-10-22 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates in termination |
| US7989887B2 (en) * | 2009-11-20 | 2011-08-02 | Force Mos Technology Co., Ltd. | Trench MOSFET with trenched floating gates as termination |
| KR20150076814A (en) * | 2013-12-27 | 2015-07-07 | 삼성전기주식회사 | Power semiconductor device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005475A (en) * | 2010-10-15 | 2011-04-06 | 无锡新洁能功率半导体有限公司 | Insulated gate bipolar transistor (IGBT) with improved terminal and manufacturing method thereof |
| CN102130150A (en) * | 2010-12-13 | 2011-07-20 | 成都方舟微电子有限公司 | Junction terminal structure of semiconductor device |
| CN207967001U (en) * | 2018-04-08 | 2018-10-12 | 无锡新洁能股份有限公司 | A kind of terminal structure of with groove |
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