CN201608184U - Groove type power MOS device with improved terminal protection structure - Google Patents
Groove type power MOS device with improved terminal protection structure Download PDFInfo
- Publication number
- CN201608184U CN201608184U CN2009203532160U CN200920353216U CN201608184U CN 201608184 U CN201608184 U CN 201608184U CN 2009203532160 U CN2009203532160 U CN 2009203532160U CN 200920353216 U CN200920353216 U CN 200920353216U CN 201608184 U CN201608184 U CN 201608184U
- Authority
- CN
- China
- Prior art keywords
- groove
- conductive type
- connecting line
- dividing
- terminal protection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
The utility model relates to a groove type power MOS device, in particular to a groove type power MOS device with an improved terminal protection structure. A cell region positioned on a semiconductor base plate and the terminal protection structure are arranged on the overhead view plane of the MOS device, wherein the cell region comprises a plurality of cells in parallel connection and is positioned in the center region of the semiconductor base plate, the outer periphery of the cell region is provided with the terminal protection structure, the cells of the cell region are connected in parallel into a whole body through conductive polysilicon positioned in the groove, the terminal protection structure comprises a pressure dividing protection region positioned at an inner ring of the terminal protection structure and a stop protection region positioned at an outer ring of the terminal protection structure, the pressure dividing protection region adopts a groove structure, the groove structure comprises at least two pressure dividing grooves, and an ohm contact hole is arranged between the two adjacent pressure dividing grooves, so a second conductive type layer between the two adjacent pressure dividing grooves has the electric potential equal to the source electrode, and the pressure dividing capability of the terminal protection region is improved. The pressure dividing protection region of the utility model can averagely distribute the electric field, and can reduce the size of the protection region, so the area of the pipe core is reduced, and the cost is reduced. The utility model is compatible with the existing groove type power MOS process, and the manufacture is convenient.
Description
Technical field
The utility model relates to a kind of groove type power MOS device, especially a kind of groove type power MOS device with improved terminal protection structure.
Background technology
Improve device performance, reducing cost is to promote constantly two main driving sources of development of power MOS (Metal Oxide Semiconductor) device, and the development of this two aspect depends primarily on processes level and designs level.As an important component part of power MOS (Metal Oxide Semiconductor) device, terminal protection structure has not only directly influenced device performance, and plays an important role to reducing cost.In the prior art; described terminal protection structure; as described in Chinese patent ZL200710302461.4 and ZL 200810019085.2, its terminal protection structure feature is that trap runs through whole terminal, and deeply the groove to epitaxial loayer is divided into several separate well regions with well region.
Yet, as shown in Figure 1, being provided with two dividing groove 16 in the described dividing potential drop protection zone 2, the P-trap 7 that described two dividing groove are 16 is a floating state, promptly the P-trap 7 of 16 of dividing groove does not link to each other with any electrode with definite current potential.When the P-trap that dividing groove is 16 is floated, there is following problem:
One, the P-trap potential of floating is subject to the external environment influence.The MOS device is grid source end short circuit ground connection; when drain electrode 14 adds forward bias voltage (corresponding to N type device); the voltage of MOS device mainly by on the cellular region 1 corresponding on outermost cellular groove 17 and the dividing potential drop protection zone 2 corresponding near sharing corresponding to dividing groove 16 on the P-trap 7 of 16 of the dividing groove of cellular region 1, the dividing potential drop protection zone 2 near cellular region 1; and the dividing potential drop of all the other the P-traps 7 on the dividing potential drop protection zone 2 and 16 pairs of forward bias voltages of dividing groove is very little, and simulation result as shown in Figure 4.The extremely uneven structure of this electric-field intensity distribution when improving the forward bias voltage of drain electrode 14, may will cause the MOS device in the regional area premature breakdown, and the breakdown performance of device is worsened.
Two, when adding forward bias voltage in the drain electrode 14; the voltage of MOS device mainly by on the cellular region 1 corresponding on outermost cellular groove 17 and the dividing potential drop protection zone 2 corresponding near on the P-trap 7 of 16 of the dividing groove of cellular region 1, the dividing potential drop protection zone 2 when sharing near the dividing groove 16 of cellular region 1; remaining P-trap 7 and dividing groove 16 do not reach the purpose of dividing potential drop design on the described dividing potential drop protection zone 2, have wasted the area in terminal protection district.For power MOS (Metal Oxide Semiconductor) device, terminal protection structure has occupied 20% of die area at least, so the waste of area can cause the raising of cost; If keep total die area constant, will sacrifice the cellular region area and go to remedy, so also can increase the conducting resistance of device.
Summary of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art; a kind of groove type power MOS device with improved terminal protection structure is provided; itself and existing groove manufacturing process compatibility; do not need to increase the photoetching number of plies; can improve device withstand voltage and stability thereof, and can dwindle die area and reduce cost.
The technical scheme that provides according to the utility model, described groove type power MOS device with improved terminal protection structure, on the top plan view of described MOS device, comprise the cellular region and the terminal protection structure that are positioned on the semiconductor substrate, described cellular region comprises the cellular of some parallel connections, and is positioned at the center of semiconductor substrate; The periphery of described cellular region is provided with terminal protection structure, in the described cellular region cellular by being positioned at groove conductive polycrystalline silicon and unify; Described terminal protection structure comprises the dividing potential drop protection zone that is positioned at its inner ring and is positioned at the protection zone of ending of its outer ring; Its innovative point is:
On the cross section of terminal protection structure, groove structure is adopted in described dividing potential drop protection zone, described groove structure comprises at least two dividing groove, dividing groove is positioned at second conductive type layer, the degree of depth stretches into first conductive type epitaxial layer under second conductive type layer, the growth of dividing groove wall surface has the insulated gate oxide layer, in described dividing groove, be deposited with conductive polycrystalline silicon, the notch at dividing groove top is covered by dielectric, between described adjacent two dividing groove ohmic contact hole is set, be coated with first metal connecting line in the described ohmic contact hole, second conductive type layer that is positioned between adjacent two dividing groove contacts with first metal connecting line; Described first metal connecting line connects into equipotential with second conductive type layer and the source metal between adjacent two dividing groove, constitutes groove-shaped dividing potential drop protection zone with this;
Described first conductive type layer comprises first conductivity type substrate that is positioned at semiconductor substrate bottom and is positioned at first conductive type epitaxial layer above first conductivity type substrate, and the first conduction type injection region that is positioned at the first conductive type epitaxial layer top; Described second conductive type layer is positioned at the top of first conductive type epitaxial layer; Described source metal is positioned at above the cellular region; Described source metal and described first metal connecting line fuse;
On the cross section of terminal protection structure; adopt groove structure by the protection zone; be positioned at second conductive type layer by groove; the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; by the trench wall superficial growth insulated gate oxide layer is arranged; thereafter; in groove, be deposited with conductive polycrystalline silicon; by the groove top second metal connecting line is set; cover by dielectric by groove top all the other slot-open-sections except that second metal connecting line; be second conductive type layer of top by the groove outside with the first conductive type layer injection zone; described second metal connecting line connects into equipotential with the first conduction type injection region of ending the groove outside simultaneously with the conductive polycrystalline silicon in groove, constitutes the groove-shaped protection zone of ending with this.
When source metal was zero potential, described first metal connecting line connected into zero potential with second conductive type layer and the source metal between adjacent two dividing groove.On the cross section of terminal protection structure, the described first conductive type layer substrate is provided with drain electrode end.On the cross section of terminal protection structure, do not contact between described first metal connecting line and second metal connecting line.On the top plan view of terminal protection structure, be provided with gate metal between the described source metal and first metal connecting line.
Described " first conduction type " and " second conduction type " are among both, and for N type metal-oxide-semiconductor field effect transistor, first conduction type refers to the N type, and second conduction type is the P type; For P type metal-oxide-semiconductor field effect transistor, first conduction type is just in time opposite with N type metal-oxide-semiconductor field effect transistor with the type of the second conduction type indication.
Advantage of the present utility model and effect:
1, with second conductive type layer between two adjacent on dividing potential drop protection zone dividing groove; by offering ohmic contact hole; utilize first metal connecting line to link to each other with source metal; make second conductive type layer and source terminal keep equipotential (being zero potential when working usually); get rid of floating struction and be subject to ectocine; the unsettled situation of current potential has been guaranteed effect and stability that dividing potential drop is protected, has improved the performance of product.
2, the dividing potential drop protection zone can the mean allocation electric field, therefore can dwindle the size of protection zone, thereby reduce die area, reduces cost.
3, the utility model can with existing 4 version groove type power MOS device processing technology compatibilities; when making cellular region; form the terminal protection district together; as forming groove together; the grid oxygen filled conductive polysilicon of growing together; diffuse to form well region and heavy doping source region together, leave contact hole together, reduced complexity and the degree of difficulty made.
4, this kind improved terminal project organization and thinking can also be applied to other power discrete device, as Planar DMOS, field-effect transistor, diode, IGBT etc.
Description of drawings
Fig. 1 is the generalized section of existing power groove MOS field effect tube.
Fig. 2 is the A-A cutaway view of Fig. 3.
Fig. 3 is the top plan view hardware cloth line chart of the utility model structure.
Fig. 4 is the simulation result schematic diagram of Fig. 1 structure.
Fig. 5 is a simulation result schematic diagram of the present utility model.
Embodiment
The utility model is described in further detail below in conjunction with concrete drawings and Examples.
As Fig. 2～shown in Figure 3: with N type MOS device is example, and the utility model comprises cellular region 1, dividing potential drop protection zone 2, by protection zone 3, insulating medium layer 4, first metal connecting line 5, conductive polycrystalline silicon 6, P-trap 7, N type epitaxial loayer 8, N+ substrate 9, insulated gate oxide layer 10, N+ injection region 11, source terminal 12, gate terminal 13, drain electrode end 14, ohmic contact hole 15, dividing groove 16, cellular groove 17, by groove 18, second metal connecting line 19, source metal 20 and gate metal 21.
Fig. 3 overlooks the hardware cloth line chart of state plane for deep groove large power N type MOS device.As shown in Figure 3, MOS device center is a source metal 20, and described cellular region 1 is covered by source metal 20, and the periphery of described cellular region 1 is provided with terminal protection structure.Cellular region 1 by groove-shaped conductive polycrystalline silicon 6 with cellular and unify.The terminal protection district comprise the dividing potential drop protection zone 2 that is positioned at its inner ring and be positioned at its outer ring by protection zone 3.The described source metal 20 and first metal connecting line 5 fuse.The periphery of described first metal connecting line 5 is second metal connecting line 19, and the described protection zone 3 of ending is covered by second metal connecting line 19.The interval that described source metal 20, gate metal 21, first metal connecting line 5 and second metal connecting line are 19 is dividing potential drop protection zone 2.
Fig. 2 is the A-A cutaway view of Fig. 3.As shown in Figure 2, on the cross section, groove structure is adopted in dividing potential drop protection zone 2, dividing groove 16 is positioned at doped with P trap layer 7, the degree of depth stretches into the light dope N type epitaxial loayer 8 of P trap layer 7 below, the growth of dividing groove 16 inner wall surface has insulated gate oxide layer 10, is deposited with conductive polycrystalline silicon 6 in the dividing groove 16, and the notch at dividing groove 16 tops is covered by insulating medium layer 4; Comprise at least two dividing groove 16 in the described dividing potential drop protection zone 2; 16 of described adjacent two dividing groove are provided with ohmic contact hole 15; be provided with first metal connecting line 5 in the described ohmic contact hole 15; first metal connecting line 5 connects into equipotential with the P trap layer 7 of 16 of dividing groove with source terminal 12; make the current potential of the P trap layer 7 of 16 of dividing groove have definite electromotive force; the P trap layer 7 that dividing groove is 16 is not a floating state, constitutes the dividing potential drop protection zone 2 of groove-shaped conductive polycrystalline silicon with this.
On the cross section, described by protection zone 3 employing groove structures, the described width that ends the width of groove 18 greater than cellular groove 17 in the cellular region 1.The described groove 18 that ends is positioned at doped with P trap layer 7, the degree of depth stretches into the light dope N type epitaxial loayer 8 of P trap layer 7 below, insulated gate oxide layer 10 is arranged, be deposited with conductive polycrystalline silicon 6 in groove 18 by the growth of groove 18 inner wall surface, the top is provided with second metal connecting line 19.Described second metal connecting line 19 will be connected the position equipotential by the conductive polycrystalline silicon in the groove 18 6 with the P trap layer 8 in the outside, or second metal connecting line 19 will connect into equipotential by the N+ injection region 11 and the P trap layer 7 in the conductive polycrystalline silicon in the groove 18 6 and the outside, make the leakage current that can more effectively reduce the surface by protection zone 3, help improving the stability of MOS device surface; The described groove 18 top notches that end are covered by insulating medium layer 4, constitute groove-shaped by the protection zone.
As shown in Figure 2, on the cross section, be connected with drain electrode end 14 on the described N+ substrate 9.Conductive polycrystalline silicon 6 is provided with the lead end gate terminal 13 of gate electrode in the cellular groove 17 on the described cellular region 1, source terminal 12 is set on the source metal 20, the described source metal 20 and first metal connecting line 5 fuse, and described first metal connecting line 5 does not contact with second metal connecting line 19.
The working mechanism of described improved terminal protection structure is: P trap layer 7 is present in the whole terminal protection zone, and dividing groove 16 is with isolated with P trap layer 7 by groove 18.When described N type MOS device adds forward bias voltage on drain electrode end 14, source terminal 12 is during with gate terminal 13 ground connection, the maximum field point, and promptly the Mi Qu of power line exists and the main infall of tying corresponding cellular groove 17 with it.Described master becomes the P trap of cellular region 1 outermost cellular groove 17 and the PN junction that N type epitaxial loayer 8 is formed.Forward bias voltage on the described drain electrode end 14, the PN junction that N type epitaxial loayer 8 and P trap layer 7 are constituted is anti-inclined to one side, and depletion layer can be to lightly doped N type epitaxial loayer 8 expansions.When the value of main knot reversed bias voltage greatly when making depletion layer expand to dividing groove 16 on the dividing potential drop protection zone 2; main knot electronics flow on the dividing groove 16; it is electronegative that dividing potential drop protection zone 2 is become by electric neutrality, and described negative electrical charge is distributed in dividing groove 16 corresponding to the outer wall near cellular region 1 outermost cellular groove 17.P trap layer 7 corresponding to 16 of adjacent two dividing groove on the described dividing potential drop protection zone 2 has constituted anti-inclined to one side PN junction equally with N type epitaxial loayer 8,16 of adjacent two dividing groove are passed through ohmic contact hole 15 and are linked to each other with source terminal 12, make the P trap layer 7 of 16 of adjacent two dividing groove be zero potential; When the depletion layer of described main knot expands to dividing potential drop protection zone 2 corresponding near the dividing groove 16 of outermost cellular groove 17 time; the depletion layer that adjacent dividing groove is 16 is connected with main knot depletion layer; the curvature that exhausts aspect becomes big; the majority carrier that dividing groove is 16 flows into depletion layer; the electric field neutralisation of 16 generations of dividing groove the horizontal component of electric field of main knot part, played the purpose of dividing potential drop.P trap layer 7 by 16 of dividing groove links to each other with source terminal 12; P trap layer 7 electromotive force that make 16 of dividing groove are zero, have improved the ability of dividing potential drop protection zone 2 dividing potential drops, make the whole M OS device can minification; can guarantee simultaneously the voltage endurance capability of MOS device, reduce the MOS device cost.
As shown in Figure 4 and Figure 5, under the same terms, to grid 13, the source electrode 12 short circuit ground connection of the MOS device and the MOS device of the present utility model of existing structure, drain electrode end 14 adds forward voltage, obtains the distribution schematic diagram of potential lines on the MOS device.As shown in Figure 4 and Figure 5, be positioned at the depletion layer that 22 in dotted line on P trap layer 7 and the N type epitaxial loayer 8 has constituted the reverse bias PN junction, the dense cluster shape solid line 23 in the depletion layer is a potential lines, and the dense degree of potential lines has been reacted electric field strength herein.As can be seen from Figure 4; the problem that the MOS device of existing structure exists is: the potential lines of the overwhelming majority in the described depletion layer dividing potential drop protection zone 2 corresponding near the left side outer wall of the dividing groove 16 of cellular region 1 and above insulating medium layer 4 concentrate convergence; and the outer wall corresponding to the dividing groove 16 at float the P trap layer 7 and the described P of floating trap layer 7 two ends of 16 of adjacent two dividing groove only is distributed with the minority potential lines in the dividing potential drop protection zone 2; therefore can cause whole dividing potential drop protection zone Electric Field Distribution extremely inhomogeneous, occur too early partial breakdown easily.As shown in Figure 5; the utility model is provided with ohmic contact hole 15 16 of adjacent two dividing groove, and when making drain electrode end 14 add forward voltage, potential lines is divided equally in whole dividing potential drop protection zone; thereby the reduction local electric field strength, the useful life and the scope of application that help prolonging the MOS device.
By on insulating medium layer 4, increasing a photoetching window, when photoetching corrosion, form ohmic contact hole 15, to the link to each other P trap layer 7 of 16 of two dividing groove of first metal connecting line 5 links to each other with source terminal 12, make the P trap layer 7 of 16 of dividing groove not be floating state, increased the dividing potential drop ability, technological operation simultaneously is simple, does not increase the photoetching cost.
Claims (5)
1. one kind has the groove type power MOS device that improved terminal is protected structure, on the top plan view of described MOS device, comprise the cellular region and the terminal protection structure that are positioned on the semiconductor substrate, described cellular region comprises the cellular of some parallel connections, and is positioned at the center of semiconductor substrate; The periphery of described cellular region is provided with terminal protection structure, the cellular in the described cellular region by being positioned at groove conductive polycrystalline silicon and unify; Described terminal protection structure comprises the dividing potential drop protection zone that is positioned at its inner ring and is positioned at the protection zone of ending of its outer ring; It is characterized in that:
On the cross section of terminal protection structure, groove structure is adopted in described dividing potential drop protection zone, described groove structure comprises at least two dividing groove, dividing groove is positioned at second conductive type layer, the degree of depth stretches into first conductive type epitaxial layer under second conductive type layer, the growth of dividing groove wall surface has the insulated gate oxide layer, in described dividing groove, be deposited with conductive polycrystalline silicon, the notch at dividing groove top is covered by dielectric, between described adjacent two dividing groove ohmic contact hole is set, be coated with first metal connecting line in the described ohmic contact hole, second conductive type layer that is positioned between adjacent two dividing groove contacts with first metal connecting line; Described first metal connecting line connects into equipotential with second conductive type layer and the source metal between adjacent two dividing groove, constitutes groove-shaped dividing potential drop protection zone with this;
Described first conductive type layer comprises first conductivity type substrate that is positioned at semiconductor substrate bottom and is positioned at first conductive type epitaxial layer above first conductivity type substrate, and the first conduction type injection region that is positioned at the first conductive type epitaxial layer top; Described second conductive type layer is positioned at the top of first conductive type epitaxial layer; Described source metal is positioned at above the cellular region; Described source metal and described first metal connecting line fuse;
On the cross section of terminal protection structure; adopt groove structure by the protection zone; be positioned at second conductive type layer by groove; the degree of depth stretches into first conductive type epitaxial layer of second conductive type layer below; by the trench wall superficial growth insulated gate oxide layer is arranged; thereafter; in groove, be deposited with conductive polycrystalline silicon; by the groove top second metal connecting line is set; cover by dielectric by groove top all the other slot-open-sections except that second metal connecting line; be second conductive type layer of top by the groove outside with the first conductive type layer injection zone; described second metal connecting line connects into equipotential with the first conduction type injection region of ending the groove outside simultaneously with the conductive polycrystalline silicon in groove, constitutes the groove-shaped protection zone of ending with this.
2. according to the described groove type power MOS device of claim 1, it is characterized in that: when source metal was zero potential, described first metal connecting line connected into zero potential with second conductive type layer and the source metal between adjacent two dividing groove.
3. according to the described groove type power MOS device of claim 1, it is characterized in that: on the cross section of terminal protection structure, the described first conductive type layer substrate is provided with drain electrode end.
4. according to the described groove type power MOS device of claim 1, it is characterized in that: on the cross section of terminal protection structure, do not contact between described first metal connecting line and second metal connecting line.
5. according to the described groove type power MOS device of claim 1, it is characterized in that: on the top plan view of terminal protection structure, be provided with gate metal between the described source metal and first metal connecting line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009203532160U CN201608184U (en) | 2009-12-29 | 2009-12-29 | Groove type power MOS device with improved terminal protection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009203532160U CN201608184U (en) | 2009-12-29 | 2009-12-29 | Groove type power MOS device with improved terminal protection structure |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN201608184U true CN201608184U (en) | 2010-10-13 |
Family
ID=42952887
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009203532160U Expired - Lifetime CN201608184U (en) | 2009-12-29 | 2009-12-29 | Groove type power MOS device with improved terminal protection structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN201608184U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752375B (en) * | 2009-12-29 | 2011-06-22 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
| CN104078497A (en) * | 2013-03-28 | 2014-10-01 | 深圳市力振半导体有限公司 | Power field effect transistor device structure |
-
2009
- 2009-12-29 CN CN2009203532160U patent/CN201608184U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101752375B (en) * | 2009-12-29 | 2011-06-22 | 无锡新洁能功率半导体有限公司 | Groove type power MOS device with improved terminal protective structure |
| CN104078497A (en) * | 2013-03-28 | 2014-10-01 | 深圳市力振半导体有限公司 | Power field effect transistor device structure |
| CN104078497B (en) * | 2013-03-28 | 2019-03-15 | 南京励盛半导体科技有限公司 | A kind of structure of power field effect transistor device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101752375B (en) | Groove type power MOS device with improved terminal protective structure | |
| EP2342753B1 (en) | Insulated gate bipolar transistor | |
| CN107204372A (en) | A kind of channel-type semiconductor device and manufacture method for optimizing terminal structure | |
| CN110534514B (en) | Groove-shaped terminal structure of transverse high-voltage power semiconductor device | |
| CN202839620U (en) | Super junction metal oxide semiconductor field effect transistor (MOSFET) component | |
| CN112234095B (en) | Power MOSFET device with enhanced cell design | |
| CN112164719B (en) | Low resistance device with equipotential floating groove and manufacturing method thereof | |
| JP2013069866A (en) | Semiconductor device | |
| CN114823872B (en) | Full-isolation substrate voltage-resistant power semiconductor device and manufacturing method thereof | |
| CN103022130A (en) | Semiconductor device | |
| KR20020079919A (en) | Dmos transistor structure having improved performance | |
| CN207183281U (en) | A kind of groove grid super node semiconductor devices of adjustable switch speed | |
| CN108899363B (en) | Trench gate IGBT device capable of reducing on-voltage drop and turn-off loss | |
| CN107546274B (en) | LDMOS device with step-shaped groove | |
| CN113658999A (en) | Power semiconductor device with junction-free termination technology, manufacturing method and application | |
| CN201608184U (en) | Groove type power MOS device with improved terminal protection structure | |
| CN114335170A (en) | Semiconductor power device | |
| CN113410299B (en) | High-voltage-resistance n-channel LDMOS device and preparation method thereof | |
| CN110534566B (en) | IGBT power device | |
| CN104617139A (en) | Ldmos device and manufacturing method thereof | |
| CN113659011A (en) | Integrated device based on super junction MOSFET and manufacturing method thereof | |
| CN203659876U (en) | Super junction device and semiconductor structure comprising same | |
| CN102983161A (en) | Non-buried layer double deep N well high-voltage isolation N-type LDMOS and method for manufacturing N-type LDMOS devices | |
| CN107863378B (en) | Super junction MOS device and manufacturing method thereof | |
| CN203242627U (en) | Semiconductor component, vertical MOSFET, IGBT structure and integrated semiconductor device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| AV01 | Patent right actively abandoned |
Granted publication date: 20101013 Effective date of abandoning: 20091229 |