CN202839620U - Super junction metal oxide semiconductor field effect transistor (MOSFET) component - Google Patents
Super junction metal oxide semiconductor field effect transistor (MOSFET) component Download PDFInfo
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- CN202839620U CN202839620U CN 201220069393 CN201220069393U CN202839620U CN 202839620 U CN202839620 U CN 202839620U CN 201220069393 CN201220069393 CN 201220069393 CN 201220069393 U CN201220069393 U CN 201220069393U CN 202839620 U CN202839620 U CN 202839620U
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Abstract
The utility model provides a super junction metal oxide semiconductor field effect transistor (MOSFET) component. Grooves adjacent to adjacent quarter arcs of a terminal voltage-resistant ring are designed to be arcs of concentric circles, and the interval between an active area and the terminal voltage-resistant ring is equal everywhere. When reverse bias voltage is applied to the component, the active area and the terminal voltage-resistant ring of the super junction and a joint part between the active area and the terminal voltage-resistant ring can be depleted simultaneously through optimizing a super junction, and the distribution of an electric field is more uniform in the whole super junction, thereby acquiring larger breakdown voltage than an existing super junction MOSFET structure.
Description
Technical field
The utility model relates to a kind of super junction MOSFET components and parts.
Background technology
Power semiconductor is the inherent actuating force of the power-electronic system of development, especially at aspects such as energy savings, dynamically control, noise minimizings.Power semiconductor is mainly used in to be controlled the energy between the energy and the load, and should have precision height, speed characteristics fast and low in energy consumption.In power circuit, power semiconductor (particularly MOSFET, referred to as MOS) is mainly as switching device, because it is how sub-device, so its switch power consumption less.Its on-state power consumption is then higher, reduce on-state power consumption, just must reduce conducting resistance R
DsonTherefore, power semiconductor will further develop, and just must reduce conducting resistance R
DsonStudies show that, (be R for desirable N ditch MOS components and parts
DsonOnly consider the drift layer resistance R
D), conducting resistance R
DsonWith puncture voltage V
BBetween the pass be:
Conducting resistance is subjected to breakdown voltage limit and has a limit---and be referred to as " the silicon limit " (Silicon Limit), and can't reduce again.At beginning of the nineties late 1980s, " the silicon limit " broken in a kind of proposition of new ideas, and it can obtain low on-state power consumption and high switching speed simultaneously.This concept has obtained " super junction is theoretical " (Super Junction Theory) through after evolution and improving.
2000 and calendar year 2001, Chen Xing assist in education is awarded and is successively published thesis, and has further analyzed conducting resistance R
DsonWith puncture voltage V
BRelation, draw:
This result and experimental data are very approaching, can be used for the three dimensional analysis of super-junction structures is calculated.And proved that in theory quantitatively under same breakdown voltage, super junction MOSFET significantly reduces than the conducting resistance of conventional MOS FET, can break through the silicon limit.
Only have majority carrier in the super-junction structures turn on process---electronics, and do not have the participation of minority carrier, therefore, its switching loss is identical with traditional power MOSFET, and the impurity doping content of its voltage support layer can improve order of magnitude nearly; In addition, owing to insert p type island region on the vertical direction, can compensate excessive current lead-through electric charge.Add reverse bias voltage at drift layer, will produce a transverse electric field, the pn knot is exhausted.When voltage reached certain value, drift layer exhausted fully, will play the effect of voltage support layer.Since the significantly raising of doping content, under identical puncture voltage, conducting resistance R
DsonCan greatly reduce, descend 5 times than traditional power device.Equally, we can be at identical puncture voltage V
B, identical conducting resistance R
DsonThe less die area of lower use, thus the grid electric charge reduced, improve switching frequency.Because super-junction device is how sub-device, therefore, this device does not have the current tail phenomenon of igbt transistor, so super-junction device can obtain low on-state power consumption and high switching speed simultaneously.
Yet high voltage power device usually can be subject to tying the impact of curvature effect and cause electric field to be assembled near knot, usually utilizes pressure ring to reduce the curvature effect of pn knot.And the terminal pressure ring generally can adopt the quadrant arc to replace the right angle at four angles, this is because there is higher puncture voltage cylindrical diffusion region than rectangle, triangle and rhombus diffusion region, traditional super junction terminal pressure ring is adding in the situation of reverse biased, the depletion region of active area and potential dividing ring all can extend, when voltage is added to certain numerical value, pn knot in the active area can exhaust fully, plays the effect of a voltage support.Yet, because the list structure that super junction active area P type Si and N-type Si are special, when active area pn knot exhausted, the junction of active area and terminal potential dividing ring can't exhaust simultaneously, this can cause super junction to puncture in the junction in advance, greatly reduces the puncture voltage of device.
Summary of the invention
A purpose of the present utility model is to overcome the deficiency that the junction of the active area of super junction MOSFET components and parts and termination environment can not exhaust simultaneously, the super junction MOSFET components and parts that provide the junction of a kind of active area and termination environment to exhaust simultaneously.
A kind of super junction MOSFET components and parts, the silicon substrate that comprises the first conduction type, be arranged on the wherein epitaxial loayer of the first conduction type of one side of silicon substrate, epitaxial loayer zone line at described the first conduction type is formed with the source region, also be formed with the termination environment around active area, be provided with a plurality of parallel arranged and the equal groove of spacing at active area, in groove, be filled with the second conduction type silicon, being surrounded with the source region in the termination environment is formed with many four jiaos and has the square raceway groove that circular arc and spacing equate, fill the second conduction type silicon in the described square raceway groove, described the second conduction type silicon that is positioned at square raceway groove forms the terminal pressure ring, the spacing of the terminal pressure ring that described groove is adjacent respectively and the spacing between the adjacent trenches, spacing between the adjacent square raceway groove equates, the shape at described at least one groove two ends near the terminal pressure ring is set to circular arc, the arc of described groove and terminal pressure ring be isocentric circular arc.
Further, being surrounded with the source region in the termination environment is formed with many four jiaos and has the quadrant arc, the shape at described at least one groove two ends near the terminal pressure ring is set to the quadrant arc, and the quadrant arc of described groove and the quadrant arc of terminal pressure ring are isocentric circular arc.
Further, the groove number that the two ends shape is set to the quadrant arc is x,
Wherein, r is the radius of curvature of quadrant arc, and d is the spacing between the adjacent end pressure ring, and a is the width of terminal pressure ring, and c is the number of terminal pressure ring.
Further, the epitaxial loayer of described the first conduction type silicon and the second conduction type forms the first conductivity regions and the second conductivity regions alternately, and the spacing d between the described adjacent terminal pressure ring equates with the spacing of adjacent the first conductivity regions.
Further, described the first conduction type is the P type, and described the second conduction type is N-type.
Further, described the first conductivity regions is N-type, and described the second conductivity regions is the P type.
Further, the depth-to-width ratio of described terminal pressure ring and p type island region is 4:1.
Further, the width of the groove in the described active area is identical with the width of square raceway groove, and the degree of depth of groove is identical with square channel depth.
Further, the width of described groove is the 4-6 micron.
Further, the adjacent trenches spacing is the 6-10 micron.
Further, the range of curvature radius of the quadrant arc of described terminal pressure ring is 200 microns-300 microns.
A kind of super junction MOSFET components and parts that the utility model provides, the adjacent trench design of adjacent quadrant arc with the terminal pressure ring is become concentrically ringed circular arc, active area is equated with interval between the terminal pressure ring everywhere, by the optimization to super junction, device is when adding reverse biased, the active area of super junction and terminal pressure ring and the junction between the two can exhaust simultaneously, the distribution of electric field in whole super junction is also more even, thereby obtains the puncture voltage larger than existing super-junction structures.
Description of drawings
Fig. 1 is the vertical view of a kind of embodiment of the utility model super junction MOSFET components and parts.
Fig. 2 is prior art super junction when adding reverse biased, the vertical view that quadrant arc place depletion region distributes.
Fig. 3 is the active area of a kind of embodiment of the utility model super junction MOSFET components and parts and the vertical view at terminal pressure ring quadrant arc place.
Fig. 4 is c-c place profile among Fig. 3.
Fig. 5 is the cutaway view of a kind of embodiment of the utility model super junction MOSFET components and parts.
Wherein: 1, N-type silicon substrate; 2, N-type epitaxial loayer; 3, p type island region; 4, N-type district; 5, terminal pressure ring; 6, passivation layer; 7, electrode metal; 8, back metal; 9, groove; 10, square raceway groove; 11, field oxide; 12, gate oxide; 13, source electrode; 14, grid; 15, drain electrode.
Embodiment
Clearer for technical problem, technical scheme and beneficial effect that the utility model is solved, below in conjunction with drawings and Examples, the utility model is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the utility model, and be not used in restriction the utility model.
The invention provides the super junction MOSFET components and parts of a kind of embodiment, described MOSFET components and parts comprise the silicon substrate of the first conduction type, be arranged on the wherein epitaxial loayer of the first conduction type of one side of silicon substrate, epitaxial loayer zone line at described the first conduction type is formed with the source region, also be formed with the termination environment around active area, be provided with a plurality of parallel arranged and the equal groove 9 of spacing at active area, in groove 9, be filled with the second conduction type silicon, the epitaxial loayer of described the first conduction type silicon and the second conduction type forms the first conductivity regions and the second conductivity regions alternately, in the termination environment, be surrounded with the source region and be formed with many four jiaos square raceway grooves with circular arc, fill the first conduction type silicon in the described square raceway groove and form the terminal pressure ring 5 that has, described groove 9 equates with the spacing b of terminal pressure ring, the shape at described at least one groove, 9 two ends near terminal pressure ring 5 is set to circular arc, and the circular arc of the circular arc of groove 9 and terminal pressure ring 5 is isocentric circular arc.
In the present embodiment, described circular arc is the quadrant arc, being surrounded with the source region in the termination environment is formed with many four jiaos and has the quadrant arc, the shape at described at least one groove, 9 two ends near terminal pressure ring 5 is set to the quadrant arc, and the quadrant arc of described groove 9 and the quadrant arc of terminal pressure ring 5 are isocentric circular arc.
As shown in Figure 1 and Figure 4, the first conduction type can be N-type or P type, and the second conduction type and the first conductivity type opposite can be N-type or P type, and namely described the first conduction type is the P type, and described the second conduction type is N-type; Perhaps described the first conductivity regions is N-type, described the second conductivity regions is the P type, in the present embodiment, described the first conduction type is N-type, described the second conduction type is the P type, be provided with N-type epitaxial loayer 2 at N-type silicon substrate 1, central area at N-type epitaxial loayer 2 is formed with the source region, be provided with the groove 9 of a plurality of parallel arranged at active area, in groove 9, be filled with P type silicon, also be formed with the termination environment around described active area, described P type silicon and N-type epitaxial loayer 2 form p type island region 3 and N-type district 4 alternately, being formed with many four jiaos around active area is the square raceway groove of quadrant arc, fill P type silicon in the described square raceway groove and form the terminal pressure ring 5 with quadrant arc, be coated with for the passivation layer 6 that insulate at active area and terminal pressure ring 5, also be provided with the with it electrode metal 7 of ohmic contact on the described passivation layer 6, electrode metal 7 is electrically connected with source electrode 13 and grid 14 respectively, be provided with drain electrode 15 at N-type silicon substrate 1 back metal, the width of the groove 9 in the described active area is identical with the width of square raceway groove, the degree of depth of described groove is identical with the degree of depth of square raceway groove, described groove 9 equates with the spacing b of terminal pressure ring 5 everywhere, the groove 9 adjacent with terminal pressure ring 5 quadrant arcs is shaped as the quadrant arc, and the quadrant arc of groove 9 and the quadrant arc of terminal pressure ring 5 are isocentric circular arc.
In conjunction with Fig. 2 and shown in Figure 5, the intersection of the active area of super junction and terminal pressure ring 5 in the prior art, because the groove 9 of active area is strip structure, and terminal pressure ring 5 is four rectangular configuration that the angle is the quadrant arc, not equidistant between the loop configuration of the strip structure of active area and terminal pressure ring 5 can be caused in the junction of the two, when between source electrode and drain electrode, adding reverse biased, when the depletion region of the active area of super junction and terminal pressure ring 5 has exhausted, intersection of the two at it, namely the shadow region among the figure does not also exhaust fully, if continue to add reverse biased, the zone of shaded side is very possible just not to have been punctured when also exhausting fully, so the existence in shadow region can reduce the withstand voltage of super junction greatly.
In order to address this is that, the shape that the utility model proposes described at least one groove, 9 two ends near terminal pressure ring 5 is set to the quadrant arc, the quadrant arc of described groove 9 and the quadrant arc of terminal pressure ring 5 are isocentric circular arc, be provided with equally the quadrant arc at active area and terminal pressure ring 5 adjacent grooves 9, with the quadrant arc of terminal pressure ring 5 be concentric circles, groove 9 equates with spacing between the terminal pressure ring 5 everywhere, and the spacing of the terminal pressure ring 5 that described groove 9 is adjacent respectively and the spacing between the adjacent trenches 9, spacing between the adjacent square raceway groove 10 equates.
For so that active area and termination environment can exhaust fully, the hole sum that is positioned at p type island region 3 equals the electronics sum in N-type district 3, and the computing formula that the hole sum equals the electronics sum is N
AV
n=N
DV
p, wherein, N
ABe acceptor concentration, N
DBe donor concentration, V
nBe the volume in all N-type districts 4, V
pVolume for all p type island regions 3.
In conjunction with shown in Figure 5, on the termination environment, also be provided with field oxide 11, be provided with gate oxide 12 at p type island region, passivation layer 6 is used for insulation, can adopt boron phosphorus silicate glass of the prior art (BPSG), SiO
2, the known passivation layer 6 such as SiN, in the present embodiment, described passivation layer 6 is preferably the boron phosphorus silicate glass layer, electrode metal 7 comprise known all can form the electrode metal 7 of ohmic contact, electrode metal connects respectively source electrode 13 and grid 14, the preferred Al of the utility model front metal, be provided with drain electrode 15 at N-type silicon substrate 1 back metal, back metal 8 preferred nickel or silver, at source electrode 13 with drain when adding reverse biased between 15, the depletion region of active area and terminal pressure ring 5 can exhaust fully, does not have unspent zone.。
The described groove 9 required number computing formula that change over the quadrant arc,
Wherein, r is the radius of curvature of quadrant arc, and d is the spacing between the adjacent end pressure ring 5, and a is the width of terminal pressure ring 5, and c is the number of terminal pressure ring 5.
Groove depth is according to the concrete technology level and to the specific requirement of device, Ron is less for larger then its conducting resistance of depth-to-width ratio, but its cost is higher, in the present embodiment, the width of the groove 9 in the described active area is identical with the width of square raceway groove 10, and the degree of depth of groove 9 is identical with square raceway groove 10 degree of depth, groove 9 interior filling P type silicon form p type island region 3, described terminal pressure ring 5 is 4:1 with the depth-to-width ratio of p type island region 3, and technique realizes that easily cost is also relatively moderate.
Spacing d between the described adjacent terminal pressure ring 5 equates with the spacing e of adjacent p type island region 3, the width of described groove 9 is the 4-6 micron, groove 9 width are less than 4 microns, consider to increase on the one hand the difficulty of etching groove from the angle of technique, on the other hand in the situation of same trench 9 degree of depth and same groove spacing, P type (or N-type) well width is less, and then to want to exhaust required P type (or N-type) the groove concentration of N-type (or the P type) extension of same concentrations just larger, and carrier concentration is larger in the groove, and its withstand voltage will be lower; If groove width, then can increase the difficulty that groove is filled greater than 6 microns, in the present embodiment, preferred 4 microns.
The radius of curvature of annulus is too small, then increase the DeGrain of puncture voltage, can occupy the too much area in source region if its radius of curvature is excessive, cause conducting resistance Rdson to increase, the range of curvature radius of the quadrant arc of described terminal pressure ring 5 is 200 microns-300 microns, in the present embodiment, the scope of the radius of curvature of the quadrant arc of described terminal pressure ring 5 is 200 microns.
In the first embodiment, the number of described terminal pressure ring 5 is 9, and the groove width preferred value is 4 microns, and the separation preferred value is 8 microns, and the preferred value of the concentrically ringed radius of curvature of corner is 200 microns, then 1/4th of required change concentrically ringed numbers
Then get its integer, 1/4th concentrically ringed numbers of required change are 7, and the described groove 9 required numbers that change over the quadrant arc are 7.
The second embodiment, the number of described terminal pressure ring 5 is 9, and the groove width preferred value is 6 microns, and the separation preferred value is 6 microns, and the preferred value of the concentrically ringed radius of curvature of corner is 300 microns, then 1/4th of required change concentrically ringed numbers
/ 4th concentrically ringed numbers of required change are 7, and the described groove 9 required numbers that change over the quadrant arc are 16.
The third embodiment, the number of described terminal pressure ring 5 is 9, and the groove width preferred value is 4 microns, and the separation preferred value is 10 microns, and the preferred value of the concentrically ringed radius of curvature of corner is 300 microns, then 1/4th of required change concentrically ringed numbers
Then get its integer, 1/4th concentrically ringed numbers of required change are 7, and the described groove 9 required numbers that change over the quadrant arc are 17.
A kind of super junction MOSFET components and parts that the utility model provides, the silicon substrate that comprises the first conduction type, be arranged on the wherein epitaxial loayer of the first conduction type of one side of silicon substrate, epitaxial loayer zone line at described the first conduction type is formed with the source region, also be formed with the termination environment around active area, be provided with a plurality of parallel arranged and the equal groove of spacing at active area, in groove, be filled with the second conduction type silicon, being surrounded with the source region in the termination environment is formed with many four jiaos and has the square raceway groove that quadrant arc and spacing equate, fill the second conduction type silicon in the described square raceway groove, described the second conduction type silicon that is positioned at square raceway groove forms the terminal pressure ring, the spacing of the terminal pressure ring that described groove is adjacent respectively and the spacing between the adjacent trenches, spacing between the adjacent channel equates, the shape at described at least one groove two ends near the terminal pressure ring is set to the quadrant arc, the quadrant arc of described groove and the quadrant arc of terminal pressure ring are isocentric circular arc, by the adjacent trench design of adjacent quadrant arc with the terminal pressure ring is become concentrically ringed quadrant arc, active area is equated with interval between the terminal pressure ring everywhere, be optimized by the structure to super junction, device is when adding reverse biased, the active area of super junction and terminal pressure ring and the junction between the two can exhaust simultaneously, the distribution of electric field in whole super junction also more even, thus the puncture voltage larger than existing super-junction structures obtained.
The above only is preferred embodiment of the present utility model; not in order to limit the utility model; all any modifications of within spirit of the present utility model and principle, doing, be equal to and replace and improvement etc., all should be included within the protection range of the present utility model.
Claims (11)
1. super junction MOSFET components and parts, it is characterized in that, the silicon substrate that comprises the first conduction type, be arranged on the wherein epitaxial loayer of the first conduction type of one side of silicon substrate, epitaxial loayer zone line at described the first conduction type is formed with the source region, also be formed with the termination environment around active area, be provided with a plurality of parallel arranged and the equal groove of spacing at active area, in groove, be filled with the second conduction type silicon, being surrounded with the source region in the termination environment is formed with many four jiaos and has the square raceway groove that circular arc and spacing equate, fill the second conduction type silicon in the described square raceway groove, described the second conduction type silicon that is positioned at square raceway groove forms the terminal pressure ring, the spacing of the terminal pressure ring that described groove is adjacent respectively and the spacing between the adjacent trenches, spacing between the adjacent square raceway groove equates, the shape at described at least one groove two ends near the terminal pressure ring is set to circular arc, the arc of described groove and terminal pressure ring be isocentric circular arc.
2. super junction MOSFET components and parts as claimed in claim 1, it is characterized in that, being surrounded with the source region in the termination environment is formed with many four jiaos and has the quadrant arc, the shape at described at least one groove two ends near the terminal pressure ring is set to the quadrant arc, and the quadrant arc of described groove and the quadrant arc of terminal pressure ring are isocentric circular arc.
3. super junction MOSFET components and parts as claimed in claim 1 is characterized in that, the groove number that the two ends shape is set to the quadrant arc is x,
Wherein, r is the radius of curvature of quadrant arc, and d is the spacing between the adjacent end pressure ring, and a is the width of terminal pressure ring, and c is the number of terminal pressure ring 5.
4. super junction MOSFET components and parts according to claim 2, it is characterized in that, the epitaxial loayer of described the first conduction type silicon and the second conduction type forms the first conductivity regions and the second conductivity regions alternately, and the spacing between the described adjacent terminal pressure ring equates with the spacing of adjacent the first conductivity regions.
5. super junction MOSFET components and parts according to claim 4 is characterized in that, described the first conduction type is the P type, and described the second conduction type is N-type.
6. super junction MOSFET components and parts according to claim 4 is characterized in that, described the first conductivity regions is N-type, and described the second conductivity regions is the P type.
7. super junction MOSFET components and parts according to claim 6 is characterized in that, the depth-to-width ratio of described terminal pressure ring and p type island region is 4:1.
8. super junction MOSFET components and parts according to claim 1 is characterized in that, the width of the groove in the described active area is identical with the width of square raceway groove, and the degree of depth of groove is identical with square channel depth.
9. the described super junction MOSFET components and parts of any one is characterized in that according to claim 1-8, and the width of described groove is the 4-6 micron.
10. the described super junction MOSFET components and parts of any one is characterized in that according to claim 1-8, and the adjacent trenches spacing is the 6-10 micron.
11. super junction MOSFET components and parts according to claim 2 is characterized in that, the range of curvature radius of the quadrant arc of described terminal pressure ring is 200 microns-300 microns.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 201220069393 CN202839620U (en) | 2012-02-29 | 2012-02-29 | Super junction metal oxide semiconductor field effect transistor (MOSFET) component |
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| CN 201220069393 CN202839620U (en) | 2012-02-29 | 2012-02-29 | Super junction metal oxide semiconductor field effect transistor (MOSFET) component |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103579301A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | Corner layout for high voltage semiconductor devices |
| US9450083B2 (en) | 2011-08-25 | 2016-09-20 | Alpha And Omega Semiconductor Incorporated | High voltage field balance metal oxide field effect transistor (FBM) |
| US9577072B2 (en) | 2011-08-25 | 2017-02-21 | Alpha And Omega Semiconductor Incorporated | Termination design for high voltage device |
| CN108987459A (en) * | 2018-07-25 | 2018-12-11 | 王永贵 | A kind of power device |
| CN109273519A (en) * | 2017-07-18 | 2019-01-25 | 富士电机株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN111987147A (en) * | 2020-10-26 | 2020-11-24 | 江苏应能微电子有限公司 | Power semiconductor device |
| CN114072927A (en) * | 2019-07-16 | 2022-02-18 | 三菱电机株式会社 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
| CN117096178A (en) * | 2023-10-17 | 2023-11-21 | 富芯微电子有限公司 | High-voltage-resistant planar semiconductor device |
| WO2024001779A1 (en) * | 2022-06-30 | 2024-01-04 | 苏州华太电子技术股份有限公司 | Super junction power device |
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2012
- 2012-02-29 CN CN 201220069393 patent/CN202839620U/en not_active Expired - Lifetime
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US9224852B2 (en) | 2011-08-25 | 2015-12-29 | Alpha And Omega Semiconductor Incorporated | Corner layout for high voltage semiconductor devices |
| US9450083B2 (en) | 2011-08-25 | 2016-09-20 | Alpha And Omega Semiconductor Incorporated | High voltage field balance metal oxide field effect transistor (FBM) |
| US9543413B2 (en) | 2011-08-25 | 2017-01-10 | Alpha And Omega Semiconductor Incorporated | Corner layout for high voltage semiconductor devices |
| US9577072B2 (en) | 2011-08-25 | 2017-02-21 | Alpha And Omega Semiconductor Incorporated | Termination design for high voltage device |
| US9865678B2 (en) | 2011-08-25 | 2018-01-09 | Alpha And Omega Semiconductor Incorporated | High voltage field balance metal oxide field effect transistor (FBM) |
| US10069005B2 (en) | 2011-08-25 | 2018-09-04 | Alpha And Omega Semiconductor Incorporated | Termination design for high voltage device |
| CN103579301A (en) * | 2012-07-30 | 2014-02-12 | 万国半导体股份有限公司 | Corner layout for high voltage semiconductor devices |
| CN103579301B (en) * | 2012-07-30 | 2016-12-07 | 万国半导体股份有限公司 | Turning layout for high-voltage semi-conductor device and preparation method thereof |
| CN109273519B (en) * | 2017-07-18 | 2023-05-23 | 富士电机株式会社 | Semiconductor device and method for manufacturing semiconductor device |
| CN109273519A (en) * | 2017-07-18 | 2019-01-25 | 富士电机株式会社 | The manufacturing method of semiconductor device and semiconductor device |
| CN108987459A (en) * | 2018-07-25 | 2018-12-11 | 王永贵 | A kind of power device |
| CN114072927A (en) * | 2019-07-16 | 2022-02-18 | 三菱电机株式会社 | Semiconductor device, power conversion device, and method for manufacturing semiconductor device |
| CN111987147A (en) * | 2020-10-26 | 2020-11-24 | 江苏应能微电子有限公司 | Power semiconductor device |
| WO2024001779A1 (en) * | 2022-06-30 | 2024-01-04 | 苏州华太电子技术股份有限公司 | Super junction power device |
| CN117096178A (en) * | 2023-10-17 | 2023-11-21 | 富芯微电子有限公司 | High-voltage-resistant planar semiconductor device |
| CN117096178B (en) * | 2023-10-17 | 2024-01-16 | 富芯微电子有限公司 | High-voltage-resistant planar semiconductor device |
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