CN102969358B - A widthwise high voltage power semiconductor devices - Google Patents

A widthwise high voltage power semiconductor devices Download PDF

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CN102969358B
CN102969358B CN 201210516539 CN201210516539A CN102969358B CN 102969358 B CN102969358 B CN 102969358B CN 201210516539 CN201210516539 CN 201210516539 CN 201210516539 A CN201210516539 A CN 201210516539A CN 102969358 B CN102969358 B CN 102969358B
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CN 201210516539
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CN102969358A (en )
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乔明
章文通
李燕妃
许琬
蔡林希
吴文杰
陈涛
胡利志
黄健文
张波
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电子科技大学
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Abstract

一种横向高压功率半导体器件,属于功率半导体器件技术领域。 A widthwise high voltage power semiconductor devices, belonging to the technical field of power semiconductor devices. 包括纵向超结元胞结构和终端结构;终端结构位于整体元胞结构的外侧或外围。 Comprising longitudinal superjunction structure and cellular structure of the terminal; a terminal or peripheral structures are located outside the overall cellular structure. 纵向超结元胞结构在提高击穿电压的同时降低导通电阻,相比传统横向超结器件,纵向超结元胞结构减小了版图面积,进一步降低了导通电阻;单个或多个元胞集成,多个并联元胞可共用同一个终端,并通过终端结构将漏电极横向引出,不仅易于和常规电路集成,而且大大减小版图面积,进一步降低工艺成本。 Cellular longitudinal super junction structure to reduce on-resistance while improving the breakdown voltage, compared to conventional super-junction device laterally, longitudinally super junction structure cellular layout area is reduced, further reducing the on-resistance; membered single or multiple cell integration, a plurality of parallel cellular shared with a terminal, and the terminal structure by a lateral drain electrode lead, and a conventional integrated circuit is not only easy but also greatly reduce the layout area, further reducing the cost of the process. 本发明具有导通电阻低、耐压高、版图面积小等诸多优点,采用本发明可获得各种性能优良的横向半导体功率器件,具有高速、高集成度、低导通损耗的特点。 The present invention has a low on-resistance, high breakdown voltage, and small layout area and many other advantages, the present invention can be obtained using the excellent performance of the lateral semiconductor power devices, high-speed, high integration, low conduction loss characteristics.

Description

一种横向高压功率半导体器件 A widthwise high voltage power semiconductor devices

技术领域 FIELD

[0001] 本发明属于功率半导体器件技术领域,涉及一种横向高压功率半导体器件。 [0001] The present invention belongs to the technical field of power semiconductor devices, relates to a lateral high voltage power semiconductor device.

背景技术 Background technique

[0002] 横向高压功率半导体器件是高压功率集成电路发展必不可少的部分,高压功率器件要求具有高的击穿电压,低的导通电阻和低的开关损耗。 [0002] The lateral high voltage power semiconductor device is a high voltage power development an essential part of an integrated circuit, high voltage power device required to have a high breakdown voltage, low on-resistance and low switching losses. 横向高压功率器件实现高的击穿电压,要求其用于承担耐压的漂移区具有长的尺寸和低的掺杂浓度,但为了满足器件低导通电阻,又要求作为电流通道的漂移区具有高的掺杂浓度。 A lateral high voltage power device to achieve a high breakdown voltage required for the pressure to assume the drift region having a long dimension and a low doping concentration, but in order to meet the low on-resistance device, and 1 as the drift region current path having high doping concentration. 在功率MOS器件设计中,击穿电压BV(Breakdown Voltage)与比导通电阻Rm,sp的关系很严峻:Rm,sp 00 BV2_5,这一矛盾关系限制了该类器件在高压大电流领域的应用。 In the power MOS device design, the breakdown voltage BV (Breakdown Voltage) and the specific on-resistance Rm, sp very serious relationship: Rm, sp 00 BV2_5, the contradiction between limited the application of such devices is in the field of high voltage large current . 为了解决这对矛盾,陈星弼院士在其1998年的美国专利中提出了一种新型功率MOS器件——CooIMOS,并很快走向市场。 To resolve this contradiction, Academician Chen Xingbi in its US patent in 1998, a new power MOS device --CooIMOS, and soon to the market. CooIMOS器件采用交替的P、N条结构代替传统功率MOS器件中低掺杂漂移区层作电压支持层(耐压层)。 CooIMOS device using alternating P, N number of power MOS transistor structure instead of the conventional low-doped drift region layer for voltage support layer (withstand voltage layer). 当器件加反向偏置电压时,P、N条相互耗尽,承受器件耐压。 When the reverse bias voltage applied to the device, P, N each depleted strip, bear the breakdown voltage. 由于P条和N条的掺杂浓度高于传统结构的漂移区浓度,使得其正向导通电阻大大降低,从而改善导通电阻与器件耐压之间的矛盾。 Since P slices and dopant concentration of the N drift region is higher than the concentration of conventional structure, so that its positive conduction resistance is greatly reduced, thereby improving the contradiction between the on-resistance and breakdown voltage. 然而,传统的横向超结结构的P条和N条是沿器件横向方向放置,与纵向超结结构相比,器件版图面积较大,进而增加了制造成本。 However, conventional P and N of transverse strips super junction structure is placed in the device the transverse direction, as compared with the longitudinal super junction structure, device layout area is large, thereby increasing manufacturing costs.

发明内容 SUMMARY

[0003] 为解决上述现有技术中所存在的问题,本发明提出了一种新型的横向高压功率半导体器件,该器件包括元胞结构和终端结构。 [0003] In order to solve the above-described prior art problems, the present invention provides a new type of high-voltage lateral power semiconductor device, the device comprises a cellular structure and termination structure. 一方面,N型漂移区中引入P型掺杂条构成纵向超结漂移区结构,打破传统硅极限,缓解器件耐压和导通电阻之间的矛盾关系,并减小器件版图面积;另一方面,超结漂移区结构掺杂浓度较高,为开路电流提供低阻通路,从而降低导通电阻;再一方面,关态时,高浓度的P型掺杂条和N型掺杂条在漂移区引入两个新的电场尖峰,使漂移区电势在源端和漏端的分布类似纵向超结结构的电势分布,同时,N型掺杂条和P型掺杂条产生的额外电场,增强了介质槽电场,从而提高器件耐压;最后,该器件可集成单个或多个元胞,多个元胞共用同一个终端结构,大大减小版图面积,降低工艺成本。 In one aspect, N-type drift region doping strips introducing P-type region constituting the super junction structure longitudinal drift, conventional silicon breaking limit, to ease the contradictory relationship between breakdown voltage and on-resistance, and to reduce the layout area of ​​the device; another aspect, the drift region of the super junction structure of a high doping concentration to provide a low resistance current path is open, thereby reducing the on-resistance; another aspect, when the off state, a high concentration P-type dopant and the N-type dopant bar strip drift region introduced two new field peaks, so that the drift region potential of the source terminal and the drain terminal of the distribution is similar to the longitudinal potential distribution of the super junction structure, at the same time, N type dopant strip and P-type dopant additional field strip produced enhanced medium tank farm, thereby improving the device breakdown voltage; Finally, the device may be integrated single or plurality of cells, a plurality of cells share the same terminal structure, layout area is greatly reduced, reducing the process cost.

[0004] 本发明技术方案为: [0004] The technical solution of the present invention are:

[0005] 一种横向高压功率半导体器件,如图2所示,包括至少一个或一个以上的纵向超结元胞结构61和终端结构62 ;多个纵向超结元胞结构61沿器件横向或宽度方向紧密堆积在一起,形成整体纵向超结元胞结构;所述终端结构62位于整体元胞结构的外侧或外围。 [0005] A lateral high voltage power semiconductor device 2, comprising at least one or more longitudinal superjunction structure cellular structure 62 and a terminal 61; a plurality of longitudinal cellular super junction structure 61 in the lateral width of the device or direction close packing together to form a unitary cellular longitudinal superjunction structure; the terminal structure 62 or positioned outside the periphery of the overall cellular structure.

[0006] 所述纵向超结元胞结构61包括位于P型衬底I表面的N型漂移区31,位于N型漂移区31顶部一侧的P型体区41,P型体区41中具有分别与位于器件表面源极金属52相连的P+源极接触区42和N+源极接触区32 ;P型体区41下方的N型漂移区31中具有P型掺杂条43,P型掺杂条43与旁边的N型漂移区31形成超结结构,超结结构与超结结构下方的N型漂移区31构成具有部分超结结构的漂移区;栅极结构由栅氧化层23和多晶硅栅电极51构成,其中栅氧化层23与N型漂移区31和P型体区41相接触,多晶硅栅电极51与源极金属52之间通过介质层22相互隔离。 [0006] The cellular longitudinal superjunction structure 61 includes an N-type drift region surface of the P-type substrate I 31, P-type body region 41 is located in the top side 31 of the N-type drift region, P-type body region 41 having respectively, at the surface of the source device electrode metal 52 is connected to a P + source contact region 42 and the N + source contact region 32; P-type body region 41 N-type drift region below 31 having a P-type doped strips 43, P-type doping Article 43 adjoining the N-type drift region 31 form a super junction structure, N-type drift region of the super junction structure below the superjunction structure portion 31 constitutes the drift region having a super-junction structure; gate structure by a gate oxide layer 23 and polysilicon gate constituting the electrode 51, wherein the gate oxide layer 23 in contact with the N-type drift region 31 and P-type body region 41, isolation between the polysilicon gate electrode 51 and source metal layer 52 through the dielectric 22.

[0007] 所述终端结构62,包括N型漂移区31、N型掺杂条34、N型重掺杂漏极接触区33和介质槽2 ;终端结构62中N型漂移区31的顶部一侧是与漏极金属53相连的N型重掺杂漏极接触区33,N型掺杂条34位于N型重掺杂漏极接触区33下方的N型漂移区31中,且与N型重掺杂漏极接触区33相接触;介质槽2位于N型掺杂条34和所述纵向超结元胞结构61的P型掺杂条43之间,介质槽2和N型掺杂条34下方保留部分N型漂移区31作为电流通道,漏极金属53和源极金属52之间通过介质层22相互隔离。 The [0007] termination structure 62, including an N-type drift region 31 is, article 34 is doped N-type, heavily doped N-type drain contact region 33 and a medium tank 2; the top of a termination structure of N-type drift region 62 31 the drain side is connected to the metal 53 N-type drain contact region 33 is heavily doped, N-type dopant article 34 in the N-type heavily doped region 33 N-type drift region beneath the drain contact 31, and the N-type the heavily doped drain contact region 33 is in contact; 43, medium tank 2 and N-type doped P-type dopant strip and the longitudinal strip 234 superjunction cellular structure 61 of the N-type doped dielectric strips positioned grooves the lower portion 34 to retain the N-type drift region 31 as a current path between the drain 53 and source metal 52 are isolated from the metal layer 22 through the dielectric.

[0008] 本发明提供的横向高压功率半导体器件包括纵向超结元胞结构61和终端结构62。 [0008] The lateral high voltage power semiconductor device according to the present invention comprises longitudinal superjunction cellular structure 61 and the termination structure 62. 在纵向元胞结构61的N型漂移区31中引入P型掺杂条43,与N型漂移区31形成纵向超结结构。 Introducing P-type dopant 31 in strip 43 in the longitudinal direction of the N-type drift region of the cellular structure 61, and the N-type drift region 31 is formed longitudinally super junction structure. 终端结构62中引入的N型掺杂条34与N型漂移区31形成N+N结,N型掺杂条34的浓度较高,为开态电流提供低阻通道,从而降低导通电阻。 Termination structure 62 introduced in article 34 and N-type doped N-type drift region 31 is formed N + N junction, an N-type dopant concentration higher strip 34 provides a low resistance path for the current on-state, thereby reducing the on-resistance. 器件的横向耐压主要由终端结构62中的介质槽2承受,采用介质槽2耐压可以减小版图面积,降低工艺成本。 Mainly by the lateral pressure device 62 in the terminal structure receiving medium tank 2, tank 2 using dielectric breakdown voltage can be reduced layout area, reducing the process cost. 本发明提供的横向高压功率半导体器件可以采用平面栅、槽栅或V型栅等结构,应用灵活。 Lateral high voltage power semiconductor device according to the present invention may be employed to provide the gate plane, or V-shaped gate trench gate structure such as flexible in application. 器件可集成单个或多个纵向超结元胞结构61,多个元胞可以共用同一个终端结构62,大大减小版图面积,进一步降低工艺成本。 Single or multiple devices may be integrated cellular longitudinal super-junction structure 61, a plurality of cellular terminals can share the same structure 62, greatly reduce the layout area, further reducing the cost of the process.

[0009] 本发明的工作原理可以描述如下: [0009] The working principle of the present invention may be described as follows:

[0010] 本发明提供的横向高压功率半导体器件可采用平面栅、槽栅或V型栅等结构,这些结构的工作原理相似,关态时,横向高压功率半导体器件工作原理如图3所示。 [0010] The lateral high voltage power semiconductor device according to the present invention can be provided in the gate plane, or V-shaped gate trench gate structure, etc., similar to the working principle of these structures, when the off-state, high-voltage lateral power semiconductor device shown in Figure 3 works.

[0011] 本发明提供的横向高压功率半导体器件可集成单个或多个纵向超结元胞结构61,多个纵向超结元胞结构61可共用同一个终端结构62,从而大大减小版图面积。 [0011] The lateral high voltage power semiconductor device according to the present invention may be integrated to provide a single or a plurality of longitudinal cellular super-junction structure 61, a plurality of longitudinal super junction structure cellular terminal 61 can share a same structure 62, thereby greatly reducing the area of ​​layout. 器件的横向耐压主要由终端结构62的介质槽2决定。 Lateral pressure device 2 is mainly determined by the dielectric trench termination structure 62. 如图3 (b)所示,当器件耐压时,N型漂移区31和P型体区41构成的PN结冶金结面开始耗尽,随着漏电压增加,耗尽区向N型漂移区31扩展,使得N型漂移区31与P型体区41所构成的PN结冶金结面出现电场峰值。 As shown in FIG 3 (b), when the breakdown voltage, the PN junction metallurgical junction N-type drift region 31 and P-type body region 41 formed of a depletion started, as the drain voltage increases, the depletion region into the N-type drift extension region 31, N-type drift region 31 such that the peak electric field and the PN junction surface of the metallurgical junction P-type body region 41 thereof. N型漂移区31中引入的P型掺杂条43辅助耗尽N型漂移区31,优化器件纵向电场,提高器件纵向耐压。 N-type drift region 31 of P-type dopant introduced in the auxiliary strip 43 a depletion N-type drift region 31, the longitudinal electric field optimization device to improve device breakdown voltage vertical. 同时,耗尽的P型掺杂条43中剩下负的电离受主电荷,调制器件体内的电场分布,避免电场线在源端过度集中,并在P型掺杂条43和介质槽2的界面处引入新的电场峰值,增强介质槽电场,进一步提高器件横向耐压。 Meanwhile, the remaining 43 negative strip depleted P-type dopant ionized acceptor charge, the electric field distribution in vivo modulation device, to avoid excessive concentration of electric field lines at the source, and the doped dielectric strip 43 and the P-type tank 2 introducing new interface peak electric field, the electric field enhancing medium tank, to further improve the breakdown voltage lateral devices. 终端结构中还包括N型掺杂条34,N型掺杂条34浓度较高,器件耐压时,耗尽的N型掺杂条剩下大量正的电离施主电荷,调制器件体内的电场分布,避免漏端电场线过度集中,并在N型掺杂条43和介质槽界面处引入新的电场尖峰,增强介质槽电场,从而提高器件击穿电压。 Terminal structure further comprises a strip 34 doped N-type high concentration N-type doping strips 34, when the breakdown voltage, a depletion N-type dopant remaining large pieces of positive charge ionized donor, the electric field distribution in vivo modulation device , to avoid excessive concentration of electric field lines at the drain terminal, and introducing new peak electric field in the N-type doped dielectric strip and the groove 43 at the interface, the electric field enhancing medium tank, thereby improving the device breakdown voltage. P型掺杂条43的引入,增加了N型漂移区31的浓度,因此在提高击穿电压的同时降低了导通电阻。 P-type dopant is introduced into the strip 43, increasing the concentration of N-type drift region 31, thus improving the breakdown voltage at the same time reduces the on-resistance. 同时,高浓度掺杂的N型掺杂条34为开态电流提供低阻通道,进一步降低器件导通电阻。 Meanwhile, heavily doped N-type dopant to provide a low resistance path for the strip 34 on-state current, to further reduce device on-resistance. P型掺杂条43和N型掺杂条34在N漂移区31体内引入两个新的电场尖峰,优化漂移区的电势分布,使漂移区电势在源端和漏端的分布类似纵向超结结构的电势分布。 P-type doped strip 43 and N-type doped strip 34 in 31 in vivo N-drift regions to introduce two new field spikes, optimizing the potential distribution of the drift region of the drift region potential of the source terminal and the drain terminal profile similar longitudinal super junction structure potential distribution. 采用介质槽耐压可以进一步减小器件版图面积,降低工艺成本。 Pressure medium tank using the device can be further reduced layout area, reducing the process cost. 器件集成在P型衬底材料I上,由于器件源端耐压,与传统介质槽结构相比,N型漂移区31对P型衬底I的辅助耗尽作用更加明显,使得器件的纵向耐压大大增加。 Devices integrated on a P-type substrate material I, since the source device breakdown voltage, compared with conventional media slot structure, the auxiliary I P-type substrate 31 pairs of N-type drift region is depleted more obvious, the longitudinal direction such that resistance of the device pressure greatly increased.

[0012] 需要说明的是: [0012] It should be noted that:

[0013] (I)纵向超结元胞结构61中引入P型掺杂条43,与N型漂移区31构成纵向超结结构,缓解击穿电压和导通电阻之间的矛盾关系。 [0013] (I) cellular longitudinal super junction structure 61 in the P-type dopant introduced into the strip 43, constituting the super junction structure and vertical N-type drift region 31, to ease the contradictory relationship between breakdown voltage and on-resistance.

[0014] (2)终端结构62包括N型漂移区31、N型掺杂条34、介质槽2和第二N型重掺杂区33。 [0014] (2) the terminal structure 62 comprises a drift region 31 is N-type, N-type doping article 34, the medium tank 2 and the second heavily doped N-type region 33.

[0015] (3)N型重掺杂漏极接触区33若采用P型重掺杂漏极接触区44代替,可以实现性能良好的横向IGBT (Insulated Gate Bipolar Transistor)器件。 [0015] (3) N-type heavily doped drain contact region 33 when the P-type heavily doped drain contact region 44 in place, good performance can be achieved lateral IGBT (Insulated Gate Bipolar Transistor) device.

[0016] (4)器件可集成单个或多个纵向超结元胞结构,多个并联的元胞可共用同一个终端结构62,从而大大减小器件版图面积。 [0016] (4) a single or multiple devices may be integrated cellular longitudinal super-junction structure, a plurality of parallel cellular terminal can share the same structure 62, thereby greatly reducing the layout area of ​​the device.

[0017] (5)横向高压功率半导体器件中的N型掺杂条34可以有也可以没有。 [0017] (5) lateral high voltage power semiconductor devices doped N-type strip 34 may or may not.

[0018] (6)横向高压器件可以是平面栅、槽栅或V型栅等结构。 [0018] (6) lateral high voltage devices may be planar gate, or V-shaped gate trench gate structure and the like.

[0019] 本发明具有以下有益效果: [0019] The present invention has the following advantages:

[0020] 本发明提供的横向高压功率半导体器件包括纵向超结元胞结构61和终端结构62,其中,纵向超结元胞结构61的N型漂移区31引入P型掺杂条43,构成纵向超结结构,打破传统功率MOS器件理论极限,在保持功率MOS所有优点的同时,又有着极低的比导通电阻和高的耐压。 [0020] The lateral high voltage power semiconductor device according to the present invention comprises longitudinal superjunction structure cellular structure 61 and a terminal 62, wherein the longitudinal superjunction cellular structure 61 of the N-type drift region 31 doped P-type strip 43 is introduced, constituted longitudinal super junction structure, a theoretical limit to break conventional power MOS device, while maintaining all the advantages of the power MOS, but also has a very low specific on-resistance and high breakdown voltage. 传统横向功率MOS器件实现高的击穿电压时,要求其用于承受耐压的N型漂移区具有长的尺寸和低的掺杂浓度,这使得器件的面积和导通电阻大大增加,增加了工艺成本,从而限制横向高压功率器件的应用。 When a conventional lateral power MOS device realized a high breakdown voltage, which is required for the N-type withstand voltage drift region having a long dimension and a low doping concentration, which makes the area of ​​the device on-resistance and greatly increased, increasing the process costs, thereby limiting the application of a lateral high voltage power device. 本发明提供的横向高压功率半导体器件中终端结构主要包括N型漂移区31、介质槽2、N型重掺杂漏极接触区33和N型掺杂条34,介质槽承受耐压,需要的面积较小,从而减小器件的版图面积。 Lateral high voltage power semiconductor devices of the present invention provides a terminal structure includes an N-type drift region 31, the medium tank 2, N-type heavily doped drain contact region 33 and N-type doped strip 34, subjected to pressure medium tank, need small in size, thereby reducing the layout area of ​​the device. 介质槽2 —侧的P型掺杂条43辅助耗尽N型漂移区31,优化器件纵向电场。 Medium tank 2 - P-type doped side bar 43 assisted depletion N-type drift region 31, the longitudinal electric field optimization device. P型掺杂条耗尽时,为漂移区提供大量负的电离受主电荷,调制漂移区电场在源端的分布,避免源端电场线过度集中,导致器件提前击穿。 Doped P-type strips is depleted, to provide a large negative charge acceptor ionization drift region, the drift region electric field modulation profile of the source, the source to avoid excessive concentration of electric field lines, resulting in breakdown of the device in advance. 开态时,高浓度的N型掺杂条34为开态电流提供低阻通道,可以降低导通电阻,关态时,耗尽的N型掺杂条34在介质槽2另一侧引入大量正的电离施主电荷,调制漂移区电场在源端的分布,避免漏端电场线过度集中在漏电极与介质槽2的接触界面,防止器件提前发生击穿。 In the on state, a high concentration N-type dopant to provide a low resistance path for the strip 34 on-state current can be reduced on-resistance, when the OFF state, N-type dopant depleted strip 34 is introduced in a large number of groove 2 the other side of the medium positive ionization donor charge, the electric field distribution in the drift region modulation source terminal, a drain terminal to avoid excessive concentration of electric field lines at the contact interface with the drain electrode of the dielectric trench 2, preventing the device breakdown occurs earlier. N型掺杂条34和P型掺杂条43引入了两个新的电场尖峰,优化器件体内电场,增强介质槽电场,从而提高器件耐压。 Article 34 and N-type doped P-type dopant Article 43 introduces two new peak electric field, the electric field within the device to optimize, enhance medium tank farm, thereby improving the breakdown voltage. 所述横向高压器件可以采用平面栅、槽栅或者V型栅等结构,同时,可集成单个或多个元胞结构61,多个并联的元胞61可共用同一个终端结构62,因此大大减小器件版图面积,降低工艺成本。 The lateral high voltage planar gate device may be employed, or a V-shaped gate trench gate structure, etc., at the same time, may be integrated single or multiple cellular structure 61, a plurality of parallel cellular terminal 61 can share the same structure 62, and therefore greatly reduce small device layout area, reducing the process cost. 横向高压器件的第二N型重掺杂区33用第二P型重掺杂区44代替,可以获得高耐压和低导通电阻的横向IGBT器件。 Lateral IGBT device 44 in place of N-type heavily doped region of the second lateral high-voltage device region 33 by a second heavily doped P-type, a high breakdown voltage and low on-resistance.

[0021] 综上所述,本发明的横向高压功率半导体器件具有导通电阻低、耐压高、版图面积小等诸多优点,降低了工艺难度和成本。 [0021] In summary, high-voltage lateral power semiconductor device according to the present invention having a low ON resistance, high breakdown voltage, and small layout area and many other advantages, reduce the cost and process difficulty. 因此,采用本发明可获得各种性能优良的横向半导体功率器件,具有高速、高集成度、低导通损耗的特点。 Accordingly, the present invention can be obtained using the excellent performance of the lateral semiconductor power device features high speed, high integration, low conduction loss.

附图说明 BRIEF DESCRIPTION

[0022] 下面将结合附图及实施例对本发明作进一步说明,附图中: [0022] The accompanying drawings and the following embodiments of the present invention is further illustrated drawings in which:

[0023]图1是传统横向高压功率半导体器件结构剖面图。 [0023] FIG. 1 is a conventional high-voltage lateral cross-sectional view of the device structure of the power semiconductor.

[0024]图2是本发明提供的平面栅横向高压功率半导体器件结构剖面图,包括纵向超结元胞结构61和终端结构62,元胞采用P型掺杂条43和N型漂移区31构成的纵向超结结构。 [0024] FIG. 2 is a transverse plane of the gate high voltage power semiconductor device of the present invention provides a cross-sectional view, including cellular longitudinal superjunction structure 61 and the termination structure 62, using the cellular strip 43 and P-type doped N-type drift region 31 is formed vertical super junction structure.

[0025]图3是传统横向高压功率器件和本发明提供的横向高压功率半导体器件的耐压原理图,其中,(a)是传统器件的耐压原理图;(b)是本发明器件的耐压原理图。 [0025] FIG. 3 is a schematic diagram of a lateral pressure high-voltage power semiconductor device and the conventional lateral high voltage power device provided by the present invention, wherein, (A) is a schematic diagram of a conventional pressure device; (b) a resistance device of the invention pressure schematic.

[0026]图4是本发明提供的浅槽栅横向高压功率半导体器件结构剖面图。 [0026] FIG. 4 is a shallow trench gate structure of a transverse sectional view of high voltage power semiconductor device of the present invention is provided.

[0027]图5是本发明提供的深槽栅横向高压功率半导体器件结构剖面图。 [0027] FIG. 5 is a lateral high voltage deep trench-gate power semiconductor device of the present invention provides a cross-sectional view of FIG.

[0028]图6是本发明提供的平面栅横向高压功率半导体器件结构剖面图,终端结构62中不包含N型掺杂条34。 [0028] FIG. 6 is a transverse plane of the gate high voltage power semiconductor device of the present invention provides a cross-sectional view, the structure of the terminal 62 is not included in article 34 N-type dopant.

[0029] 图7是本发明提供的一种新型的横向IGBT器件结构剖面图,其中,N型重掺杂漏极接触区33采用P型重掺杂漏极接触区44代替。 [0029] FIG. 7 is a novel structure of a lateral IGBT according to the present invention provides a cross-sectional view of the device, wherein, N-type drain contact region 33 heavily doped P-type heavily doped drain contact region 44 in place.

[0030] 图8是本发明提供的平面栅横向高压功率半导体器件结构剖面图,器件集成了多个纵向超结元胞结构61。 [0030] FIG. 8 is a sectional view of a planar gate structure of a semiconductor lateral high voltage power device according to the present invention provides, a device integrates a plurality of longitudinal cellular superjunction structure 61.

[0031]图9是本发明提供的槽栅横向高压功率半导体器件结构剖面图,器件集成了多个纵向超结元胞结构61。 [0031] FIG. 9 is a transverse sectional view of high voltage power semiconductor trench gate structure of the present invention to provide a device, a device integrates a plurality of longitudinal cellular superjunction structure 61.

[0032]图10是传统横向高压功率半导体器件和本发明提供的横向高压功率半导体器件击穿时,器件体内的电势分布图,其中,(a)是传统横向高压器件击穿时电势分布图;(b)是本发明提供的横向高压功率半导体器件击穿时的电势分布图。 [0032] FIG. 10 is a lateral high voltage power semiconductor device of a conventional lateral high voltage power semiconductor device and the present invention provides the breakdown potential of the device in vivo profile, wherein, (A) is a potential profile view of a conventional lateral high voltage breakdown of the device; (b) is a lateral high-voltage potential when the power semiconductor device of the present invention provides a breakdown profile.

[0033]图11是传统横向高压功率器件和本发明提供的横向高压功率半导体器件击穿时,器件的横向电场分布图,包括表面电场和体内电场。 [0033] FIG. 11 is a lateral high voltage power semiconductor device and a conventional lateral high voltage power device of the present invention provides a breakdown of the transverse electric field profile of the device, including the body surface electric field and the electric field.

具体实施方式 detailed description

[0034] 一种横向高压功率半导体器件,如图2所示,包括至少一个或一个以上的纵向超结元胞结构61和终端结构62 ;多个纵向超结元胞结构61沿器件横向或宽度方向紧密堆积在一起,形成整体纵向超结元胞结构;所述终端结构62位于整体元胞结构的外侧或外围。 [0034] A lateral high voltage power semiconductor device 2, comprising at least one or more longitudinal superjunction structure cellular structure 62 and a terminal 61; a plurality of longitudinal cellular super junction structure 61 in the lateral width of the device or direction close packing together to form a unitary cellular longitudinal superjunction structure; the terminal structure 62 or positioned outside the periphery of the overall cellular structure.

[0035] 所述纵向超结元胞结构61包括位于P型衬底I表面的N型漂移区31,位于N型漂移区31顶部一侧的P型体区41,P型体区41中具有分别与位于器件表面源极金属52相连的P+源极接触区42和N+源极接触区32 ;P型体区41下方的N型漂移区31中具有P型掺杂条43,P型掺杂条43与旁边的N型漂移区31形成超结结构,超结结构与超结结构下方的N型漂移区31构成具有部分超结结构的漂移区;栅极结构由栅氧化层23和多晶硅栅电极51构成,其中栅氧化层23与N型漂移区31和P型体区41相接触,多晶硅栅电极51与源极金属52之间通过介质层22相互隔离。 [0035] The cellular longitudinal superjunction structure 61 includes an N-type drift region surface of the P-type substrate I 31, P-type body region 41 is located in the top side 31 of the N-type drift region, P-type body region 41 having respectively, at the surface of the source device electrode metal 52 is connected to a P + source contact region 42 and the N + source contact region 32; P-type body region 41 N-type drift region below 31 having a P-type doped strips 43, P-type doping Article 43 adjoining the N-type drift region 31 form a super junction structure, N-type drift region of the super junction structure below the superjunction structure portion 31 constitutes the drift region having a super-junction structure; gate structure by a gate oxide layer 23 and polysilicon gate constituting the electrode 51, wherein the gate oxide layer 23 in contact with the N-type drift region 31 and P-type body region 41, isolation between the polysilicon gate electrode 51 and source metal layer 52 through the dielectric 22.

[0036] 所述终端结构62,包括N型漂移区31、N型掺杂条34、N型重掺杂漏极接触区33和介质槽2 ;终端结构62中N型漂移区31的顶部一侧是与漏极金属53相连的N型重掺杂漏极接触区33,N型掺杂条34位于N型重掺杂漏极接触区33下方的N型漂移区31中,且与N型重掺杂漏极接触区33相接触;介质槽2位于N型掺杂条34和所述纵向超结元胞结构61的P型掺杂条43之间,介质槽2和N型掺杂条34下方保留部分N型漂移区31作为电流通道,漏极金属53和源极金属52之间通过介质层22相互隔离。 The [0036] termination structure 62, including an N-type drift region 31, strip 34 is doped N-type, heavily doped N-type drain contact region 33 and a medium tank 2; top terminal structure 62 in the N-type drift region 31, a the drain side is connected to the metal 53 N-type drain contact region 33 is heavily doped, N-type dopant article 34 in the N-type heavily doped region 33 N-type drift region beneath the drain contact 31, and the N-type the heavily doped drain contact region 33 is in contact; 43, medium tank 2 and N-type doped P-type dopant strip and the longitudinal strip 234 superjunction cellular structure 61 of the N-type doped dielectric strips positioned grooves the lower portion 34 to retain the N-type drift region 31 as a current path between the drain 53 and source metal 52 are isolated from the metal layer 22 through the dielectric.

[0037] 本发明通过在N型漂移区31中引入P型掺杂条43和N型掺杂条34,优化器件导通电阻和击穿电压,同时采用介质槽2耐压,可以减小版图面积,降低制造成本。 [0037] The present invention 31 incorporated in the N-type drift region 43 and P-doped N-type dopant bar strip 34, optimization of the device on-resistance and breakdown voltage, while using the pressure medium tank 2, the layout can be reduced area, and reduce the manufacturing cost. 采用本发明可获得各种性能优良的横向高压功率半导体器件,具有高速、高集成度、低导通损耗的特点。 According to the present invention is excellent in various properties can be obtained lateral high voltage power semiconductor device having the characteristics of high speed, high integration, low conduction loss.

[0038] 本发明在元胞结构61的N型漂移区31中引入P型掺杂条43,P型掺杂条43与N型漂移区31构成纵向超结结构,辅助耗尽N型漂移区31,优化器件纵向电场。 [0038] In the present invention, 31 P-type dopant introduced into the N-type drift region strip cellular structure 61 of 43, P-type dopant longitudinal strip 43 constitutes the super junction structure and the N-type drift region 31, N-type drift region assisted depletion 31, the longitudinal electric field optimization device. 终端结构中引入的N型掺杂条34与N型漂移区31形成N+N结,N型掺杂条34的浓度较高,为开态电流提供低阻通道,从而降低器件导通电阻。 Termination structure introduced in article 34 and N-type doped N-type drift region 31 is formed N + N junction, an N-type dopant concentration higher strip 34 provides a low resistance path for the on-state current, to reduce device on-resistance. 器件耐压时,N型掺杂条34和P型掺杂条43在漂移区中引入两个新的电场尖峰,增强介质槽电场,从而提高器件的击穿电压。 When the breakdown voltage, N-doped P-type doped bars 34 and 43 introduce two new article peak electric field in the drift region, the electric field enhancing medium tank, thereby improving the breakdown voltage of the device. 器件的横向耐压主要由终端结构62的介质槽2决定,采用介质槽2耐压可以减小版图面积,降低工艺成本。 Lateral pressure device 2 is mainly determined by the dielectric trench termination structure 62, using 2 pressure medium tank layout area can be reduced, reducing the process cost. 本发明提供的横向高压功率半导体器件可以采用平面栅、槽栅或V型栅等结构,应用灵活。 Lateral high voltage power semiconductor device according to the present invention may be employed to provide the gate plane, or V-shaped gate trench gate structure such as flexible in application. 器件可集成单个或多个纵向超结元胞结构61,多个元胞可以共用同一个终端结构62,进一步减小版图面积,降低工艺成本。 Single or multiple devices may be integrated cellular longitudinal super-junction structure 61, a plurality of cellular terminals can share the same structure 62 to further reduce the layout area, reducing the process cost.

[0039] 本发明提供的横向高压功率半导体器件,可以采用平面栅、槽栅或V型栅等结构,相对平面栅而言,选择槽栅结构的元胞可以做的更小,因为槽栅的沟道是纵向,沟道长度由P型体区41的结深决定,而平面栅的沟道长度由P型体区41的长度决定。 [0039] The lateral high voltage power semiconductor devices provided by the invention, the gate may be planar, V-shaped or trench gate like the gate structure, relatively planar gate, the gate structure selected cellular groove can be made smaller, since the trench gate It is a longitudinal channel, the channel length is determined by the junction depth of the P type body region 41, and the channel length of the gate length is determined by the plane P-type body region 41.

[0040]图3是传统横向高压功率器件和本发明提供的横向高压功率半导体器件的耐压原理图,其中,(a)是传统横向高压器件的耐压原理图,其对应的传统器件结构如图1所示,当器件耐压时,N型漂移区31耗尽,剩下大量正的电离施主电荷,而只有P型体区41和P型重掺杂源极接触区42耗尽时,剩下负的电离受主杂质,使得介质槽2内的电场线,从N型重掺杂漏极接触区33穿过介质槽2指向P型体区41和P型重掺杂源极接触区42,如图3Ca)所示,在源端A点和漏端B点处电场线过度集中,导致器件提前击穿。 [0040] FIG. 3 is a schematic diagram of a lateral pressure high-voltage power semiconductor device and the conventional lateral high voltage power device provided by the present invention, wherein, (A) is a schematic diagram of a conventional voltage lateral high voltage devices, the conventional device structure, such as the corresponding as shown in FIG. 1, when the breakdown voltage, N-type drift region 31 is depleted, the remaining large amount of positive charge ionized donor, and only the P-type body region 41 and the P-type heavily upon depletion of source contact region 42 doped, the remaining negative ionized acceptor impurity, such that the electric field lines in the dielectric tank 2, from the N + drain contact region 33 through the P type body region 2 points medium tank 41 and a P + source contact region 42, FIG 3Ca), the excessive concentration of the source terminal and the drain terminal of the point A at point B field lines, resulting in breakdown of the device in advance.

[0041] 图3 (b)是本发明提供的横向高压功率半导体器件的耐压原理图,与图(a)不同的是,本发明在介质槽2的两侧引入了N型掺杂条34和P型掺杂条43,P型掺杂条43的引入增加了N型漂移区的浓度。 [0041] FIG. 3 (b) is a schematic diagram of a lateral pressure high-voltage power semiconductor device according to the present invention provided with the view (a) except that, in the present invention is media on both sides of the tank 2 is introduced into the N-type doped Article 34 bar 43 and P-type doped, P-type dopant introduced into the strip 43 increases the concentration of the N-type drift region. P型掺杂条43和N型漂移区31构成纵向超结结构,关态时,P型掺杂条辅助耗尽N型漂移区31,在漂移区和介质槽2的界面处引入新的电场尖峰,提高体硅电场,从而使得介质槽电场增强,器件耐压增大。 Bar 43 and P-type doped N-type drift region 31 constituting the longitudinal super junction structure, when the OFF state, the depletion of auxiliary P-doped N-type drift region 31, the introduction of a new electric field at the interface of the drift region and the medium tank 2 spikes, to improve the bulk silicon field, so that the electric field enhancement medium tank, the breakdown voltage is increased. 耗尽的P型掺杂条在介质槽左侧引入大量负的电离受主电荷,调制介质槽内的电场线在源端的分布,避免电场线在源极过度集中,防止器件提前在A'点击穿。 P-type dopant introduced into the large number of negative strip depletion on the left side of the main charge by ionization of the medium slot, the electric field lines are distributed modulation medium source vessel, to avoid excessive concentration of electric field lines at the source electrode, in advance to prevent the device A 'clicks wear. N型掺杂条34浓度较高,耗尽的N型掺杂条剩下大量正的电离施主电荷,从而调制介质槽的电场线在漏端的分布,避免电场线在漏电极集中,防止器件提前在B'点击穿,从而提高器件的击穿电压。 Article 34 higher N-type dopant concentration, the depletion of the N-type dopant remaining large pieces of ionized donor positive charge, so the electric field at the drain end of the distribution line modulation medium tank, to avoid the electric field concentration on the drain electrode line, to prevent the advance device in B 'breakdown, thereby improving the breakdown voltage of the device. 比较图3 (a)和(b)可见,本发明提供的高压器件的介质槽电场线分布均匀,不会在源端和漏端过度集中,这使得器件体内电场增强,电场与横坐标围城的面积大大增加,即器件的击穿电压大大提高。 Comparison of FIG. 3 (a) and (b) visible, high-voltage electric field lines medium tank device of the present invention provides uniform distribution, without excessive concentration of the source and drain ends, which makes the enhanced electric field inside the device, the electric field and the abscissa Siege area increased significantly, i.e., the breakdown voltage of the device is greatly improved.

[0042] 槽栅横向高压功率器件的耐压原理与平面栅高压功率器件相同,相比平面栅器件而言,槽栅器件的元胞结构61可以做的更小,从而减小版图面积,降低工艺成本。 [0042] The principle of the trench gate breakdown voltage lateral high voltage power device with high voltage power same planar gate device, compared to a planar gate device, cellular device trench gate structure 61 can be made smaller, thereby reducing the layout area, reducing process costs. 图4是本发明提供的浅槽栅横向高压功率半导体器件结构剖面图。 FIG 4 is a shallow trench gate structure of a transverse sectional view of high voltage power semiconductor device of the present invention is provided. 浅槽栅器件耐压时,漂移区中的电场容易在槽氧化层23的尖角处过度集中,如图中C点,导致器件提前发生击穿。 When shallow trench gate breakdown voltage, the electric field in the drift region is easily excessive concentration of the groove at the sharp oxide layer 23, as shown in point C, resulting in device breakdown occurs earlier.

[0043]图5是本发明提供的深槽栅横向高压功率半导体器件结构剖面图,深槽栅器件和浅槽栅器件在结构上除了槽栅的深浅之外,没有其他区别,其中深槽栅器件的槽栅延伸到了P型衬底I中。 [0043] FIG. 5 is a lateral high voltage deep trench-gate power semiconductor device of the present invention provides a cross-sectional view, the deep grooves and shallow grooves gate devices on a gate device structures other than the depth of the gate groove, no other differences, wherein the gate deep grooves the groove extends to the gate device I, P-type substrate. 相比浅槽栅器件,如图4,深槽栅器件有几个方面的优势,一方面,深槽栅和N型漂移区31构成MIS (Metal Insulator Semiconductor)电容,关态时,MIS电容使N型漂移区31和槽氧化层23界面处积累大量空穴,辅助耗尽N型漂移区,优化器件纵向电场;另一方面,开态时,MIS电容的作用,使N型漂移区31和槽氧化层23界面处积累大量电子,增加N型漂移区的浓度,为开态电流提供低阻通道,从而降低器件导通电阻;再一方面,将槽栅深入P型衬底I中,可以避免槽氧化层23底部尖角处的电场过度集中,如图中D点,从而提高器件的击穿电压;最后,深槽栅还可以起到器件之间的隔离作用。 Compared shallow trench gate device 4, the gate device has deep grooves several advantages, on the one hand, and deep trench gate N-type drift region 31 constituting the MIS (Metal Insulator Semiconductor) capacitor, when the off state, MIS capacitor so N-type drift region 31 and the accumulation of a large number of holes at the interface slot oxide layer 23, N-type drift region assisted depletion, device optimization longitudinal electric field; on the other hand, in the on state, MIS capacitor effect, the N-type drift region 31 and groove accumulated at the interface oxide layer 23 a large number of electrons, increasing the concentration of the N-type drift region, provides a low resistance path for the current on-state, thereby reducing the on-resistance of the device; another aspect, the depth of the trench gate P-type substrate I may be field oxide layer to avoid sharp corners at the groove bottom of the excessive concentration of 23, as shown in point D, thereby improving the breakdown voltage of the device; and finally, a deep groove can also play a gate isolation between devices.

[0044] 图6是本发明提供的一种平面栅横向高压功率半导体器件结构剖面图,器件的终端结构62包括介质槽2、N型漂移区31和N型重掺杂漏极接触区33,但不包含N型掺杂条34。 [0044] FIG. 6 is a transverse plane of the gate high voltage power semiconductor device of the present invention provides a cross-sectional view, the structure of the terminal device 62 comprises medium tank 2, N-type drift region 31 and heavily doped N-type drain contact region 33, but it does not comprise N-type dopant strip 34. 该结构的耐压和导通电阻的关系没有图2的结构优化,这是因为,N型掺杂条34不仅在关态时提供大量正的电离施主电荷,调制介质槽内的电场线分布,避免漏端电场线过度集中。 Relationship between voltage and on-resistance of the structure is not optimized structure of FIG. 2, since, N-doped strip 34 not only provide a large number of positive charge ionized donor, modulation field lines distribution medium tank during the OFF state, avoid excessive concentration of the drain end of field lines. 在开态时,N型掺杂条还能为开态电流提供低阻通道,降低器件导通电阻。 In the open state, N-type dopant can also provide a low resistance path for the strip on-state current, to reduce device on-resistance.

[0045]图7是本发明提供的一种新型的横向IGBT器件结构剖面图,集成在P型衬底I上,包括N型漂移区31、P型体区41、N型重掺杂发射极接触区32、P型重掺杂发射极接触区42、介质槽2、P型掺杂条43、N型掺杂条34和P型重掺杂集电极接触区44 ;P型重掺杂集电极接触区44的下面是N型掺杂条34,N型掺杂条34的左侧是介质槽2 ;栅氧化层21上面是多晶硅栅电极51,发射极金属56位于P型体区41上面,集电极金属57位于P型重掺杂集电极接触区44表面;多晶娃栅电极51、发射极金属56和集电极金属57之间通过介质层22相互隔离。 [0045] FIG. 7 is a novel structure of a lateral IGBT according to the present invention provides a cross-sectional view of a device, integrated on a P-type substrate I, including N-type drift region 31 is, P-type body region 41 is, heavily doped N-type emitter contact region 32, the P-type heavily doped emitter contact region 42, the medium tank 2, P-type doped strips 43, N-type doped bars 34 and P + collector contact region 44 is; P + collector 44 below the electrode contact region is doped N-type strip 34, the left N-type dopant strip 34 is a dielectric tank 2; upper gate oxide 21 is a polysilicon gate electrode 51, emitter 41 is located above the P type body region 56 a metal electrode The collector 57 is located in the metal surface of the heavily doped P-type collector contact region 44; baby polycrystalline gate electrode 51, emitter 56 isolation between the metal electrode and the metal collector electrode 57 through the dielectric layer 22. 采用本发明的结构,可将传统IGBT器件的集电极从器件底部横向引出,栅电极、发射极和集电极都在表面,使得器件易于和常规电路集成,同时采用终端结构62横向耐压,可以大大减小器件版图面积。 Configuration of the present invention, a conventional collector of IGBT device may be laterally withdrawn from the bottom of the device, the gate electrode, emitter and collector are on the surface, and makes the device easy to conventional integrated circuit, while using the termination structure 62 lateral pressure, can greatly reduce the layout area of ​​the device.

[0046]图8是本发明提供的平面栅横向高压功率半导体器件结构剖面图,器件集成多个纵向超结元胞结构61。 [0046] FIG. 8 is a sectional view of a semiconductor device structure transverse plane of the gate high voltage power provided by the invention, super-junction device incorporates a plurality of longitudinal cellular structure 61. 纵向超结元胞结构的N型漂移区31中引入P型掺杂条43,形成纵向超结结构,并增加了N型漂移区的浓度。 Cellular longitudinal super junction structure of the N-type drift region 31 in the P-type dopant introduced into the strip 43, a longitudinal super junction structure, and increasing the concentration of N-type drift region. 开态时,更高的N型漂移区浓度降低了器件的导通电阻,关态时,P型掺杂条43辅助耗尽N型漂移区31,优化器件纵向电场,提高器件击穿电压。 In the on state, the higher the concentration of N-type drift region reduces the on-resistance of the device, when the OFF state, P-type dopant depletion auxiliary bar 43 N-type drift region 31, the longitudinal electric field optimization device to improve device breakdown voltage. 多个元胞结构共用一个终端结构62,大大减小器件版图面积,从而降低工艺成本。 A plurality of cellular structures share a termination structure 62, which reduces the layout area of ​​the device, thus reducing process cost. 终端结构中引入N型掺杂条34,可以进一步缓解器件的耐压和导通电阻之间的矛盾关系。 Terminal N-type dopant introduced in the structure of strip 34, may further ease the contradiction relationship between breakdown voltage and on-resistance of the device.

[0047]图9是本发明提供的槽栅横向高压功率半导体器件剖面图,器件集成多个纵向超结元胞结构61。 [0047] FIG. 9 is a transverse cross-sectional view of the semiconductor device in FIG trench gate high voltage power provided by the invention, super-junction device incorporates a plurality of longitudinal cellular structure 61. 除了栅电极的结构不同之外,槽栅结构器件和图8的结构没有其他差别,工作原理也相同。 Except for the structure of the gate electrode, the structure of trench gate structure of the device of FIG. 8 and no other differences, the principle is the same. 相比平面栅而言,槽栅结构的元胞结构做的更小,可以更进一步减小版图面积。 Compared to planar-gate, the structure of the cellular structure of the gate groove made smaller, the layout area can be further reduced.

[0048] 为了使本发明所要解决的技术问题、技术方案及有益效果更加清楚明白,以图2为实施例,并和传统结构对比,对本发明作进一步详细说明。 [0048] In order to make the technical problem to be solved by the present invention, technical solutions and beneficial effects more clearly understood, an embodiment in FIG. 2, and comparative and conventional structure, the present invention is described in further detail.

[0049] 如图2所示,本发明提供的平面栅横向高压功率半导体器件包括纵向超结元胞结构61和终端结62,其中,N型漂移区31引入了P型掺杂条43和N型掺杂条34。 [0049] As shown, the transverse plane of the gate high voltage power semiconductor device according to the present invention comprises longitudinal superjunction structure 61 and the cellular terminal junction 622, where, N-type drift region 31 of P-type dopant introduced into strip 43 and N type doped strip 34. 引入的P型掺杂条43和N型漂移区31构成纵向超结结构,P型掺杂条辅助耗尽N型漂移区,并引入一个纵向电场峰值,优化器件纵向电场,提高器件纵向耐压。 Bar 43 and P-type doped N-type drift region 31 constituting the incorporated longitudinal super junction structure, a P-type doping of auxiliary depletion N-type drift region, and introduced into a vertical electric field peak, a vertical electric field optimization device to improve device breakdown voltage longitudinal . 耗尽的P型掺杂条43和N型掺杂条34分别为N型漂移区提供电离受主电荷和电离施主电荷,优化介质槽内的电场分布,缓解漂移区电场在源端和漏端的过度集中,提高器件的击穿电压。 P-type dopant depletion strip 43 and strip 34 are N-type doped N-type drift region is provided by the ionization and the main charge ionized donor charge, optimization of the electric field distribution medium tank, alleviate electric field drift region at the source end and the drain end excessive concentration, improve the breakdown voltage. 开态时,N型掺杂条为开态电流提供低阻通道,降低器件导通电阻。 In the on state, N-type doped to provide a low resistance path for the strip on-state current, to reduce device on-resistance. 图10 (b)给出了本发明提供的横向高压器件击穿时的电势分布图,其中,N型漂移区31的浓度为2el5Cm_3、深度为25微米,介质槽2的宽度9微米,深度20微米,N型掺杂条34的浓度为1.3el6CnT3,P型掺杂条浓度3.2e16cnT3,N型掺杂条和P型掺杂条宽度均为0.5微米,P型衬底浓度为1.5el4CnT3。 FIG. 10 (b) shows the potential distribution map of the present invention provides a lateral high-voltage breakdown device, wherein the concentration of N-type drift region 31 is 2el5Cm_3, a depth of 25 m, a width of 9 micrometers medium tank 2, the depth 20 m, N-type dopant concentration of the bar 34 is 1.3el6CnT3, P-type dopant concentration article 3.2e16cnT3, N-doped and P-doped strip the strip width are 0.5 m, P-type substrate concentration 1.5el4CnT3. 由图,器件体内源端和漏端的电势线分布较为均匀,漂移区电势线在源极和漏极下方分布类似纵向超结结构的电势分布,P型衬底耗尽将近55微米。 FIG vivo source device and the drain terminal potential lines more evenly distributed, the drift region potential line potential super-junction structure similar to the longitudinal distribution of the source and the drain under the distribution, P-type substrate depletion nearly 55 microns. 图10 (a)是传统横向高压器件击穿时的电势分布图,其中,N型漂移区浓度为5el4Cm_3,P型衬底耗尽仅35微米。 FIG. 10 (a) is a potential profile view of a conventional lateral high voltage breakdown device, wherein, N-type drift region concentration 5el4Cm_3, P-type substrate is depleted only 35 microns. 与本发明结构相比,传统横向高压器件的电势线在源极和漏极较密集,越往体内电势线分布越稀疏,导致器件容易在源极和漏极与介质槽2接触的界面处发生击穿,如图3 (a)中的A点和B点,因此器件耐压较低。 Compared with the structure of the present invention, a conventional lateral high voltage potential line denser devices in the source and drain, the potential lines in vivo to more sparsely distributed, cause the device to easily occur at the interface of the source and the drain of the second contact medium tank breakdown, 3 (a) of the point a and B in FIG therefore lower breakdown voltage. 同时,相比而言,本发明结构的衬底辅助耗尽效应较为明显,器件具有更好的纵向耐压。 Meanwhile, compared with the structure of the present invention, the auxiliary substrate depletion effect is significant, the device having a better longitudinal pressure.

[0050] 更近一步的分析器件击穿时的电场分布,图11是传统横向高压功率器件和本发明提供的横向高压功率半导体器件击穿时的横向电场分布,图中实心曲线是本发明结构的横向电场分布,空心曲线是传统横向高压器件的横向电场分布。 [0050] step closer analysis of the electric field distribution when the device breakdown, FIG. 11 is a transverse electric field of the lateral high voltage power semiconductor device and a conventional lateral high voltage power device of the present invention provides the distribution of breakdown, the solid curve is a structural drawing of the present invention the transverse electric field distribution, the hollow profile is a conventional transverse electric field distribution in the lateral high voltage devices. 相比传统结构,本发明结构的表面电场和体内横向电场都大大增加,这是因为,引入的P型掺杂条43和N型掺杂条34耗尽时,在介质槽两侧引入负的电离受主电荷和正的电离施主电荷,调制介质槽内的电场在源端和漏端的分布,避免电场线在源端和漏端过度集中,器件提前发生击穿。 Compared with the conventional structure, the body surface electric field and the transverse structure of the present invention are greatly increased, because, when the bar 43 and P-type doped N-type dopant introduced into the strip 34 is depleted, the media on both sides of the introduction groove negative and the distribution of the acceptor ionization positive charge of ionized donor charge, the electric field modulation medium tank source and drain ends, to avoid excessive concentration of electric field lines at the source and drain ends, the device breakdown occurs earlier. 同时,引入两个新的电场尖峰增强介质槽电场,从而提高器件的耐压。 At the same time, the introduction of two new peak electric field enhancement medium tank, thereby improving the breakdown voltage of the device. 图10是通过MEDICI 二维器件仿真给出的两种器件击穿时的电势分布图,每两条等势线的电势差为20V,传统结构的耐压只有400V,其导通电阻将近370m Ω.cm_2,而本发明结构的耐压高达715V,但导通电阻仅有55mΩ.cm_2,本发明结构打破了传统硅极限,在获得高的击穿电压的同时,大大降低了导通电阻。 FIG 10 is a potential profile view of two devices by the two-dimensional device simulator MEDICI given breakdown electric equipotential lines of every two potential difference of 20V, only the structure of the conventional voltage 400V, ON resistance nearly 370m Ω. CM_2, the breakdown voltage structure of the present invention up to 715V, but only 55mΩ.cm_2 on-resistance, the structure of the present invention breaks the conventional silicon limit in obtaining a high breakdown voltage, while greatly reducing the on-resistance.

[0051] 本发明提供的横向高压功率半导体器件由元胞结构和终端结构构成,元胞采用纵向超结结构不仅缓解耐压BV和导通电阻Rm, @的关系,同时大大减小器件版图面积,降低工艺成本。 [0051] The lateral high voltage power semiconductor device according to the present invention provides a cellular structure consists of a terminal structure and, using cellular longitudinal super junction structure only ease resistor Rm, the relationship between the breakdown voltage BV @ and conduction, while greatly reducing the layout area of ​​the device , reduce process costs. 耗尽的P型掺杂条在介质槽左侧剩下负的电离受主电荷,调制介质槽电场的分布,避免电场线在源端过度集中,导致器件提前击穿。 P-type dopant depletion in the left bar medium tank ionized acceptor remaining negative charge, the distribution of the electric field modulation medium tank, to avoid excessive concentration of electric field lines at the source, causes the device to breakdown in advance. 终端结构包括介质槽2和N型掺杂条34,采用介质槽耐压可以进一步减小版图面积。 2 comprises a dielectric trench termination structure and the N-type dopant strip 34, the pressure medium tank using the layout area can be further reduced. N型掺杂条的引入,为开态电流提供低阻通道,进一步降低器件导通电阻,关态时,耗尽的N型掺杂条在介质槽右侧剩下的电离施主杂质,优化介质槽的漏端电场,避免器件提前在漏极发生击穿,进一步提高器件的击穿电压。 Introducing N-type dopant bars provide a low resistance path for the current on-state, to further reduce the on-resistance of the device, when the OFF state, N-type dopant remaining in the right strip depleted medium bath ionized donor impurity, to optimize the medium field slot drain terminal, the drain to avoid breakdown in the device in advance, to further improve the device breakdown voltage. 同时,N型掺杂条和P型掺杂条引入两个新的电场尖峰,增大硅界面电场,使得介质槽电场增强,器件耐压提高。 Meanwhile, N-doped and P-doped strip article introducing two new peak electric field, the electric field is increased silicon interface, so that the electric field enhancement medium tank, the device breakdown voltage is improved. 器件可以采用平面栅、槽栅或V型栅等结构,还可以集成单个或多个元胞结构。 Planar gate device may be employed, or a V-shaped gate trench gate structure and the like, may also be a single or multiple integrated cellular structures. 本发明提供的横向高压器件,集成在P型衬底上,可以进一步辅助耗尽N型漂移区,优化器件纵向电场,进一步提高器件的击穿电压。 The present invention provides a lateral high-voltage device, integrated on a P-type substrate may be further assisted depletion N-type drift region, the longitudinal electric field optimization means, to further improve the device breakdown voltage.

Claims (3)

  1. 1.一种横向高压功率半导体器件,包括至少一个纵向超结元胞结构(61)和终端结构(62);当所述横向高压功率半导体器件包括多个纵向超结元胞结构(61)和终端结构(62)时,多个纵向超结元胞结构¢1)沿器件横向或宽度方向紧密堆积在一起,形成整体纵向超结元胞结构;所述终端结构(62)位于整体元胞结构的外侧或外围; 所述纵向超结元胞结构(61)包括位于P型衬底(I)表面的N型漂移区(31),位于N型漂移区(31)顶部一侧的P型体区(41),P型体区(41)中具有分别与位于器件表面源极金属(52)相连的P+源极接触区(42)和N+源极接触区(32) ;P型体区(41)下方的N型漂移区(31)中具有P型掺杂条(43),P型掺杂条(43)与旁边的N型漂移区(31)形成超结结构,超结结构与超结结构下方的N型漂移区(31)构成具有部分超结结构的漂移区;栅极结构由栅氧化层(23)和多晶硅栅电极(51)构成,其中栅氧化层(23) A lateral high voltage power semiconductor device, comprising at least one longitudinal superjunction cellular structure (61) and a terminal structure (62); and when the lateral high voltage power semiconductor device comprises a plurality of longitudinal cellular super-junction structure (61) and when the termination structure (62), a plurality of longitudinal cellular super junction structure ¢. 1) closely packed along the transverse or width direction of the device together form an integral longitudinal superjunction cellular structure; said terminal structure (62) is located in the overall cellular structure or outer periphery; the longitudinal superjunction cellular structure (61) comprises a P-type substrate (the I) the N-type drift region (31) of the surface, the N-type drift region (31) at the top side of the P type body region (41), P-type body region (41) having respectively, at the surface of the source (52) connected to a P + source contact region (42) and N + source contact region (32) device; P-type body region ( 41 is) below the N-type drift region (31) having a P-type doped strip (43), a P-type doping strips (43) form a super junction structure, and ultra-super junction structure and the N-type drift region (31) next to N-type drift region below the junction structure (31) constituting the portion of the drift region having a super-junction structure; polysilicon gate electrode gate structure (51) is constituted by a gate oxide layer (23) and wherein the gate oxide (23) N型漂移区(31)和P型体区(41)相接触,多晶硅栅电极(51)与源极金属(52)之间通过介质层(22)相互隔离;所述终端结构(62),包括N型漂移区(31)、N型掺杂条(34)、N型重掺杂漏极接触区(33)和介质槽(2);终端结构(62)中N型漂移区(31)的顶部一侧是与漏极金属(53)相连的N型重掺杂漏极接触区(33),N型掺杂条(34)位于N型重掺杂漏极接触区(33)下方的N型漂移区(31)中,且与N型重掺杂漏极接触区(33)相接触;介质槽⑵位于N型掺杂条(34)和所述纵向超结元胞结构(61)的P型掺杂条(43)之间,介质槽(2)和N型掺杂条(34)下方保留部分N型漂移区(31)作为电流通道,漏极金属(53)和源极金属(52)之间通过介质层(22)相互隔离。 N-type drift region (31) and a P-type body region (41) in contact with each other through the dielectric isolation layer (22) between the polysilicon gate electrode (51) and the source (52); said terminal structure (62), including N-type drift region (31), an N-type doping strips (34), N type heavily doped drain contact region (33) and the medium tank (2); termination structure (62) in the N-type drift region (31) the top side is a drain metal (53) connected to the N + drain contact region (33), an N-type doping strips (34) in the N-type heavily doped (33) beneath the drain contact region N-type drift region (31), and the N-type heavily doped drain contact region (33) in contact; ⑵ medium tank located N-type dopant strip (34) and said longitudinal superjunction cellular structure (61) between the P-type doped strip (43), the medium tank (2) and the N-type dopant strip (34) to retain the lower portion of the N-type drift region (31) as the current channel, drain metal (53) and source metal between (52) isolated from each other by a dielectric layer (22).
  2. 2.根据权利要求1所述的横向高压功率半导体器件,其特征在于,所述栅极结构为平面栅、槽栅或V型栅。 The lateral high voltage power semiconductor device according to claim 1, wherein said gate is a planar gate structure, or a V-shaped gate trench gate.
  3. 3.根据权利要求1所述的横向高压功率半导体器件,其特征在于,将所述终端结构(62)中的N型重掺杂漏极接触区(33)用P型重掺杂集电极接触区(44)代替,可获得横向IGBT器件。 The lateral high voltage power semiconductor device according to claim 1, wherein said terminal structure (62) of the N-type heavily doped drain contact region (33) heavily doped with a P-type collector contact region (44) in place, the lateral IGBT device can be obtained.
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