CN105070760B - A kind of power MOS (Metal Oxide Semiconductor) device - Google Patents
A kind of power MOS (Metal Oxide Semiconductor) device Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 156
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 18
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 18
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- 229910052751 metal Inorganic materials 0.000 claims description 10
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0692—Surface layout
- H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
Abstract
The invention belongs to power semiconductor device technology field, is related to a kind of power MOS (Metal Oxide Semiconductor) device.The present invention includes structure cell, drain extension region and media slot terminal with high K dielectric extension grid structure, and multiple structure cell arranged in parallel so that device has the characteristics that：Taking into account VDMOS can the advantages of producing high current and LDMOS easy of integration in parallel；During forward conduction, how sub- accumulation layer is produced close to the drift region of high K dielectric side, continuous low impedance path is formed, significantly reduces and compare conducting resistance；When reversely pressure-resistant, high K dielectric assisted depletion drift region, drift region electric field is modulated, pressure-resistant and reduction can be improved and compare conducting resistance；Media slot terminal can reduce device size, save chip area.
Description
Technical field
The invention belongs to power semiconductor device technology field, be related to it is a kind of have can Integrated Trait power MOS (Metal Oxide Semiconductor) device.
Background technology
Power MOSFET (Metal Oxide Semiconductor Filed-Effect Transistor) needs long
Drift region and low drift doping concentration are high pressure-resistant to realize, this causes than conducting resistance Ron.spExist between pressure-resistant BV
Ron,sp∝BV2.3~2.6Relation, i.e. the silicon limit.Therefore, with the pressure-resistant increase of device, than conducting resistance, exponentially trend rises,
Power consumption greatly increases.
It is suggested using high K (K is relative dielectric coefficient) medium to improve the thought of device performance, this structure can be delayed
Solve the charge imbalance problem in superjunction.Reversely it is pressure-resistant when, high K dielectric can be with assisted depletion drift region, the electricity of optimised devices
Field distribution.This can not only improve drift region concentration, and conducting resistance is compared in reduction；Meanwhile the pressure-resistant of device is also improved.It is related
Document (X.B.Chen.superjunction voltage sustaining layer with alternating
semiconductor and high-K dielectric regions.U.S.Patent 7,230,310B2,jun.12,
2007)
The device of power VDMOSFET have can in parallel the characteristics of producing high current and small cellular size, and the cellular chi of device
It is very little not increase with pressure-resistant increase.The doping concentration of device is improved using high K dielectric, device can be significantly reduced
Ron.sp.But the problem of presence can not integrate in the application of power VDMOSFET, power VDMOSFET is limited in power integrated circuit
Utilization.
Power LDMOS has the characteristics of being easily integrated, and is widely used in power integrated circuit.However, and power VDMOSFET
Compare, the power LDMOS drift region length that is lightly doped increases with the rise of breakdown voltage, causes chip area equal proportion to increase
Add so that LDMOS has big ratio conducting resistance.
The content of the invention
It is to be solved by this invention, aiming above mentioned problem, for alleviate power MOS (Metal Oxide Semiconductor) device it is pressure-resistant with than conducting resistance
Contradictory relation, propose a kind of power MOS (Metal Oxide Semiconductor) device.
To achieve the above object, the present invention adopts the following technical scheme that：
A kind of power MOS (Metal Oxide Semiconductor) device, as shown in figure 1, including the second conductive type semiconductor substrate 1 and positioned at the second conductive-type
First conduction type heavily-doped semiconductor drain region 61 of the upper surface of type Semiconductor substrate 1；The first conduction type heavy doping half
The upper surface both ends of conductor drain region 61 have the first conduction type heavily-doped semiconductor drain extension region 62；The first conduction type weight
There are multiple structure cells in parallel between doped semiconductor drain extension region 62；The first conduction type heavily-doped semiconductor leakage
There is media slot 5 between extension area 62 and structure cell, first medium layer is filled with the media slot 5；The structure cell
Including grid structure, the first conductive type semiconductor drift region 2 and the second conductive type semiconductor body area 3；Described first is conductive
The conductive type semiconductor body area 3 of type semiconductor drift region 2 and second is located at grid structure both sides；First conduction type half
Conductor drift region 2 is between the second conductive type semiconductor body area 3 and the first conduction type heavily-doped semiconductor drain region 61；Institute
Grid structure is stated to be made up of Metalized gate, gate oxide 9 and second dielectric layer 4；The gate oxide 9 is located at Metalized gate
Between both sides and the first conductive type semiconductor drift region 2 and the second conductive type semiconductor body area 3；The second dielectric layer 4
Between Metalized gate and the lower surface of gate oxide 9 and the upper surface of the first conduction type heavily-doped semiconductor drain region 61；Institute
Stating has the first conduction type heavily-doped semiconductor source region 8 and the second conduction type weight in the second conductive type semiconductor body area 3
Doped semiconductor body contact zone 7, in the second conductive type semiconductor body area 3 between the grid structure, the second conduction type
Heavily-doped semiconductor body contact zone 7 is between the first conduction type heavily-doped semiconductor source region 8；The grid structure and medium
In the second conductive type semiconductor body area 3 between groove 5, the second conduction type heavily-doped semiconductor body contact zone 7 is led with first
Electric type heavily-doped semiconductor source region 8 is separate；The first conduction type heavily-doped semiconductor source region 8 and the second conductive-type
The upper surface of type heavily-doped semiconductor body contact zone 7 has source metal, the first conduction type heavily-doped semiconductor leakage extension
The upper surface of area 62 has drain metal.
Further, the first medium layer filled in the media slot 5 is to be made up of a variety of media.
Further, the dielectric constant for a variety of media filled in the media slot 5 is heavily doped from close first conduction type
Miscellaneous one end of semiconductor drain extension region 62 gradually increases to one end close to structure cell.
Further, there is source metal in the media slot 5.
Further, there is gate metal in the media slot 5.
Further, there is gate metal in the media slot 5, second between the grid structure and media slot 5 is led
In electric type semiconductor body area 3, the second conduction type heavily-doped semiconductor body contact zone 7 is located at the first conduction type heavy doping half
Between conductor source region 8.
Further, the doping concentration of the first conductive type semiconductor drift region 2 is successively decreased from bottom to top.
Further, the first conductive type semiconductor drift region 2 is got over closer to Metalized gate, its doping concentration
It is high.
Further, have in the first conductive type semiconductor drift region 2 and be mutually juxtaposed with it in vertical direction
Second conductive type semiconductor layer 11, in the first conductive type semiconductor drift region 2 between grid structure, the second conductive-type
Type semiconductor layer 11 is between the first conductive type semiconductor drift region 2；First between grid structure and media slot 5 leads
In electric type semiconductor drift region 2, second conductive type semiconductor layer 11 is connected with media slot 5, first conduction type half
Conductor drift region 2 is connected with grid structure.
Further, the second conductive type semiconductor substrate 1 and the first conduction type heavily-doped semiconductor drain region 61
Between there is the 3rd dielectric layer 12.
In the solution of the present invention, second dielectric layer 4 has the high K dielectric of higher dielectric constant, and its dielectric constant K is more than
The dielectric constant of silica.
Beneficial effects of the present invention be take into account VDMOS can in parallel the advantages of producing high current and LDMOS easy of integration；Just
To during conducting, how sub- accumulation layer is produced close to the drift region of high K dielectric side, continuous low impedance path is formed, significantly reduces ratio
Conducting resistance；When reversely pressure-resistant, high K dielectric assisted depletion drift region, drift region electric field modulated, can improve pressure-resistant and reduce than leading
Be powered resistance；Media slot terminal can reduce device size, save chip area.
Brief description of the drawings
Fig. 1 is the structural representation of embodiment 1；
Fig. 2 is the structural representation of embodiment 2；
Fig. 3 is the structural representation of embodiment 3；
Fig. 4 is the structural representation of embodiment 4；
Fig. 5 is the structural representation of embodiment 5；
Fig. 6 is the structural representation of embodiment 6；
Fig. 7 is the structural representation of embodiment 7；
Fig. 8 is a kind of structural representation of embodiment 8；
Fig. 9 is another structural representation of embodiment 8；
Figure 10 is the structural representation of embodiment 9.
Embodiment
The present invention will be described in detail below in conjunction with the accompanying drawings
Technical scheme, high K dielectric extension grid structure, drain extension region and media slot terminal are made full use of, to work(
The electric property of rate MOS device has carried out synthesis improvement and raising.For convenience of description, a kind of work(integrated provided by the invention
Rate MOS device also abbreviation device sometimes.
Embodiment 1
As shown in figure 1, including the second conductive type semiconductor substrate 1 and on the second conductive type semiconductor substrate 1
The first conduction type heavily-doped semiconductor drain region 61 on surface；The upper surface of first conduction type heavily-doped semiconductor drain region 61
Both ends have the first conduction type heavily-doped semiconductor drain extension region 62；The first conduction type heavily-doped semiconductor leakage extension
There are multiple structure cells in parallel between area 62；The first conduction type heavily-doped semiconductor drain extension region 62 and cellular knot
There is media slot 5 between structure, first medium layer is filled with the media slot 5；The structure cell includes grid structure, first
The conductive type semiconductor body area 3 of conductive type semiconductor drift region 2 and second；The first conductive type semiconductor drift region 2
It is located at grid structure both sides with the second conductive type semiconductor body area 3；The first conductive type semiconductor drift region 2 is positioned at the
Between two conductive type semiconductor body areas 3 and the first conduction type heavily-doped semiconductor drain region 61；The grid structure is by metal
Change grid, gate oxide 9 and second dielectric layer 4 to form；The gate oxide 9 is located at Metalized gate both sides and the first conductive-type
Between type drift semiconductor area 2 and the second conductive type semiconductor body area 3；The second dielectric layer 4 be located at Metalized gate and
Between the lower surface of gate oxide 9 and the upper surface of the first conduction type heavily-doped semiconductor drain region 61；Second conduction type half
There is the first conduction type heavily-doped semiconductor source region 8 and the second conduction type heavily-doped semiconductor body to contact in conductor body area 3
Area 7, in the second conductive type semiconductor body area 3 between the grid structure, the second conduction type heavily-doped semiconductor body connects
Area 7 is touched between the first conduction type heavily-doped semiconductor source region 8；Second between the grid structure and media slot 5 leads
In electric type semiconductor body area 3, the second conduction type heavily-doped semiconductor body contact zone 7 is partly led with the first conduction type heavy doping
Body source region 8 is separate；The first conduction type heavily-doped semiconductor source region 8 and the second conduction type heavily-doped semiconductor body
The upper surface of contact zone 7 has source metal, and the upper surface of the first conduction type heavily-doped semiconductor drain extension region 62 has leakage
Pole metal.
The power MOS (Metal Oxide Semiconductor) device proposed by the present invention integrated is with traditional power MOS (Metal Oxide Semiconductor) device difference, of the invention
Structure cell, drain extension region and media slot terminal including extending grid structure with high K dielectric, and multiple structure cells and townhouse
Cloth so that device has the characteristics that：One, taking into account VDMOS can the advantages of producing high current and LDMOS easy of integration in parallel；Two,
During forward conduction, how sub- accumulation layer is produced close to the drift region of high K dielectric side, continuous low impedance path is formed, significantly reduces
Compare conducting resistance；Three, when reversely pressure-resistant, high K dielectric assisted depletion drift region, drift region electric field modulated, can improve pressure-resistant and drop
It is low to compare conducting resistance；Four, media slot terminal can reduce device size, save chip area.
Embodiment 2
As shown in Fig. 2 the power MOS device construction schematic diagram integrated using change K groove media of this example, with embodiment
1 difference is that the first medium layer is made up of a variety of media, and the dielectric constant of the medium is heavily doped by the first conduction type
The miscellaneous lateral side of structure cell 10 of semiconductor drain extension region 62 1 is incremented by.In the present embodiment, the medium of high-k can increase
By force to the assisted depletion of drift region 2, optimize the equipotential lines distribution of its media slot side, it is pressure-resistant to improve device.
Embodiment 3
As shown in figure 3, the power MOS device construction schematic diagram integrated with source field plate of this example, with embodiment 1
Difference is there is metallizing source, both sides and bottom and the first medium layer phase of the metallizing source in the media slot 5
Connect.Metallizing source can be optimized equipotential lines distribution, it is pressure-resistant to be improved device as source field plate with assisted depletion drift region 2.
Embodiment 4
As shown in figure 4, the power MOS device construction schematic diagram integrated with grid field plate of this example, with embodiment 1
Difference is there is Metalized gate, the second conductive type semiconductor body area 3 of the structure cell 10 in the media slot 5
Surface also sets up the first conduction type heavily-doped semiconductor source region 8, and it is located at media slot 5 and partly led with the second conduction type heavy doping
Between body body contact zone 7.Metalized gate is as grid field plate, when reversely pressure-resistant, can be optimized etc. with assisted depletion drift region 2
Gesture line is distributed；In forward conduction, new conducting channel is introduced close to media slot side in drift region 2, increases the electric current of device
Ability.
Embodiment 5
As shown in figure 5, the power MOS device construction schematic diagram integrated that there is grid field plate and become K groove media of this example,
The present embodiment is improved on the basis of embodiment 4, and the media slot 5 is high K dielectric close to the side of structure cell 10, and
Metalized gate is located above high K dielectric.The device of the program, when reversely pressure-resistant, high K dielectric and second Jie in media slot
Play the effect of identical assisted depletion in 4 pairs of drift region 2 of matter layer so that equipotential lines distributes very evenly, and it is pressure-resistant to significantly improve device；
In forward conduction, new conducting channel is introduced close to media slot side in drift region 2, and forms how sub- accumulation layer, is improved
Conducting resistance is compared in the current capacity of device, reduction.
Embodiment 6
As shown in fig. 6, the power MOS device construction schematic diagram integrated with longitudinal varying doping drift region of this example,
Difference with embodiment 1 is that the first conductive type semiconductor drift region 2 is divided into n (n >=2) individual first and led from bottom to top
Electric type semiconductor area, and the doping concentration of the semiconductor region is successively decreased from bottom to top.The drift region 2 of longitudinal varying doping, can
To optimize Electric Field Distribution, it is pressure-resistant to improve device.
Embodiment 7
As shown in fig. 7, the power MOS device construction schematic diagram integrated with variety lateral doping drift region of this example,
Difference with embodiment 1 is that the first conductive type semiconductor drift region 2 is led by vertical n (n >=2) individual first arranged side by side
Electric type semiconductor district's groups are into the semiconductor region is higher closer to Metalized gate, doping concentration.The drift of variety lateral doping
Area 2, there is high doping concentration close to gate electrode side, forming the relatively low conductive channel of a resistance, device can be reduced
Ratio conducting resistance.
Embodiment 8
As shown in figure 8, a kind of structural representation of the power MOS (Metal Oxide Semiconductor) device integrated with super-junction structure of this example, with reality
The difference for applying example 1 is that the side wall of the first conductive type semiconductor drift region 2 injects the second conductive type semiconductor ion,
Form second conductive type semiconductor layer 11, the conductive type semiconductor of second conductive type semiconductor layer 11 and first drift
Vertically side by side, the first conductive type semiconductor drift region 2 is located at close to Metalized gate side in area 2.N/P in super-junction structure
Bar mutually exhausts the doping concentration that can improve drift region 2, and optimization equipotential lines distribution, raising device is pressure-resistant, reduces than conducting
Resistance.
As shown in figure 9, the power MOS (Metal Oxide Semiconductor) device another kind structural representation integrated with super-junction structure of this example, this
For structure on the basis of embodiment 4, the side wall of the first conductive type semiconductor drift region 2 injects the second conductive type semiconductor
Ion, forms second conductive type semiconductor layer 11, and the second conductive type semiconductor layer 11 is partly led with the first conduction type
Vertically side by side, the first conductive type semiconductor drift region 2 is located at close to Metalized gate side for body drift region 2.Superjunction knot
Structure and grid field plate collective effect, when reversely pressure-resistant, N/P bars, which mutually exhaust, improves the doping concentration of drift region 2, optimization equipotential lines point
Cloth, it is pressure-resistant to improve device；During forward conduction, grid field plate introduces new raceway groove close to media slot side in drift region 2, improves device
Conducting resistance is compared in current capacity, reduction.
Embodiment 9
As shown in Figure 10, the power MOS device construction schematic diagram integrated with dielectric buried layer of this example, with embodiment
1 difference is, between the first conduction type heavily-doped semiconductor drain region 61 and the second conductive type semiconductor substrate layer 1
With the 3rd dielectric layer 12.The present embodiment can realize that complete medium is isolated between low-voltage circuit.
The present invention includes structure cell, drain extension region and media slot terminal with high K dielectric extension grid structure, and multiple
Structure cell arranged in parallel so that device takes into account VDMOS can the advantages of producing high current and LDMOS easy of integration in parallel；Meanwhile
Metalized gate, high K dielectric and drift region form MIS (Metal-Insulator-Semiconductor) structure.In positive guide
When logical, how sub- accumulation layer is produced close to the drift region of high K dielectric side, forms continuous low impedance path, is significantly reduced than conducting
Resistance；Reversely it is pressure-resistant when, high K dielectric assisted depletion drift region, modulate drift region electric field, can improve it is pressure-resistant and reduce than conducting
Resistance.It is particularly suitable for medium-low pressure-resistant low-consumption power electronic applications.
Claims (6)
1. a kind of power MOS (Metal Oxide Semiconductor) device, including the second conductive type semiconductor substrate (1) and served as a contrast positioned at the second conductive type semiconductor
The first conduction type heavily-doped semiconductor drain region (61) of bottom (1) upper surface；The first conduction type heavily-doped semiconductor leakage
Area (61) upper surface both ends have the first conduction type heavily-doped semiconductor drain extension region (62)；First conduction type is heavily doped
There are multiple structure cells in parallel between miscellaneous semiconductor drain extension region (62)；The first conduction type heavily-doped semiconductor leakage
Extension area (62) has media slot (5) between structure cell, and first medium layer is filled with the media slot (5)；The member
Born of the same parents' structure includes grid structure, the first conductive type semiconductor drift region (2) and the second conductive type semiconductor body area (3)；Institute
State the first conductive type semiconductor drift region (2) and the second conductive type semiconductor body area (3) and be located at grid structure both sides；It is described
First conductive type semiconductor drift region (2) is located at the second conductive type semiconductor body area (3) and the first conduction type heavy doping
Between semiconductor drain region (61)；The grid structure is made up of Metalized gate, gate oxide (9) and second dielectric layer (4)；Institute
State gate oxide (9) and be located at Metalized gate both sides and the first conductive type semiconductor drift region (2) and the second conduction type half
Between conductor body area (3)；The second dielectric layer (4) is located at Metalized gate and gate oxide (9) lower surface and the first conduction
Between type heavily-doped semiconductor drain region (61) upper surface, the second dielectric layer (4) is located at the part of Metalized gate bottom
For the high K dielectric with higher dielectric constant, its dielectric constant K is more than the dielectric constant of silica；Described second is conductive
There is the first conduction type heavily-doped semiconductor source region (8) and the second conduction type heavy doping half in type semiconductor body area (3)
Conductor body contact zone (7), in the second conductive type semiconductor body area (3) between the grid structure, the second conduction type weight
Doped semiconductor body contact zone (7) is between the first conduction type heavily-doped semiconductor source region (8)；The grid structure is with being situated between
In the second conductive type semiconductor body area (3) between matter groove (5), the second conduction type heavily-doped semiconductor body contact zone (7)
It is separate with the first conduction type heavily-doped semiconductor source region (8)；The first conduction type heavily-doped semiconductor source region (8)
There is source metal with second conduction type heavily-doped semiconductor body contact zone (7) upper surface, first conduction type is heavily doped
Miscellaneous semiconductor drain extension region (62) upper surface has drain metal；
The first medium layer of filling is to be made up of a variety of media in the media slot (5)；
The dielectric constant of a variety of media of filling prolongs from close to the leakage of the first conduction type heavily-doped semiconductor in the media slot (5)
Stretch area (62) one end gradually increases to one end close to structure cell.
2. a kind of power MOS (Metal Oxide Semiconductor) device according to claim 1, it is characterised in that there is grid gold in the media slot (5)
Belong to, in the second conductive type semiconductor body area (3) between the grid structure and media slot (5), the second conduction type is heavily doped
Miscellaneous semiconductor body contact zone (7) is between the first conduction type heavily-doped semiconductor source region (8).
A kind of 3. power MOS (Metal Oxide Semiconductor) device according to claim 2, it is characterised in that the first conductive type semiconductor drift
The doping concentration of area (2) is moved from close to the side in the first conduction type heavily-doped semiconductor drain region (61) to remote first conductive-type
Successively decrease the side in type heavily-doped semiconductor drain region (61).
A kind of 4. power MOS (Metal Oxide Semiconductor) device according to claim 2, it is characterised in that the first conductive type semiconductor drift
It is higher closer to Metalized gate, its doping concentration to move area (2).
A kind of 5. power MOS (Metal Oxide Semiconductor) device according to claim 2, it is characterised in that the first conductive type semiconductor drift
Moving has the second conductive type semiconductor layer (11) being mutually juxtaposed with it in vertical direction in area (2), between grid structure
The first conductive type semiconductor drift region (2) in, second conductive type semiconductor layer (11), which is located at the first conduction type, partly leads
Between body drift region (2)；In the first conductive type semiconductor drift region (2) between grid structure and media slot (5), second
Conductive type semiconductor layer (11) is connected with media slot (5), the first conductive type semiconductor drift region (2) and grid structure
Connection.
A kind of 6. power MOS (Metal Oxide Semiconductor) device according to claim 2, it is characterised in that the second conductive type semiconductor lining
There is the 3rd dielectric layer (12) between bottom (1) and the first conduction type heavily-doped semiconductor drain region (61).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201510556581.1A CN105070760B (en) | 2015-09-06 | 2015-09-06 | A kind of power MOS (Metal Oxide Semiconductor) device |
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| CN201510556581.1A CN105070760B (en) | 2015-09-06 | 2015-09-06 | A kind of power MOS (Metal Oxide Semiconductor) device |
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| CN107359192A (en) * | 2017-07-28 | 2017-11-17 | 电子科技大学 | A kind of lateral high-voltage device |
| CN108336131B (en) * | 2018-02-26 | 2019-03-08 | 丛艳欣 | Vertical double diffused metal-oxide semi conductor transistor and preparation method thereof |
| CN108550621A (en) * | 2018-04-28 | 2018-09-18 | 重庆大学 | It is a kind of that there is the superjunction silicon carbide VDMOS device for becoming K media slots |
| CN113410299B (en) * | 2020-03-16 | 2023-01-31 | 电子科技大学 | High-voltage-resistance n-channel LDMOS device and preparation method thereof |
| CN111211174B (en) * | 2020-03-20 | 2023-01-31 | 济南安海半导体有限公司 | SGT-MOSFET semiconductor device |
| CN112366230A (en) * | 2020-11-09 | 2021-02-12 | 中芯集成电路制造(绍兴)有限公司 | Power semiconductor device and forming method |
| CN117317023B (en) * | 2023-11-23 | 2024-03-29 | 北京智芯微电子科技有限公司 | Radiation-resistant semiconductor device, process, circuit, chip and electronic equipment |
| CN117650158A (en) * | 2024-01-26 | 2024-03-05 | 湖北九峰山实验室 | Wide bandgap semiconductor trench MOSFET device and manufacturing method thereof |
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