CN102184939A - Semiconductor power device with high-K medium tank - Google Patents
Semiconductor power device with high-K medium tank Download PDFInfo
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Abstract
The invention relates to a semiconductor power device with a high-K medium tank, belonging to the technical field of power semiconductor devices. The device comprises a semiconductor substrate, a semiconductor drift region on the semiconductor substrate, and an active area and a trench gate structure on the semiconductor drift region, wherein the semiconductor drift region comprises a first semiconductor area and a second semiconductor area having the same conduction type; the dosage concentration of the second semiconductor area is higher than that of the first semiconductor area, and the width of the second semiconductor area is smaller than that of the first semiconductor area; a high-K medium tank is arranged below the trench gate structure; two ends of the high-K medium tank are contacted with a conductive material of the trench gate structure and the semiconductor substrate respectively, and two sides of the high-K medium tank are contacted with the second semiconductor area; and the drift region consisting of the first semiconductor area and the second semiconductor area are symmetrically distributed at two sides of the high-K medium tank. The semiconductor power device has the advantages of being high in voltage resistance, small in on resistance, low in power consumption, large in process tolerance, simple in manufacturing process and low in cost and the like, and is suitable for being as the power semiconductor device with low power consumption.
Description
Technical field
The invention belongs to the power semiconductor technical field, particularly the low-power consumption semiconductor power device of grooved MOS control.
Background technology
Power MOSFET is many electronic conductions type device, has input impedance height, frequency height, conducting resistance and has plurality of advantages such as positive temperature coefficient.These advantages make it obtain extensive use in field of power electronics, have improved the efficient of electronic system greatly.
The high pressure resistant drift region that needs of device is low than length and drift region doping content.Yet,, cause the conducting resistance (R of device along with the increase of drift region length and the reduction of doping content
On) increase, the ON state power consumption increases, the break-over of device resistance R
OnThere is following relation with puncture voltage BV: i.e. R
On∝ BV
2.5
Along with the progress of manufacturing process, the conduction resistance that cellular density is increasing, conventional planar gate VDMOS on the silicon chip descends and reached capacity by the restriction of JFET (Junction field effect transistor) effect.Because UMOS (U-type trench MOS, U type groove MOS) has the advantage of no JFET effect and high gully density, along with the progress of technology, it is very little that its conduction resistance can be done.Even but the UMOS structure that adopts, when when high-voltage great-current is used, because the resistance of drift region accounts for the overwhelming majority of device all-in resistance, so the problem of the silicon limit does not still solve.
The U.S. Pat 4754310 of the D.J.Coe application of Philip u s company in 1988 (denomination of invention: High voltage semiconductor device[high-voltage semi-conductor device]) proposes laterally adopting P district alternately and N district as withstand voltage zone in high-voltage MOSFET (LDMOSFET) structure for the first time, with the low-doped drift region of single conduction type (N type or P type) in the replacement conventional power device method as Withstand voltage layer.
At U.S. Pat patent 521627,1993, semiconductor power devices with alternation conductivity type high-voltage breakdown regions[has the semiconductor power device of the high withstand voltage zone of alternating conductivity type], the P post district that replaces and the N post district thought as drift layer is adopted in proposition in vertical power device (especially vertical MOS FET), and is called " compound buffer layer ".
The Withstand voltage layer of super node MOSFET is except along the exhausting of source-drain region direction, also exhaust mutually between P post district and the N post district in the Withstand voltage layer, make that under higher drain voltage, whole Withstand voltage layer just exhausts fully, be similar to an intrinsic Withstand voltage layer, thereby the withstand voltage of device is improved.Simultaneously, the N post district in the super knot can adopt higher concentration, helps reducing conducting resistance like this.
To surpass knot and introduce POWER VD MOS, on the withstand voltage basis of raising, reduce conducting resistance; But in order to obtain high performance hyperconjugation VDMOS, the difficulty that its technology realizes is bigger.Routine " super knot " structure is to adopt repeatedly extension, repeatedly injection and the formation of annealed technology.At first, the VDMOS device withstand voltage is high more, and required longitudinal P post district and N post district are dark more, thereby makes that the number of times of dark P post district and N post district's extension and injection is a lot, technology difficulty is very big, cost is high; Secondly, adopt repeatedly inject, repeatedly extension and annealing form P type and the N type post district that replaces longitudinally, be difficult to form the P type or the N type post district of high concentration and fillet degree, thereby limited the further reduction of break-over of device resistance; Once more, the electric property of " super knot " device is non-equilibrium very sensitive to electric charge, must accurately control the width and the concentration in P post district and N post district on the technology, otherwise cause the device electric property to be degenerated; At last, the body diode reverse of device is recovered hardening etc., and has reliability decrease and because the transverse p/n junction depletion layer enlarges degradation problem under the conducting resistance that causes when big electric current is used.
In U.S. Pat 7,230,31082, (denomination of invention: superjunction voltage sustaining layer with alternating semiconductor and high-K dielectric regions, propose in [having the semiconductor region alternately and the super knot Withstand voltage layer of high K dielectric area], utilize high dielectric constant to improve the thought of device performance.This structure can be avoided conventional super knot p post and the n post problem of counterdiffusion mutually, and enlarges the safety operation area of device, the conducting resistance of reduction device when big electric current.If but the device architecture in the patent is based on extension repeatedly, repeatedly injection technology technology obtains, then technology difficulty is bigger, technology cost height, and very narrow (can not be very little than conducting) can not be done by P post district and N post district, and owing to need independent cutting to form the high dielectric constant filling slot in this patent, this will certainly increase the complexity of technology.
Document (Yoshiyuki Hattori, Takashi Suzuki, Masato Kodama, Eiko Hayashii, and Tsutomu Uesugi, the small inclination of Shallow angle implantation for extended trench gate power MO SFETs with super junction structure[in having the super knot power MOSFET of extension slot grid injects], ISPSD, 2001) propose a kind of small inclination that adopts and injected the groove grid hyperconjugation VDMOS structure that ion forms, reduced the technology cost that forms super knot to a certain extent; And because this technology, P post district or N post district can do very narrowly, are requiring the low-consumption power electronic applications to have good application prospects.But inject the oxide layer of ion penetration groove sidewall in this technology, so need the thickness of accurate controlled oxidation layer, technology difficulty is big, to technology sensitivity relatively, withstand voltage also do not high.
Chinese patent CN 101267000A, (Wang Cailin, extension groove grid super node MOSFET and manufacture method thereof that Sun Jun, oxide fill) and academic dissertation (Sun Jun, [SJ MOSFET specificity analysis and design] 2008) in proposed to have the super knot UMOS of extension groove.This structure has extension slot under the groove grid, fill silicon dioxide in the extension slot, and utilizes the mode of small inclination ion injection to form super-junction structure in the extension slot both sides, and the super-junction structure of extension slot both sides is with respect to the extension slot symmetry.What fill in this extensibility of structure groove is silicon dioxide, though improved the dynamic property of device to a great extent, but the conduction loss of device does not have greatly improved, and the withstand voltage electric charge nonequilibrium effect to super knot drift region of this structure still is very sensitive.
Summary of the invention
The invention provides a kind of semiconductor device with high K media slot, this semiconductor device has withstand voltage height, conducting resistance is little, low in energy consumption, process allowance is big, and manufacturing process is simple, low cost and other advantages.
Technical solution of the present invention is as follows:
A kind of semiconductor power device with high K media slot shown in Fig. 2 a, comprises drift semiconductor district, the active area in the drift semiconductor district and slot grid structure 14 on Semiconductor substrate 1, the Semiconductor substrate.Described active area comprises tagma 5, body contact zone 7 and source region 9, and wherein body contact zone 7 all links to each other with tagma 5 with source metal with source region 9, and tagma 5 links to each other with the drift semiconductor district; Described slot grid structure 14 is positioned at the centre of active area, and the electric conducting material 11 that is surrounded by gate medium 6 and gate medium constitutes, and the electric conducting material 11 of slot grid structure 14 links to each other with gate metal.
Described drift semiconductor district comprises first semiconductor region 2 and second semiconductor region 3 that conduction type is identical, the doping content of described second semiconductor region 3 is higher than first semiconductor region 2, and the width of described second semiconductor region 3 is less than the width of described first semiconductor region; It under described slot grid structure 14 a high K media slot, the promptly inner deep trouth that is filled with high K dielectric material 4, the two ends up and down of high K dielectric material 4 contact with the electric conducting material 11 and the Semiconductor substrate 1 of slot grid structure 14 respectively, the left and right sides of high K dielectric material 4 contacts with second semiconductor region 3, and is distributed in high K media slot 4 bilateral symmetry by the drift region that first semiconductor region 2 and second semiconductor region 3 constitute; The relative dielectric constant of described high K dielectric material is greater than the relative dielectric constant in drift semiconductor district, and its critical breakdown electric field is greater than 30V/ μ m.
In the technique scheme:
Described high K dielectric material 4 can be determined by concrete material, and will take all factors into consideration the character of the material of high K medium.But high K dielectric material 4 should satisfy the relative dielectric constant of dielectric constant greater than the drift semiconductor district, and its critical breakdown electric field should be greater than 30V/ μ m.
The bottom of described slot grid structure and active area bottom flushes or is lower than active area bottom (shown in Fig. 2 b).
Described gate dielectric material 6 is high K dielectric material or silicon dioxide; If gate dielectric material is high K dielectric material, the high K dielectric material that then constitutes gate dielectric material is identical or inequality with the high K dielectric material that constitutes high K media slot.
The semiconductor device that provides of the present invention with high K media slot, if device withstand voltage is higher, can increase one deck low-doped semiconductor Withstand voltage layer 12 identical with drift semiconductor district conduction type between the bottom of drift region and high K media slot and Semiconductor substrate, the doping content of described low-doped semiconductor Withstand voltage layer 12 is less than the doping content of described second semiconductor region 3.This device can reduce technology difficulty because high K media slot etching depth is more shallow, and it is withstand voltage to bear part by semiconductor Withstand voltage layer 12, and this is more suitable in withstand voltage higher application scenario (the withstand voltage 400V of being higher than).
The semiconductor device that provides of the present invention with high K media slot, the longitudinal length of drift region and the longitudinal length of extension groove change, and the withstand voltage of device can in very large range change.But consider the restriction of technology cost and conduction resistance, this structure generally is to have more obvious advantage about 100-300V.
The semiconductor device with high K media slot that provides of the present invention can be the N channel device, also can be P-channel device.The semiconductor device with high K media slot that provides of the present invention is preferably the device of MOS control, as VDMOS device or IGBT device, thereby alleviates contradictory relation between withstand voltage, conducting resistance and the switching loss.
According to an aspect of the present invention, the N raceway groove VDMOS with high K media slot disclosed by the invention has slot grid structure and n
-The n drift region, wherein slot grid structure reduces channel resistance and has reduced JFET (junction field effect transistor) effect, and n drift region concentration is much larger than n
-The concentration of drift region.Therefore, slot grid structure and n
-The n drift region reduces break-over of device resistance greatly.On the other hand, fill high K dielectric material in the groove that this structure has below the groove grid, improved n
-Optimization concentration in the n drift region, this has not only reduced conduction resistance, and avoids the electric charge imbalance problem in the super junction device, and process allowance is very big.
The invention has the beneficial effects as follows: 1) because the present invention has introduced high K dielectric material, make that second semiconductor region, 3 doping contents that contacts with high K media slot in the drift semiconductor district are higher, this helps increasing drift semiconductor district concentration and then reduction conducting resistance; 2) first semiconductor region 2 in drift semiconductor district is identical with the conduction type of second semiconductor region 3 among the present invention, not only avoided the charge balance problem of super junction device, reduced the sensitiveness of device electric property, thereby increased process allowance second semiconductor region, 3 width and doping content; And electric current is except at high concentration second semiconductor region 3, and small amount of current first semiconductor region 2 of flowing through has further reduced resistance; At last, device withstand voltage slightly improves.With respect to the groove grid hyperconjugation VDMOS device of routine, conducting resistance of the present invention reduces about 40%.So in application, can have very low conduction loss; Withstand voltage decline and because the horizontal problem that rises of the conducting resistance that causes of pn knot depletion layer expansion when 3) structure of the present invention has been alleviated big electric current and used.4) second semiconductor region, 3 width are narrower, the lateral dimension and the chip area of the device of having abridged.
Description of drawings
The super knot of the conventional groove grid of Fig. 1 N raceway groove VDMOS structural representation.
Fig. 2 a is groove grid N raceway groove VDMOS structural representation according to an embodiment of the invention.
Fig. 2 b is groove grid N raceway groove VDMOS structural representation in accordance with another embodiment of the present invention.
The groove grid N raceway groove VDMOS structural representation of Fig. 2 c another embodiment according to the present invention.
Fig. 3 is groove grid P raceway groove VDMOS structural representation according to an embodiment of the invention.
Fig. 4 is groove grid N raceway groove IGBT structural representation according to an embodiment of the invention.
The conventional groove grid hyperconjugation VDMOS structure of Fig. 5 and the puncture voltage of semiconductor device of the present invention and the relation of N post district concentration (Nn).
Fig. 6 be conventional groove grid hyperconjugation VDMOS structure with semiconductor device of the present invention in the comparison of high K medium blocking characteristics when the different K values.
Fig. 7 be conventional groove grid hyperconjugation VDMOS structure with semiconductor device of the present invention in the comparison of high K medium forward conduction characteristic when the different K values.
Fig. 8 is the schematic diagram of the manufacture method of semiconductor device of the present invention, and wherein 8a is that small inclination injects schematic diagram, and 8b is the schematic diagram that injects the n post district of back formation, and 8c is a schematic diagram behind the high K medium of filling.
Embodiment
The present invention will be described in detail below in conjunction with accompanying drawing.
Conventional super knot groove grid VDMOS structure, as shown in Figure 1, on Semiconductor substrate 1, be the drift region, this drift region comprise alternately p N-type semiconductor N district 2 ' and n N-type semiconductor N district 3 ', p N-type semiconductor N district 2 ' and n N-type semiconductor N district 3 ' be column, be also referred to as p post district and n post district, p N-type semiconductor N district 2 ' and the super knot of n N-type semiconductor N district 3 ' formation.N N-type semiconductor N district 3 ' be positioned under the slot grid structure 14, n N-type semiconductor N district 3 ' width greater than the width of slot grid structure, slot grid structure comprises the electric conducting material 11 that gate medium 6 and gate medium surround, and draws gate electrode G from electric conducting material 11 surfaces.Preferably, p N-type semiconductor N district 2 ' total impurities (being the product of transverse width and doping content) should equate i.e. charge balance, and should exhaust entirely in blackout conditions with n N-type semiconductor N district 3 ' total impurities.P N-type semiconductor N district 2 ' and n N-type semiconductor N district 3 ' on be active area, comprise P type tagma 5 and at the P on 5 tops, P type tagma
+Semiconductor region 7 (that is body contact zone) and n
+Semiconductor region 9 (that is source region).At part P
+Semiconductor region 7 and n
+Be formed with source electrode S on the semiconductor region 9.At n
+Be formed with drain electrode D on the lower surface of Semiconductor substrate 1.
A kind of semiconductor power device with high K media slot shown in Fig. 2 a, comprises drift semiconductor district, the active area in the drift semiconductor district and slot grid structure 14 on Semiconductor substrate 1, the Semiconductor substrate.Described active area comprises tagma 5, body contact zone 7 and source region 9, and wherein body contact zone 7 all links to each other with tagma 5 with source metal with source region 9, and tagma 5 links to each other with the drift semiconductor district; Described slot grid structure 14 is positioned at the centre of active area, and the electric conducting material 11 that is surrounded by gate medium 6 and gate medium constitutes, and the electric conducting material 11 of slot grid structure 14 links to each other with gate metal.
Described drift semiconductor district comprises first semiconductor region 2 and second semiconductor region 3 that conduction type is identical, the doping content of described second semiconductor region 3 is higher than first semiconductor region 2, and the width of described second semiconductor region 3 is less than the width of described first semiconductor region; It under described slot grid structure 14 a high K media slot, the promptly inner deep trouth that is filled with high K dielectric material 4, the two ends up and down of high K dielectric material 4 contact with the electric conducting material 11 and the Semiconductor substrate 1 of slot grid structure 14 respectively, the left and right sides of high K dielectric material 4 contacts with second semiconductor region 3, and is distributed in high K media slot 4 bilateral symmetry by the drift region that first semiconductor region 2 and second semiconductor region 3 constitute; The relative dielectric constant of described high K dielectric material is greater than the relative dielectric constant in drift semiconductor district, and its critical breakdown electric field is greater than 30V/ μ m.
Be example illustrates semiconductor device of the present invention with reference to Fig. 2 a structure with n raceway groove VDMOS device below.
1 is Semiconductor substrate among Fig. 2 a, is n under the situation of n raceway groove VDMOS
+Semiconductor substrate.Be n from left to right successively on the Semiconductor substrate 1
-N-type semiconductor N district 2, n N-type semiconductor N district 3 and high K dielectric material 4.n
-N-type semiconductor N district 2 and n N-type semiconductor N district 3 constitute the drift region of device.The inner filling of groove that limits by the inner surface in n N-type semiconductor N district 3 by high K dielectric material 4.n
-The both sides of semiconductor region 2 and the high K media slot of n semiconductor region 3 symmetrical distributions.
Be active area on the drift region, comprise the P on P type tagma 5 and 5 tops, P type tagma
+Semiconductor region 7 (that is body contact zone) and n
+Semiconductor region 9 (that is source region).Directly over high K medium 4, be slot grid structure 14, comprise the electric conducting material 11 that gate medium 6 and gate medium surround, draw gate electrode G from electric conducting material 11 surfaces.Preferably, electric conducting material 11 is formed by polysilicon.Gate medium 6 is high K medium or silicon dioxide, and the high K medium and the high K medium in the extension groove that constitute gate medium 6 are identical or different.
N of the present invention
-N-type semiconductor N district 2, n N-type semiconductor N district 3 and/or high K dielectric material 4 preferably are column (therefore, n
-N-type semiconductor N district 2 and n N-type semiconductor N district 3 are also referred to as n
-Post district 2 and n post district 3), and vertical with Semiconductor substrate 1, and this moment, the section shape of high K medium was a rectangle.n
-N-type semiconductor N district 2, n N-type semiconductor N district 3 and/or high K medium 4 also can be other shape, and the section shape of for example described high K medium is trapezoidal or triangle.
The width (direction that is parallel to Semiconductor substrate 1) in n N-type semiconductor N of the present invention district 3 is less than n
-The width in N-type semiconductor N district 2.
The n of high K media slot both sides
-The drift region that N-type semiconductor N district 2 and n N-type semiconductor N district 3 constitute is about high K media slot symmetry.
Preferably, inject by the small inclination ion and form in n N-type semiconductor N of the present invention district 3.The injection of small inclination ion is meant that the direction of ion injection and the normal direction angle of described surfaces of active regions are the 0-30 degree, and preferably this angle is less than 20 degree.
The K value of preferably high K medium is much larger than the K value in drift semiconductor district, and the critical breakdown electric field of preferably high K medium is greater than 30V/ μ m.
The drift semiconductor district can be semiconductor silicon (K=11.9), germanium (K=16), carborundum (K=9.7-10.3) and GaAs semi-conducting materials such as (K=13.1).
Preferably, the height of slot grid structure 14 of the present invention equals active layer thickness, and the height of high K medium 4 equals the height in described drift semiconductor district.Alternatively, slot grid structure 14 surpasses active area downwards, and the height that makes slot grid structure is greater than active area thickness, and the height of high K medium is seen Fig. 2 b less than the height in drift semiconductor district.
Fig. 2 c is the N channel groove grid VDMOS device architecture schematic diagram of another embodiment according to the present invention.The difference of the embodiment of itself and Fig. 2 a is: at n
-Drift region that N-type semiconductor N district 2 and n N-type semiconductor N district 3 constitutes and high K medium 4 material underneath and on Semiconductor substrate 1, have the low-doped semiconductor layer of one deck (that is Withstand voltage layer) 12.Since the existence of low-doped semiconductor layer 12, n
-The height in N-type semiconductor N district 2 and n N-type semiconductor N district 3 can be than among Fig. 2 a little, the further like this manufacturing process of simplifying device.The doping type of low-doped semiconductor layer 12 is identical with the doping type of semiconductor region 3, but doping content is lower than the doping content of semiconductor region 3.
Be the structure that example has illustrated semiconductor device of the present invention with N raceway groove VDMOS above, structure of the present invention is equally applicable to p raceway groove VDMOS.For example, the VDMOS device of Fig. 3 is corresponding with the structure of the VDMOS of Fig. 2 a, and just the n raceway groove VDMOS by Fig. 2 a becomes p raceway groove VDMOS, so the corresponding change of the conduction type of each semiconductor regions, in order to distinguish, add 01 in all label back of Fig. 3 with n raceway groove VDMOS.The structure of Fig. 2 b and Fig. 2 c all can form corresponding p raceway groove VDMOS.
In addition, VDMOS is an example of semiconductor device of the present invention, and semiconductor device of the present invention is applicable to the device of MOS control.For example, semiconductor device of the present invention can also comprise IGBT.Fig. 4 illustrates N raceway groove IGBT according to an embodiment of the invention.Device among device among Fig. 4 and Fig. 2 a different mainly are to use p
+The n that Semiconductor substrate 101 replaces among Fig. 1
+Semiconductor substrate 1.Through the change of Semiconductor substrate, the structure shown in Fig. 2 b and Fig. 2 c also is applicable to IGBT.
The structure of the invention described above is significantly improved the on state characteristic of device, and for example conducting resistance almost reduces by 40%, and the withstand voltage of device increase, and has not had super-junction structure withstand voltage to the nonequilibrium sensitiveness of electric charge, has improved process allowance.
Compare below by the conventional VDMOS structure among the semiconductor device of the present invention among Fig. 2 a and Fig. 1 and to further specify advantage of the present invention:
1. device property analysis
1) conducting resistance
The conducting resistance R of conventional high-pressure trough grid VDMOS structure
On, mainly by drift zone resistance R
D, the accumulation area resistance R
AWith channel resistance R
ChBe in series, i.e. R
On=R
D+ R
A+ R
Ch
The parameter of the channel region of semiconductor device of the present invention can equate with the channel region parameter of the groove grid hyperconjugation VDMOS of routine, so that the channel resistance of two kinds of structures can be thought is equal.
Relating to parameters such as n post district (N raceway groove) width that accumulation area resistance and polysilicon gate covered are P type well region above the n post district in the semiconductor device of the present invention, are high K medium below the polysilicon, so there is not accumulating region, accumulation layer resistance can be ignored.
Drift zone resistance R
DMain relevant by concentration, width, length and the electric current effect of extension of drift region.Because structure proposed by the invention has adopted high K medium that the optimization concentration in n post district 3 is improved, and N
-The drift semiconductor district also can current channel, so cause the conducting resistance of the structure that proposes very little at last.
Therefore the structure of the present invention's proposition has significantly reduced the conducting resistance of forward, reduces device power consumption.
2) puncture voltage
Compare with conventional groove grid hyperconjugation VDMOS, structure of the present invention has modulating action to the body internal electric field, and device withstand voltage is slightly improved, and because the introducing of high K medium makes be not very sensitive to electric charge, improved process allowance, reduced technology difficulty withstand voltage.
Above-mentioned the analysis showed that, the present invention compares with the VDMOS structure of routine, withstand voltage rising to some extent, conducting resistance has descended and has been close to 40%.In addition, it is simple that structure of the present invention also has manufacturing process, to characteristic such as electric charge is insensitive.
2. performance evaluation
Take all factors into consideration each parameter to the influence of device performance and based on consideration, set up the structural model that patent of the present invention proposes according to Fig. 2 a to technology difficulty:
N
-The post sector width is 3 μ m, and concentration is 2 * 10
15Cm
-3, the width in n post district is 0.5 μ m, it is 3.5 * 10 that its corresponding n post district optimizes concentration
16Cm
-3, the width of corresponding extension groove is 5 μ m.Wherein optimize determining of concentration: under this concentration, the withstand voltage and conducting resistance of device reaches best compromise.Based on this model, utilize the medici simulation software that the performance of device is carried out emulation.
1) blocking characteristics
Nn represents the concentration in N post district, V among Fig. 5-7
LeakThe voltage of expression drain electrode, I
LeakThe electric current of expression drain electrode, BV represents puncture voltage.
The puncture voltage of conventional groove grid hyperconjugation VDMOS (see figure 1) and the relation of n post district concentration are shown in the curve in Fig. 5 left side.The relation of VDMOS puncture voltage of the present invention and n post district concentration is shown in the curve on Fig. 5 right side.
Fig. 5 shows, high 1 order of magnitude of groove grid hyperconjugation VDMOS structure of the optimization concentration ratio routine of semiconductor device of the present invention, thereby conducting resistance and conduction loss reduction; And puncture voltage reduces the sensitiveness of change in concentration, thereby process allowance is bigger; Moreover the more conventional hyperconjugation VDMOS of high-breakdown-voltage of semiconductor device of the present invention slightly improves.
As can be seen from Figure 5: (1) conventional groove grid hyperconjugation VDMOS puncture voltage when charge balance reaches maximum.(2) optimal concentration in the structure n post district that proposes for the present invention is greater than n
-The concentration in post district helps reducing conducting resistance.(3) compare with conventional groove grid hyperconjugation VDMOS, the puncture voltage of the structure that the present invention proposes is insensitive to the variation of n post district concentration.
The puncture voltage comparison diagram in the time of different K values of the structure that conventional groove grid hyperconjugation VDMOS and the present invention propose as shown in Figure 6, as seen from the figure, the puncture voltage of the structure that the present invention proposes is insensitive to the variation of K value.
2) forward conduction characteristic
The structure that conventional groove grid hyperconjugation VDMOS and the present invention propose when different K values the forward conduction characteristic more as shown in Figure 7, under given drain current, the structure of the present invention's proposition has very low forward voltage drop, and the K value is big more, conducting resistance is low more.This mainly is because the result of high K medium and super-junction structure combined influence.
Fig. 8 shows by small inclination and injects n N-type semiconductor N district 3 and the high K medium of filling subsequently that forms VDMOS of the present invention (Fig. 2 a is an example with n raceway groove VDMOS).At first form n in substrate, the drift region with common process
-Behind type semiconductor layer and the active area, utilize dry etching, from surfaces of active regions vertically downward etching until the Semiconductor substrate upper surface, to form groove; Utilize mask 13 to adopt small inclination to inject n type impurity, the groove two side is become the n type by the n-type, form the n post district 3 of narrow and high concentration, form the n of symmetry thus in the groove both sides
-Fig. 8 a and Fig. 8 b see in post district 2 and n post district 3; In groove, fill high K medium, make its thickness equal (or less than) n post district and n
-The thickness in post district is seen Fig. 8 c.Form slot grid structure at last and carry out substrate thinning and electrode preparation.Wherein small inclination injects can reference literature (Yoshiyuki Hattori, Takashi Suzuki, Masato Kodama, Eiko Hayashii, and Tsutomu Uesugi, [Shallow angle implantation for extended trench gate power MO SFETs with super junction structure] ISPSD, 2001).
Semiconductor device of the present invention is compared with the groove grid hyperconjugation VDMOS structure of routine, and it is about 40% that conducting resistance has descended, and withstand voltagely slightly rises; Simultaneously, semiconductor device of the present invention has the insensitive superior function of electric charge, and having overcome super junction device the most common also is more scabrous problem, has increased the flexibility ratio of designs and manufacturing; Moreover the technology that forms super knot is simple relatively.What n-post district of the present invention or n post district can do simultaneously is very narrow, makes that conducting resistance and device area are less.The most suitable power device of doing low-power consumption of vertical MOS FET device of the present invention, especially for withstand voltage be the low-consumption power electronic applications of 100-300V.
Claims (9)
1. the semiconductor power device with high K media slot comprises drift semiconductor district, the active area in the drift semiconductor district and slot grid structure (14) on Semiconductor substrate (1), the Semiconductor substrate; Described active area comprises tagma (5), body contact zone (7) and source region (9), and wherein body contact zone (7) link to each other with tagma (5) with source metal respectively with source region (9), and tagma (5) link to each other with the drift semiconductor district; Described slot grid structure (14) is positioned in the middle of the active area, and the electric conducting material (11) that is surrounded by gate medium (6) and gate medium constitutes, and the electric conducting material (11) of slot grid structure (14) links to each other with gate metal;
It is characterized in that:
Described drift semiconductor district comprises first semiconductor region (2) and second semiconductor region (3) that conduction type is identical, the doping content of described second semiconductor region (3) is higher than first semiconductor region (2), and the width of described second semiconductor region (3) is less than the width of described first semiconductor region; It under described slot grid structure (14) a high K media slot, it is the deep trouth that inside is filled with high K dielectric material (4), the two ends up and down of high K dielectric material (4) contact with the electric conducting material (11) and the Semiconductor substrate (1) of slot grid structure (14) respectively, the left and right sides of high K dielectric material (4) contacts with second semiconductor region (3), and the drift region that is made of first semiconductor region (2) and second semiconductor region (3) distributes in high K media slot (4) bilateral symmetry; The relative dielectric constant of described high K dielectric material is greater than the relative dielectric constant in drift semiconductor district, and its critical breakdown electric field is greater than 30V/ μ m.
2. the semiconductor device with high K media slot as claimed in claim 1, it is characterized in that, also have the low-doped semiconductor Withstand voltage layer (12) identical with drift semiconductor district conduction type between the bottom of drift region and high K media slot and Semiconductor substrate (1), the doping content of described low-doped semiconductor Withstand voltage layer (12) is less than the doping content of described second semiconductor region (3).
3. the semiconductor device with high K media slot as claimed in claim 1 or 2 is characterized in that, the bottom of described slot grid structure flushes with the active area bottom or is lower than bottom the active area.
4. the semiconductor device with high K media slot as claimed in claim 1 or 2 is characterized in that, described gate dielectric material (6) is high K dielectric material or silicon dioxide; If gate dielectric material is high K dielectric material, the high K dielectric material that then constitutes gate dielectric material is identical or inequality with the high K dielectric material that constitutes high K media slot.
5. the semiconductor device with high K media slot as claimed in claim 1 or 2, it is characterized in that, second semiconductor region (3) that contacts with high K media slot in the drift semiconductor district utilizes the injection of small inclination ion to pass the preceding etching groove sidewall of the high K dielectric material of filling and forms, or adopts ions diffusion technology to form.
6. the semiconductor device with high K media slot as claimed in claim 1 or 2 is characterized in that, first semiconductor region (2) and second semiconductor region (3) are column structure in the drift semiconductor district, and vertical with Semiconductor substrate (1); Described high K media slot is vertical with Semiconductor substrate (1), and its longitudinal profile shape is rectangle, trapezoidal or triangle.
7. the semiconductor device with high K media slot as claimed in claim 1 or 2 is characterized in that, described semiconductor device with high K media slot is N channel device or P-channel device.
8. the semiconductor device with high K media slot as claimed in claim 8 is characterized in that, described N channel device or P-channel device are the device of MOS control.
9. the semiconductor device with high K media slot as claimed in claim 9 is characterized in that, the device of described MOS control is VDMOS device or IGBT device.
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