CN106960868A - The resistance to nip of semiconductor devices being made up of semiconductor and the insulator containing conductive region - Google Patents
The resistance to nip of semiconductor devices being made up of semiconductor and the insulator containing conductive region Download PDFInfo
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- CN106960868A CN106960868A CN201610013035.8A CN201610013035A CN106960868A CN 106960868 A CN106960868 A CN 106960868A CN 201610013035 A CN201610013035 A CN 201610013035A CN 106960868 A CN106960868 A CN 106960868A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 234
- 239000012212 insulator Substances 0.000 title claims abstract description 42
- 239000004020 conductor Substances 0.000 claims abstract description 47
- 230000001413 cellular effect Effects 0.000 claims abstract description 34
- 238000005516 engineering process Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims description 20
- 239000002184 metal Substances 0.000 claims description 15
- 230000005669 field effect Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 238000012856 packing Methods 0.000 claims description 10
- 239000000126 substance Substances 0.000 claims description 3
- 238000010276 construction Methods 0.000 claims description 2
- 230000000694 effects Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 36
- 238000009413 insulation Methods 0.000 description 18
- 238000000034 method Methods 0.000 description 9
- 239000002245 particle Substances 0.000 description 8
- 230000004888 barrier function Effects 0.000 description 6
- 239000000463 material Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 3
- 239000000084 colloidal system Substances 0.000 description 3
- 229910052906 cristobalite Inorganic materials 0.000 description 3
- 230000004907 flux Effects 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052682 stishovite Inorganic materials 0.000 description 3
- 229910052905 tridymite Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 230000006698 induction Effects 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
Abstract
The invention discloses a kind of semiconductor devices, it is related to technical field of semiconductors.The semiconductor devices contains at least one cellular in two relative main surfaces of device, each cellular has the fisrt feature area of a device in the first main surface, there is the second feature area of a device in the second main surface, there is a resistance to nip between the characteristic area of two devices, resistance to nip includes at least one semiconductor region and (I+C) area, the described existing insulator in (I+C) area has electric conductor again, and there is the face being connected directly to one another in semiconductor region and (I+C) area.This pressure-proof area structure not only using the device of high withstand voltage is manufactured, is also used as the knot marginal technology of high withstand voltage device.
Description
Technical field
The invention belongs to the Withstand voltage layer of technical field of semiconductors, more particularly to high pressure (or power) semiconductor devices.
Background technology
It is well known that in common power device, when off, the high back voltage put on PN junction is born by the lighter and thicker semiconductor layer of a doping to device, hereinafter referred to as Withstand voltage layer.For power device, conducting resistance RonAlso mainly determined by Withstand voltage layer.Pressure-resistant higher, Withstand voltage layer doping is lighter and thickness is thicker, so as to cause the conducting resistance of device increased dramatically.The conducting resistance R of traditional longitudinal power deviceonIt is proportional to the breakdown voltage V of deviceB2.5 power relations.
The Chinese invention patent ZL91101845.X and U.S. patent Nos 5,216,275 of the present inventor solves above mentioned problem.Solution is to improve the pressure-resistant of device while reducing the conducting resistance of device by introducing the semiconductor of two kinds of conduction types in resistance to nip, and the structure is referred to as compound buffer layer or superjunction.Utilize the structure of foregoing invention, the conducting resistance R of device Withstand voltage layeronWith breakdown voltage VBRelation be lowered to 1.3 powers by 2.5 original powers.This is an important breakthrough of traditional Withstand voltage layer relation.
Superjunction devices is pressure-resistant because the N-type and the complementarity principle of P-type semiconductor by Withstand voltage layer are improved to reduce conducting resistance, but the requirement to technique in actually manufacture is higher, it is necessary to strictly control N-type and the dosage of two kinds of semiconductors of p-type.
The content of the invention
The present invention proposes a kind of semiconductor devices, at least containing a cellular in the first main surface (upper space in each figure except for the electrodes) and the second main surface (lowest surface in each figure except for the electrodes) of the semiconductor devices, each cellular is in fisrt feature area (such as p in Fig. 1, Fig. 2 and Fig. 3 for being close to have a device in the first main surface+Area 24, or the M areas 21 in Fig. 7, or p areas 22 and M areas 21 in Fig. 8, or the p areas 57 in Fig. 9 and n+Area 56, or the p in Figure 10-13+Area 29, n+Area 30 and gate insulation area 32), in the second feature area (n in Fig. 1, Fig. 2, Fig. 3 and Fig. 7 for being close to have a device in the second main surface+Area 25, or the n areas 20 in Fig. 8 and n+Area 25, or the n in Figure 10+Area 28 and n areas 45, or the n in Figure 11+Area 28, or the p in Figure 12+Area 36, or the p in Figure 13+Area 36 and n areas 46, or the p in Figure 14+Area 54 and n areas 55, or the n in Figure 16+Area 51)；There is resistance to nip (a n areas 27 and (I+C) area 38 in Figure 1A, Fig. 3, Fig. 7, Fig. 8, Fig. 9, Figure 14, Figure 16 between the fisrt feature area and second feature area of device, or the p areas 37 in Fig. 2A and (I+C) area 38, or the n areas 27 in Fig. 2 B, Fig. 2 C, Figure 11-13 and p areas 37 and (I+C) area 38, or n areas 43 and (I+C) area 38 in Figure 10).Resistance to nip OFF state can high pressure resistant but electric current as low as can be neglected, conducting state have a very low pressure drop but current density can reach it is very big.
Resistance to nip includes at least one semiconductor region (n area 27 in Figure 1A, Fig. 3, Fig. 7, Fig. 8, Fig. 9, Figure 14, Figure 16, or the p areas 37 in Fig. 2A, or the n areas 27 in Fig. 2 B, Fig. 2 C, Figure 11-13 and p areas 37, or the n areas 43 in Figure 10) and (I+C) area, the existing insulator in (I+C) area has electric conductor (each figure Zhong 38 areas) again.
Semiconductor region and (I+C) area are directly connected to.
Semiconductor devices includes at least two electrodes：One electrode is partly or entirely directly connected to the first main surface, and another electrode is partly or entirely directly connected to the second main surface；The two electrodes are located at the outside in region between the first main surface and the second main surface.
Alternatively, referring to Fig. 4 and Fig. 5, semiconductor devices is formed by multiple cellular closs packings.On a section between the fisrt feature area and second feature area of device, the construction of resistance to nip can be interdigital strip structure (referring to Fig. 4 A, Fig. 5 A), or hexgonal structure (referring to Fig. 4 G, Fig. 4 H, Fig. 5 H and Fig. 5 I), or rectangular configuration (referring to Fig. 4 D, Fig. 4 E, Fig. 5 D and Fig. 5 E), or square structure (referring to Fig. 4 B, Fig. 4 C, Fig. 5 B, Fig. 5 C), or inlay square structure (referring to Fig. 4 F, Fig. 5 F and Fig. 5 G).
(I+C) ratio of the cross-sectional area of the cross-sectional area in area 38 and semiconductor region is constant (such as Fig. 1, Fig. 2, Fig. 3) or changed (such as Figure 15 and Figure 16) according to the distance with device fisrt feature area.
Alternatively, referring to Fig. 2 and Fig. 3, semiconductor devices above, semiconductor region in resistance to nip is made up of that (such as the semiconductor region in resistance to nip in Fig. 2A is n-type area 27 semiconductor region of the first conduction type and/or the semiconductor region of second of conduction type, the semiconductor region in resistance to nip in Fig. 2 B is that the semiconductor region in the resistance to nip in p-type area 37, Fig. 2 C is made up of n-type area 27 and p-type area 37).
Alternatively, referring to Fig. 2, Fig. 3 and Fig. 9-11, the second feature area of device is semiconductor region (such as n in Fig. 2, Fig. 3 of the first conduction type+Area 25).
The fisrt feature area of device includes semiconductor region (such as p in Fig. 2, Fig. 3 of second of conduction type being directly connected to the semiconductor region in resistance to nip+Area 24, and the p in Figure 10+Area 29).
The fisrt feature area of device also includes semiconductor region (such as p in Fig. 2, Fig. 3 of second of conduction type+Area 24, and the p areas 57 in Fig. 9) or a conductor region (electrode S conductor in Figure 10 and Figure 11) being directly connected to the insulator region (such as (I+C) area 38 in Fig. 2, Fig. 3 and Fig. 9-11) in resistance to nip.
Alternatively, referring to Figure 13, there is the semiconductor region (p of second of conduction type for being close to the second main surface in the second feature area of device+Area 36), also one semiconductor region (n areas 46) of the first conduction type that is connected with the semiconductor region of second of conduction type, the semiconductor region (n areas 46) of this first conduction type and is connected with resistance to nip (n areas 27, p areas 37 and (I+C) area 38).
Fisrt feature area (gate insulator area 32, the p of device+Area 29, n+Area 30) include the semiconductor region (p of second of conduction type being directly connected to the semiconductor region (n areas 27) of the first conduction type in resistance to nip+Area 29).
The fisrt feature area of device is also comprising the semiconductor region of second of conduction type being connected with the insulator region ((I+C) area 38) in resistance to nip or a conductor region (area 23).
The present invention can be used as its specific embodiment with following devices：
Alternatively, referring to Fig. 7, semiconductor devices is Schottky (Schottky) diode of the contact of a gold-half, and the second feature area of device is the semiconductor region (n of the first conduction type+Area 25).
There is a metal (M areas 21) in the fisrt feature area of device, and the semiconductor region (n areas 27) of metal and the first conduction type in resistance to nip ((I+C) area 38 and n areas 27) is directly connected to.
The fisrt feature area of device and the second feature area of device respectively have conductor to connect two electrodes (being respectively electrode A and electrode K) respectively as Schottky diode.
The fisrt feature area of device is also comprising the semiconductor region of second of conduction type being connected with insulator region in resistance to nip ((I+C) area 38) or a conductor region (M areas 21).
Alternatively, referring to Fig. 8, semiconductor devices is Schottky diode (JBS) rectifier or P-i-N Schottky mixing (MPS) rectifier of a Junction Barrier Controlled, and the second feature area of semiconductor devices is the semiconductor region (n of the first conduction type+Area 25 and n areas 20).
A metal area (M areas 21) is contained in the fisrt feature area of device, and the semiconductor region (n areas 27) of the metal area and the first conduction type in resistance to nip (n areas 27 and (I+C) area 38) is directly connected to.
Semiconductor region (p area 22) of the fisrt feature area of device also containing second of conduction type, it is directly connected to the semiconductor region (n areas 27) and metal area of the first conduction type in resistance to nip.
The fisrt feature area of device and the second feature area of device respectively have conductor to connect two electrodes (anode A and negative electrode K) respectively as JBS rectifiers or MPS rectifiers.
Alternatively, referring to Fig. 9, semiconductor devices is a bipolar transistor (BJT), and the second feature area of device is the semiconductor region (n of the first conduction type+Area 58).
The semiconductor region (n areas 27) of at least one the first conduction type in resistance to nip, constitutes BJT collecting zone.
The semiconductor region (p areas 57) for second of conduction type that the fisrt feature area of device is included, constitutes BJT base.
There is the semiconductor region (n of the first conduction type in the fisrt feature area of device+Area 56), the area removes and surrounded in the part on the first main surface by base, constitutes BJT launch site.
The semiconductor region (n+ areas 58) of the first conduction type in the second feature area of device has conductor to connect as colelctor electrode (electrode C), there is conductor to connect as base stage (electrode B), in launch site (n in base (p areas 57)+Area 56) there is conductor to connect as emitter stage (electrode E).
Alternatively, referring to Figure 10 and Figure 11, semiconductor devices is an isolated-gate field effect transistor (IGFET) (IGFET), and the second feature area of device is the semiconductor region (n of the first conduction type+Area 28), constitute IGFET drain region.
The semiconductor region (the n areas 27 in n areas 43, Figure 11 in Figure 10) of at least one the first conduction type in resistance to nip, constitutes IGFET drift region.
Semiconductor region (the p for second of conduction type that the fisrt feature area of device is included+Area 29), constitute IGFET source substrate zone.
The fisrt feature area of device also includes the semiconductor region (n of the first conduction type+Area 30), the area removes the part on the first main surface by source substrate zone (p+Area 29) surround, constitute IGFET source region.
A part from source region, by a part for source substrate zone until, covered with an insulating barrier (area 32), constituting IGFET gate insulation area on the first main surface untill the semiconductor region of the first conduction type in resistance to nip；
Drain region (n+Area 28) there is conductor to connect as drain electrode (electrode D), in source region (n+Area 30) there are conductor and source substrate zone (p+Area 29) it is connected as source electrode (electrode S), there is conductor to connect as gate electrode (electrode G) in described gate insulation area (area 32).
Alternatively, referring to Figure 12 and Figure 13, semiconductor devices is a gated transistor (IGBT), the semiconductor region (p of second of conduction type in the second feature area of device+Area 36) be IGBT anode region.
Semiconductor region (the p for second of conduction type that the fisrt feature area of device is included+Area 29), constitute the source substrate zone of the IGFET contained by IGBT.
The fisrt feature area of device also includes the semiconductor region (n of the first conduction type+Area 30), the area removes the part on the first main surface by source substrate zone (p+Area 29) surround, constitute the source region for the IGFET that IGBT is included.
A part from source region, by a part for source substrate zone until, covered with a layer insulating (area 32), constituting the grid region of the IGFET contained by IGBT on the semiconductor surface untill the semiconductor region of the first conduction type in resistance to nip.
There is conductor to connect as anode (electrode A) in device anode area, there is conductor to be connected with source substrate zone as negative electrode (electrode K) in the source region, there is conductor to connect as gate electrode (electrode G) on described gate insulation layer.
Alternatively, referring to Figure 14, semiconductor devices is an IGCT, the semiconductor region (p of second of conduction type in the second feature area of device+Area 54) be IGCT anode region.
The semiconductor region (p areas 53) for second of conduction type that the fisrt feature area of device is included, constitutes the grid region of IGCT.
The fisrt feature area of device also includes the semiconductor region (n areas 52) of the first conduction type, and the area removes and surrounded in the part on the first main surface by grid region, constitutes the cathodic region of IGCT.
A part for insulation layer ((I+C) area 38) in the part and resistance to nip in grid region constitutes the gate electrode (electrode G) of IGCT covered with a floor conductor.
In device anode area (p+Area 54) there is conductor to draw as anode (electrode A), there is conductor to draw as negative electrode (electrode K) in cathodic region (n areas 52).
Obviously, the present invention can be applied equally to other high tension apparatus, such as photo thyristor (LCT), gate turn off thyristor (GTO), MOS control IGCTs (MCT), junction field effect transistor (JFET), static induction transistor (SIT), etc..
It should be pointed out that the present invention is also used as the knot terminal technology of a variety of devices.
Alternatively, referring to Figure 16, a cellular in semiconductor devices is located at the edge (edge of structure shown in Fig. 2) of semiconductor devices workspace, is used as the pressure-resistant technology at knot edge；Semiconductor region (the p in Fig. 2 of insulation layer ((I+C) area 38) in semiconductor region (Figure 16 A P areas 50) or a conductor (Figure 16 B electrode A) by second of conduction type, resistance to nip and second of conduction type in device fisrt feature area+Area 24) it is connected.
Alternatively, referring to Fig. 1 C, in resistance to nip, conduction region is strip, and the conduction region of each strip is surrounded by insulation layer, and the distance between strips of conductive area be able to can also be differed with identical.
Alternatively, referring to Fig. 1 D, in resistance to nip, conduction region is rectangle, and each rectangular conductive area is surrounded by insulation layer, and the distance between rectangular conductive area be able to can also be differed with identical.
Alternatively, referring to Fig. 1, (in E, resistance to nip, conduction region is U-shaped, and each U-shaped conduction region is surrounded by insulation layer, and the distance between U-shaped conduction region be able to can also be differed with identical.
Alternatively, referring to Fig. 1 F, in the resistance to nip according to the content of the invention 1, conduction region is granular, and each granular conduction region is surrounded by insulation layer, and the distance between granular conductive area be able to can also be differed with identical.
Of particular note is that, the conduction region (C) in (I+C) area in the present invention, can be metal or the semiconductor of any one conduction type, can also be the semiconductor of two kinds of conduction types, it might even be possible to be their mixture.The insulation layer (I) in (I+C) area in the present invention is not meant to simply a type of insulating materials, and it can be other materials, can be in the optional position of insulation layer.
The breakdown voltage proposed by the present invention that improves reduces the new structure of voltage-sustaining layer of conducting resistance simultaneously.The structure includes a semiconductor region and (I+C) area, and the existing insulator in (I+C) area has electric conductor insulator region again.During in order to make device pressure-resistant, the electrostatic flux of the generation in semiconductor region can introduce some conductors preferably laterally across insulator region in insulator region.So semiconductor region doping concentration can be improved further, so that the structure also reduces conducting resistance while improving pressure-resistant.
Brief description of the drawings
Accompanying drawing described herein is used for providing a further understanding of the present invention, constitutes the part of the application, and schematic description and description of the invention is used to explain the present invention, does not constitute inappropriate limitation of the present invention.In the accompanying drawings：
Figure 1A is the schematic diagram for the diode that insulation layer (I+C) of the resistance to nip by N-type semiconductor area and containing conduction region is constituted.
Figure 1B is conduction region schematic diagram of different shapes in insulation layer.
Fig. 1 C are the resistance to nip that area containing strips of conductive (I+C) area is constituted by N-type semiconductor area and insulation layer.
Fig. 1 D are the resistance to nip that area containing rectangular conductive (I+C) area is constituted by N-type semiconductor area and insulation layer.
Fig. 1 E are that the conduction region in the schematic diagram for the resistance to nip that (I+C) area is constituted with n-type semiconductor, insulator is U-shaped.
Fig. 1 F are that the conduction region in the schematic diagram for the resistance to nip that (I+C) area and n-type semiconductor are constituted, insulator is graininess.
Fig. 2A is the schematic diagram for the resistance to nip that (I+C) area and p-type semiconductor are constituted.
It is p-type semiconductor area around the schematic diagram for the resistance to nip that Fig. 2 B are n-type semiconductors to be constituted with p-type semiconductor and (I+C) area, (I+C) area.
Fig. 2 C are while being p-type semiconductor area, while being n-type semiconductor area around the schematic diagram for the resistance to nip that n-type semiconductor is constituted with p-type semiconductor and (I+C) area, (I+C) area.
Fig. 3 is semiconductor region and the width and the comparison schematic diagram of thickness in (I+C) area in resistance to nip：
Fig. 3 A be (I+C) area with the width in n-type semiconductor area might not be equal situation schematic diagram；
Fig. 3 B are that the thickness in the thickness ratio n-type semiconductor area in (I+C) area is short, and it is not reaching to the n in the second feature area of following device+The schematic diagram of the situation in area 25；
Fig. 3 C are that the thickness in the thickness ratio n-type semiconductor area in (I+C) area is length, and its lower position is less than the lower position in n areas 27, and has reached the n in the second feature area of following device+The schematic diagram of the situation in area 25；
Fig. 3 D are that thickness of the thickness in (I+C) area also than n-type semiconductor area is long, and its upper position has exceeded the upper position in n areas 27.
Fig. 4 is II-II along along Figure 1A ' the various different structure schematic diagrames of resistance to nip that constitute of section (I+C) area and semiconductor region.Each cellular is to be separated with dotted line (except Fig. 4 A imaginary points line is separated)：
Fig. 4 A are interdigital bar figures；
Fig. 4 B are the box-shaped cellular figures of semiconductor region full-mesh；
Fig. 4 C are the box-shaped cellular figures of (I+C) area full-mesh；
Fig. 4 D are the rectangle cellular figures of semiconductor region full-mesh；
Fig. 4 E are the rectangle cellular figures of (I+C) area full-mesh；
Fig. 4 F are to inlay block pattern；
The hexagon closs packing figure of Fig. 4 G semiconductor region full-mesh；
Fig. 4 H are the hexagon closs packing figures of (I+C) area full-mesh.
Fig. 5 is n-type semiconductor area and p-type semiconductor area and the various different structure schematic diagrames of the resistance to nip of (I+C) area composition of the III-III ' sections along along Fig. 2 C：
Fig. 5 A are interdigital bar figures；
Fig. 5 B are the box-shaped cellular figures of n-type semiconductor area full-mesh；
Fig. 5 C are the box-shaped cellular figures of p-type semiconductor area full-mesh；
Fig. 5 D are the rectangle cellular figures of n-type semiconductor area full-mesh；
Fig. 5 E are the rectangle cellular figures of p-type semiconductor area full-mesh；
Fig. 5 F are to inlay one of block pattern；
Fig. 5 G are inlay block pattern two；
Fig. 5 H are the hexagon closs packing figures of n-type area full-mesh；
Fig. 5 I are the hexagon closs packing figures of p-type area full-mesh.
Fig. 6 is that have a thin SiO between semi-conducting material and (I+C) area in the Withstand voltage layer being made up of semi-conducting material and (I+C) area2The schematic diagram of layer.
Fig. 7 is the schematic diagram of the Schottky diodes of the Withstand voltage layer formation constituted using semiconductor with (I+C) area.
Fig. 8 is the schematic diagram of the Schottky rectifiers of the Withstand voltage layer formation constituted using semiconductor with (I+C) area：
Fig. 8 A are the schematic diagrames of the high voltage bearing combination P-i-N Schottky rectifiers of the Withstand voltage layer formation constituted using semiconductor with (I+C) area；
Fig. 8 B are the schematic diagrames of the Schottky rectifiers of the high voltage bearing Junction Barrier Controlled of another Withstand voltage layer formation constituted using semiconductor with (I+C) area.
Fig. 9 is the schematic diagram of the high voltage bearing bipolar transistor of the Withstand voltage layer formation constituted using semiconductor with (I+C) area.
Figure 10 is the high voltage bearing n-VDMIST of the Withstand voltage layer formation constituted using semiconductor and (I+C) area schematic diagram, and n areas are lightly doped again and n by one in its (I+C) area+Drain contact.
Figure 11 is the n-VDMIST of a Withstand voltage layer using Fig. 5 D schematic diagram.
Figure 12 is the IGBT of a Withstand voltage layer using Fig. 5 D schematic diagram.
Figure 13 is the IGBT with cushion of a Withstand voltage layer using Fig. 5 D schematic diagram.
Figure 14 is the schematic diagram of the high voltage bearing IGCT of the Withstand voltage layer formation constituted using semiconductor with (I+C) area.
Figure 15 is a kind of schematic diagram of the VDMIS of the structure of voltage-sustaining layer constituted using semiconductor with (I+C) area manufacturing process：
Figure 15 A are in n+With n epitaxial layers on substrate, and form p+- 29 and n+- 30 and the schematic diagram of insulating barrier 32；
Figure 15 B are the schematic diagrames that depth has been carved on the silicon chip for have epitaxial layer close to the groove of epitaxy layer thickness；
Figure 15 C are the schematic diagrames that (I+C) area is filled with groove；
Figure 15 D are the schematic diagrames to form electrode contact.
Figure 16 is the schematic diagram at the knot edge constituted using semiconductor with (I+C) area：
Figure 16 A are the schematic diagram as an example of the cellular at the most edge of a p-n junction diode with (I+C) area；
Figure 16 B are the schematic diagram as another example of the cellular at the most edge of a p-n junction diode, the schematic diagram that insulator is directly connected in the first main surface and anode A with (I+C) area；
Figure 16 C are to be not necessarily intended to conductor covering on the schematic diagram of another example of the knot terminal technology for utilizing (I+C) area, (I+C) area, and itself covers the schematic diagram of the situation in significant component of p areas.
Embodiment
The various example embodiments of the present invention are described in detail with reference to the accompanying drawings.It should be pointed out that unless stated otherwise, the step of the arrangement and formation of each several part in these embodiments and the setting of described mathematic(al) representation and numerical value is not limit the scope of the invention.Simultaneously, it should be understood that for convenience of description, various parts shown in the accompanying drawings are not necessarily been drawn to scale.
In fact, the description of at least one following exemplary embodiment is intended merely as illustrating rather than being in any way intended to the limitation present invention, and its application or purposes.
Here no longer the technology and method known to related those of ordinary skill are discussed in detail, but belong to the scope of the present invention.
In illustrated herein and all examples for discussing, any concrete numerical value should be construed as illustrative only and nonrestrictive.Therefore, there can be different numerical value in other exemplary embodiments.
Note, similar reference numeral and letter represent similar item in figure below.Therefore, once defined in a figure some, it may not be needed to be further discussed below in following figure.
The present invention proposes a kind of semiconductor devices of the resistance to nip constituted with the insulator region by semiconductor region and containing conduction region.Here the insulator region containing conduction region is named as (I+C) area.
Here it should be mentioned that the conduction region in (I+C) area is not necessarily fairly evenly distributed, and its size, shape and material type be not also restricted.
It should be pointed out that the conductive region (C) in (I+C) area of this patent can be by metal or by any conduction type semiconductor or be made up of both.The metal in (I+C) area in this patent might not comprise only a type of material, and different places can be different types of material in (I+C) area.The insulator region (I) in (I+C) area in this patent might not comprise only a type of insulating materials, can be different materials in the different places of the insulator region.
It shall be mentioned here that, the constituent for the insulator being used in the present invention in resistance to nip is not restricted to a kind of single chemical composition.
Below by using the displaying of example embodiment, the present invention is described more fully referring to the drawings.In the accompanying drawings, identical label represents identical component or element；Thick line represents the conductor of electrode contact in accompanying drawing, and S represents semiconductor region, and (I+C) represents the insulator containing conduction region.On two opposite contact surfaces of the resistance to nip of this method formation, respectively there are the fisrt feature area and second feature area of device.
Figure 1A shows a situation for making diode by resistance to nip with n-type semiconductor area 27 and (I+C) area 38, and wherein p+ areas 24 are the fisrt feature areas of device, and it is connected with anode A.N+ areas 25 are the second feature areas of device, and it is connected with negative electrode K.The shape of conduction region is not restricted by insulator.
Figure 1B shows a situation for making diode by resistance to nip with n-type semiconductor area 27 and (I+C) area 38, wherein gray area of different shapes represents conduction region in the insulator.
Fig. 1 C show a situation for making diode by resistance to nip using n-type semiconductor area 27 and (I+C) area, wherein conduction region in the insulator is strip.
Fig. 1 D show a situation for making diode by resistance to nip using n-type semiconductor area 27 and (I+C) area, wherein conduction region in the insulator is rectangular-shaped.
Fig. 1 E show a situation for making diode by resistance to nip using n-type semiconductor area 27 and (I+C) area, wherein conduction region in the insulator is U-shaped.
Fig. 1 F show a situation for making diode by resistance to nip using n-type semiconductor area 27 and (I+C) area, wherein conduction region in the insulator is graininess.
Obviously, the n-type semiconductor area in Figure 1A could alternatively be p-type semiconductor area, as shown in Figure 2 A.In fig. 2b, in resistance to nip in addition to (I+C) area 38, also containing n-type semiconductor area 27 and p-type semiconductor area 37, wherein (I+C) area 38 is clipped between Liang Ge p-type semiconductors area 37.In fig. 2 c in shown resistance to nip, while being n-type semiconductor area 27 around each insulator region, while being p-type semiconductor area 37.
It should be noted that the insulator containing conduction region is not necessarily intended to have same width and thickness with semiconductor in resistance to nip.The width of n areas 27 and the width in (I+C) area 38 in a and b difference representative graphs 2A in Fig. 3 A.It is equal with b that we are not required for a.The thickness WI in (I+C) area 38 is short than the thickness WS in n-type semiconductor area 27 in resistance to nip shown in Fig. 3 B.The thickness WI in (I+C) area 38 is long than the thickness WS in n-type semiconductor area 27 in Fig. 3 C, and it has reached the second feature area 25 of following device.In Fig. 3 D the thickness WI in (I+C) area 38 also than n-type semiconductor area 27 thickness WS to be long so that its contact surface with the fisrt feature area 24 of device is not at grade.
The arrangement of insulator region and semiconductor region containing conduction region has many structure graphs.Fig. 4 shows (I+C) area 38 of some II-II ' sections along Fig. 2A and the arrangement method of semiconductor region 39.Many cellulars have been marked off by dotted line in figure.These figures include interdigital bar figure (Fig. 4 A), the box-shaped cellular figure (Fig. 4 B) of semiconductor region full-mesh, (I+C) the box-shaped cellular figure (Fig. 4 C) of area's full-mesh, the rectangle cellular figure (Fig. 4 D) of semiconductor region full-mesh, (I+C) the rectangle cellular figure (Fig. 4 E) of area's full-mesh, inlay block pattern (Fig. 4 F), the hexagon closs packing figure (Fig. 4 G) of semiconductor region full-mesh, the hexagon closs packing figure (Fig. 4 H) of (I+C) area full-mesh.Fig. 5 shows the arrangement method in (I+C) area 38 and n-type semiconductor area 27 and p-type semiconductor area 37 of some III-III ' sections along Fig. 2 C.These figures include interdigital bar figure (Fig. 5 A), the box-shaped cellular figure (Fig. 5 B) of the full-mesh of n-type semiconductor area 27, the box-shaped cellular figure (Fig. 5 C) of the full-mesh of p-type semiconductor area 37, the rectangle cellular figure (Fig. 5 D) of the full-mesh of n-type semiconductor area 27, the rectangle cellular figure (Fig. 5 E) of the full-mesh of p areas semiconductor 37, inlay one of block pattern (Fig. 5 F), inlay two (Fig. 5 G) of block pattern, the hexagon closs packing figure (Fig. 5 H) of the full-mesh of n-type semiconductor area 27, the hexagon closs packing figure (Fig. 5 I) of the full-mesh of p-type semiconductor area 37.
Above-mentioned semiconductor is if Si, and it can be by a thin SiO between (I+C) area2Layer 40 is separated, as shown in Figure 6.Shadow region 40 in figure represents SiO2Layer.Although SiO2Dielectric coefficient very little, but as long as SiO2Layer is 40 sufficiently thin, during it and without prejudice to semiconductor region S electric flux line enter in the insulator containing conduction region, or electric flux line enters semiconductor region S from (I+C) area.
If Fig. 2 p+Area 24 is changed to a metal, then be formed a kind of Schottky diodes, as shown in Figure 7.Metal M (27) is the fisrt feature area of device in figure.
The Schottky rectifiers of high voltage bearing Junction Barrier Controlled, or pinch off rectifier (Junction Barrier Controlled Schottky rectifier, JBS, or pinch rectifier) can also be manufactured using this patent.Similarly, high voltage bearing combination P-i-N Schottky rectifiers (Merged P-i-N/Schottky rectifier, MPS rectifier) can also be manufactured.Their structure can use Fig. 8 to represent.
The fisrt feature area of device includes a metal level M, and the p areas 22 being directly connected to M in Fig. 8 A and Fig. 8 B.There is the tie of an electrode A at the top of the fisrt feature area of device.The second feature area of the device of two figure includes n areas 20 and n+Area 25, in n+Area 25 has electrode K associated below.
High voltage bearing bipolar transistor can also be manufactured using the present invention, as shown in Figure 9.Shown here as a npn bipolar transistor, a p base 57 is contained in the fisrt feature area of device, and the core on base contains a n+Launch site 56.There is emitter E to be coupled to n at the top of the fisrt feature area of device+Launch site 56.On base 57, also one base stage B is associated to be connect.The second feature area of the bipolar transistor is n+Area 58, there is that colelctor electrode C is associated to be connect under it.
Figure 10 shows a kind of n-VDMIST constituted using the present invention.Wherein p+Area 29 is its source substrate zone, n+Area 30 is its source region, and insulator region 32 is its gate insulation area.Wherein (I+C) area 38 not with n+Drain region 28 is directly contacted, but passes through a n area 45 more more heavily doped than n area 43 to contact.Due to the presence in this n area 45, VDMIST is in conducting close to n+The resistance in drain region 28 can further reduce.Between drain D and source S plus during backward voltage, also there is a fraction voltage drop in the areas of Tu Zhong 44 and 45th area, but device is pressure-resistant mainly by n areas 43 and (I+C) area 38, and the second feature area of device includes n areas 45 and n here+Drain region 28.
Figure 11 shows to make the schematic diagram of the n-VDMIST of Withstand voltage layer another cellular using Fig. 5 D structures of the present invention.In this cellular, resistance to nip also includes p areas 37.
Figure 12 shows a kind of IGBT constituted using the present invention.Its VDMIST with Figure 11 main distinction is the n in Figure 11 second feature area+Area 28 becomes p now+Area 36.
Figure 13 shows that the one kind constituted using the present invention carries the IGBT of cushion (46th area).Its main distinction with Figure 12 is in the second feature area of device, except there is p+Outside area 36, also have in p+A N-type buffer layer 46 in area 36.Area 23 in this figure can be a p+Area or a conductor.
The insulator containing conductive particle in the Withstand voltage layer of the present invention, does not require that with semiconductor region there is same depth certainly.For example, the foot in (I+C) area 38 in Figure 10 is one and compares n+Slightly higher n areas 45 of area 28, but this insulator can also be deep into n+Inside area 28.
Using the resistance to nip of the invention that also may be utilized in fabricating IGCT certainly, as shown in figure 14, its cellular for containing pnpn layers is shown in the figure in one of example.The fisrt feature area of device includes having negative electrode K associated in p areas 53, and the n areas 52 surrounded by the p areas 53, n areas 52.There are a gate pole G, gate pole G to be connected by conductor with the top of the insulator containing conductive particle in p areas 53.The second feature area of the device of the IGCT includes n areas 55 and p+Area 54.In p+The bottom of area 54 has anode A associated.
It is understood that, the present invention can be additionally used in various other high tension apparatus, for example available for photo thyristor (LCT), gate turn off thyristor (GTO), MOS control IGCTs (MCT), junction field effect transistor (JFET), static induction transistor (SIT), etc., etc..
The method that Figure 15 shows manufacture VDMIST as Figure 10.First, in substrate n+With epitaxial layer n areas 27 in area 28.Secondly, p is made with usual manufacture VDMIS method+Source substrate zone 29 and n+Source region 30, and gate insulation layer 32, as a result as shown in fig. 15.Needs are sheltered not by the place of cutting using mask, the recess between deep trouth, i.e. Figure 15 B two n areas 27 is then carved with the method for chemical attack or the method for plasma etching.Then silicon chip is placed in the vessel of vacuum and evacuated.Covered immediately with the colloid containing conductive particle after evacuation.Due to being vacuum in groove, therefore this kind of colloid can be sucked.After the colloid surface planarizing containing conductive particle, Figure 15 C structure is formed.It is finally by upper and lower two tables surface forming electrode D, S, G, as a result as shown in figure 15d.
The resistance to nip of the present invention can be not only used for the workspaces of various devices, can also as various devices knot marginal technology.Figure 16 A show cellular one example of the insulator containing conductive particle at the most edge of a p-n junction diode.The left side of wherein figure is connected to the workspace of device, and the right is the region containing conductive particle.As long as there is certain width in this region, have above with identical p areas of p areas 50, or have the conductor being connected with p areas 50, as shown in fig 16b, you can be used as the knot edge of the diode.
Figure 16 C show that another is used as the example for tying marginal technology by the use of the insulator of conductive particle.Herein, conductor covering has been not necessarily intended on the insulator 38 containing conductive particle, and itself covers significant component of p areas 50.
Obviously, n-type area all in above-mentioned each example can be exchanged with all p-type areas, turn into a kind of device of films of opposite conductivity after exchange.
For those of ordinary skill in the art, it can also make other many example application under the present invention thought and be no more than claim of the invention.
Therefore, the semiconductor devices in the present invention has been described in detail.In order to prevent the thought for obscuring the present invention, some well-known details are not described herein.Understood in from the description above, those skilled in the art can be understanding of how to realize technical scheme disclosed in this invention.
Although some specific embodiments of the present invention have been presented in the detailed example, it should be noted, however, that for those skilled in the art, above-described embodiment is meant only to illustrate the present invention, rather than limitation the scope of the present invention.Simultaneously for those skilled in the art, above-described embodiment can hold easily modified thought and scope without departing from the present invention.The scope of the present invention is defined by the following claims.
Claims (16)
1. a kind of semiconductor devices, the semiconductor devices includes a first main surface and one
The individual second main surface relative with the first main surface, on the described first main surface and second master
At least containing a cellular in surface, the cellular is being close to have one in the described first main surface
The fisrt feature area of device, in the second feature for being close to have a device in the described second main surface
, there is a resistance to nip between the fisrt feature area and the second feature area of device in area,
It is characterized in that：The resistance to nip includes at least one semiconductor region and (I+C) area, described
There is the face being connected directly to one another between semiconductor region and (I+C) area；(I+C) area is at least
Containing an insulator region and at least containing a conductive region；
At least two electrodes of the semiconductor devices；One electrode is close to the described first main table
The subregion in face or Zone Full；Another electrode is close to the part on the described second main surface
Region or Zone Full；Two electrodes are folded by the described first main surface and the second main surface
Space outside.
2. semiconductor devices according to claim 1, described semiconductor devices is by more
The closs packing formation of individual cellular；In the fisrt feature area and the second feature area of device
Between a section on, the construction of resistance to nip is interdigital strip structure, or hexgonal structure,
Or rectangle structure, or box-shaped structure, or inlay box-shaped structure；
On the section of different distance for leaving the described first main surface, the area in (I+C) area with
The ratio of the area of semiconductor region is constant or change.
3. the semiconductor region in semiconductor devices according to claim 1, the resistance to nip
The semiconductor region of semiconductor region and/or second of conduction type including the first conduction type.
4. semiconductor devices according to claim 1, the second feature area of the device
For the semiconductor region of the first conduction type；
The fisrt feature area of the device directly connects comprising one with the semiconductor region in resistance to nip
The semiconductor region of second of the conduction type connect, or also comprising one and (I+C) area in resistance to nip
The semiconductor region for second of conduction type being connected or a conductor region.
5. semiconductor devices according to claim 1, the second feature area of the device
The semiconductor region for having second of conduction type is close to the described second main surface, also one
The semiconductor region for the first conduction type being connected with the semiconductor region of second of conduction type,
The semiconductor region of the first conduction type is connected with resistance to nip again；
The fisrt feature area of the device includes one and the first conduction type in resistance to nip
The semiconductor region for second of conduction type that semiconductor region is directly connected to, or also comprising one with
The semiconductor region for second of conduction type that (I+C) area is connected or a conductor region in resistance to nip.
6. semiconductor devices according to claim 1, the semiconductor devices is gold-half
The Schottky diode of contact, the second feature area of the device is the first conduction type
Semiconductor region；
The fisrt feature area of the device is metal, and the metal is led with the first in resistance to nip
The semi-conducting material of electric type is directly connected to；
The fisrt feature area of the device and the second feature area of the device respectively have conductor to connect
Respectively as two electrodes of Schottky diode；
The fisrt feature area of the device is also connected comprising one with (I+C) area in resistance to nip
Second of conduction type semiconductor region or a conductor region.
7. semiconductor devices according to claim 1, the semiconductor devices is one
JBS rectifiers or a MPS rectifier, the second feature area of the device be one the first
The semiconductor region of conduction type；
Contain in a metal area, the metal area and resistance to nip in the fisrt feature area of the device
The semiconductor region of the first conduction type be directly connected to；
Semiconductor region of the fisrt feature area of the device also containing second of conduction type, it with
The semiconductor region of the first conduction type in resistance to nip is directly connected to, also with the metal area
It is directly connected to；
The fisrt feature area of the device and the second feature area of the device respectively have conductor to connect
Respectively as JBS rectifiers or two electrodes of a MPS rectifier.
8. semiconductor devices according to claim 4, the semiconductor devices is one
Bipolar transistor, the second feature area of the device is partly leading for the first conduction type
Body area；
At least semiconductor region of the first conduction type in the resistance to nip, constitutes ambipolar crystalline substance
The collecting zone of body pipe；
The semiconductor region for second of conduction type that the fisrt feature area of the device is included, structure
Into the base of bipolar transistor；
There is one in the fisrt feature area of the device except described in addition to semiconductor surface
The semiconductor region for the first conduction type that base is surrounded, constitutes the transmitting of bipolar transistor
Area；
There is conductor in the semiconductor region of the first conduction type in the second feature area of the device
Connect as colelctor electrode, there is conductor to connect as base stage in the base, have in the launch site
Conductor is connected as emitter stage.
9. semiconductor devices according to claim 4, the semiconductor devices is one
Isolated-gate field effect transistor (IGFET), the second feature area of device is the half of the first conduction type
Conductor region, constitutes the drain region of isolated-gate field effect transistor (IGFET)；
At least semiconductor region of the first conduction type in the resistance to nip, constitutes insulated gate field
The drift region of effect transistor；
The semiconductor region for second of conduction type that the fisrt feature area of the device is included, structure
Into the source substrate zone of isolated-gate field effect transistor (IGFET)；
The source region of the isolated-gate field effect transistor (IGFET) is the semiconductor region of the first conduction type,
It is surrounded except in addition to semiconductor surface by source substrate zone；
A part from source region, the part by source substrate zone, until in resistance to nip
Covered with one layer of insulator on semiconductor surface untill the semiconductor region of the first conduction type,
Constitute the grid region of isolated-gate field effect transistor (IGFET)；
There is conductor to connect as drain electrode in the drain region, have conductor and source substrate in the source region
Area is connected as source electrode, has conductor to connect as gate electrode in described grid region.
10. semiconductor devices according to claim 5, the semiconductor devices is one
Insulator gate transistor (IGBT), second of conduction type in the second feature area of device is partly led
Body area is IGBT anode region；
The semiconductor region for second of conduction type that the fisrt feature area of the device is included, structure
Into the source substrate zone of the isolated-gate field effect transistor (IGFET) contained by IGBT；
The source region of isolated-gate field effect transistor (IGFET) contained by the IGBT is the first conduction
The semiconductor region of type, it is surrounded except in addition to semiconductor surface by source substrate zone；
A part from source region, the part by source substrate zone, until in resistance to nip
Covered with one layer of insulator on semiconductor surface untill the semiconductor region of the first conduction type,
Constitute the grid region of the isolated-gate field effect transistor (IGFET) contained by IGBT；
There is conductor to connect as anode in the anode region, have conductor and source substrate in the source region
Area is connected as negative electrode, has conductor to connect as gate electrode in described grid region.
11. semiconductor devices according to claim 5, the semiconductor devices is one
IGCT, the semiconductor region of second of conduction type in the second feature area of device is IGCT
Anode region；
The semiconductor region for second of conduction type that the fisrt feature area of the device is included, structure
Into the grid region of IGCT；
The cathodic region of the IGCT is the semiconductor region of the first conduction type, and it removes and partly led
Surrounded outside body surface face by grid region；
A part from grid region, led covered with a floor on (I+C) area into resistance to nip
Body, constitutes the gate pole of IGCT；
There is conductor to connect as anode in the anode region, there is conductor to connect on the cathodic region
It is used as negative electrode.
12. semiconductor devices according to claim 1, the cellular of the semiconductor devices is
Edge positioned at the workspace of a semiconductor devices, it is described as the pressure-resistant technology at knot edge
(I+C) area in resistance to nip and second of conduction type in the fisrt feature area of device are partly led
Body area is connected by the semiconductor region or a conductor of second of conduction type.
13. in semiconductor devices according to claim 1, the semiconductor devices (I+C)
The conduction region of at least one bar shaped in area.
14. in semiconductor devices according to claim 1, the semiconductor devices (I+C)
The conduction region of at least one rectangle in area.
15. in semiconductor devices according to claim 1, the semiconductor devices (I+C)
The conduction region of at least one U-shaped in area.
16. in semiconductor devices according to claim 1, the semiconductor devices (I+C)
At least one granular conduction region in area.
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