CN204179086U - A kind of semiconductor structure with self-isolation - Google Patents
A kind of semiconductor structure with self-isolation Download PDFInfo
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- CN204179086U CN204179086U CN201420460217.6U CN201420460217U CN204179086U CN 204179086 U CN204179086 U CN 204179086U CN 201420460217 U CN201420460217 U CN 201420460217U CN 204179086 U CN204179086 U CN 204179086U
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- 238000002955 isolation Methods 0.000 title claims abstract description 34
- 239000004065 semiconductor Substances 0.000 title claims abstract description 33
- 238000011049 filling Methods 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 13
- 229920005591 polysilicon Polymers 0.000 claims description 13
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000000034 method Methods 0.000 description 14
- 238000005530 etching Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000001413 cellular effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000011982 device technology Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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Abstract
A kind of semiconductor structure with self-isolation of the utility model, comprises N-type dope semiconductor substrates and N-type doped epitaxial layer; N-type doped epitaxial layer inside is provided with the P type filling well region comprising first, second, and third; First and the 3rd P type fill the upside of well region and be respectively equipped with P type doped region, P type is provided with N-type heavily doped region in doped region; One P type is filled the N-type doped epitaxial layer of well region and correspondence, P type doped region and N-type heavily doped region and is formed the second cell region; The N-type doped epitaxial layer that 2nd P type fills well region and correspondence forms isolation structure region; 3rd P type is filled the N-type doped epitaxial layer of well region and correspondence, P type doped region and N-type heavily doped region and is formed the first cell region; The cell region periphery that first, second cell region and isolation structure region are formed arranges the withstand voltage region of terminal; First cell region and the withstand voltage region of terminal form switching tube; Second cell region is separated with the first cell region by isolation structure region, forms and starts pipe.
Description
Technical field
The utility model semiconductor power device technology field, relates to a kind of high-voltage semiconductor structure, is specially a kind of semiconductor structure with self-isolation.
Background technology
In recent years, along with power device starts to be widely used in field of switch power, the research of people to it is also more and more deep.Smart-power IC (Smart Power IC) is exactly refer to that control chip part and power device integrate.Its core is the self-protection function of power device under chip operation condition, is called smart power device.Meanwhile, in field of switch power, in order to improve the efficiency of power integrated circuit, people begin one's study and to be also integrated in chip by the actuating section of system.In fact, in power management chip, start-up performance is integrated, not only reduces chip idling consumption, and decreases the number of system peripherals components and parts, thus reduces costs.
Traditional smart power device, by high tension apparatus and low voltage control integrated chip, thus realizes start-up performance, but this can bring problem on technique realizes.First, high voltage startup device normally vdmos transistor, needs thick epitaxial layer and terminal structure to provide high withstand voltage, thus increases production cost; Secondly, in order to protecting control chip, the puncture voltage of high voltage startup device always must be greater than the puncture voltage of power switch pipe.If consider technologic fluctuation, this just requires the puncture voltage central value of puncture voltage central value much larger than power switch pipe of smart power device.
In order to address this problem, people also been proposed novel high voltage startup Integrated Solution, integrate by high voltage startup pipe and power switch pipe, then control chip and power chip are carried out twin islet pair and encapsulate; Thus in succession occurred based on LDMOS (lateral double-diffused MOSFET) technique and the smart power chip etc. based on VDMOS (longitudinal bilateral diffusion MOS pipe) technique.But all there is complex structure, increase processing step, the problem that cost is higher
Utility model content
For problems of the prior art, the utility model provides one not increase technology difficulty and cost, can ensure requirement of withstand voltage, realizes the semiconductor structure with self-isolation starting pipe and switching tube isolation.
The utility model is achieved through the following technical solutions:
There is a semiconductor structure for self-isolation, comprise the N-type dope semiconductor substrates and N-type doped epitaxial layer that set gradually from top to bottom; N-type doped epitaxial layer inside is provided with P type and fills well region, and P type is filled well region and comprised and to arrange from inside to outside and well region filled by the identical P type of structure, the 2nd P type is filled well region and the 3rd P type and filled well region; The upside that one P type fills well region and the 3rd P type filling well region is respectively equipped with P type doped region, and P type is provided with N-type heavily doped region in doped region; One P type is filled the N-type doped epitaxial layer of well region and correspondence, P type doped region and N-type heavily doped region and is jointly formed the second cell region; The N-type doped epitaxial layer that 2nd P type fills well region and correspondence forms isolation structure region jointly; 3rd P type is filled the N-type doped epitaxial layer of well region and correspondence, P type doped region and N-type heavily doped region and is jointly formed the first cell region; First cell region, isolation structure region and the second cell region form cell region jointly, and cell region periphery arranges the withstand voltage region of terminal; First cell region and the withstand voltage region of terminal form switching tube; Second cell region is separated with the first cell region by isolation structure region, forms and starts pipe.
Preferably, be provided with oxide layer, dielectric layer and upper metal level above cell region successively, in the dielectric layer in portion of oxide layer, polysilicon is set; The part that upper metal level correspondence is arranged above the first cell region forms the first source metal electrode, the part that upper metal level correspondence is arranged above the second cell region forms the second source metal electrode, mutually disconnects between the first source metal electrode and the second source metal electrode; The lower metal layer be arranged on below N-type dope semiconductor substrates forms drain metal electrode; The part that polysilicon correspondence is arranged above the first cell region forms first grid electrode, and the part that polysilicon correspondence is arranged above the second cell region forms second gate electrode.
Further, oxide layer correspondence is arranged on the 2nd P type and fills well region and at least one P type of being adjacent to fill the part that well region and at least one the 3rd P type fill above well region be field oxide, and the oxide layer of remainder is gate oxide.
Further again, the first source metal electrode is connected to the 3rd P type through dielectric layer and gate oxide correspondence and fills above P type doped region corresponding to well region; Second source metal electrode is connected to a P type through dielectric layer and gate oxide correspondence and fills above P type doped region corresponding to well region.
Further, the partial polysilicon in first grid electrode is arranged on the juncture area of field oxide and gate oxide.
Further, corresponding first cell region of semicon-ductor structure surface is independently provided with the first grid end PAD of electrical connection first grid electrode, and the first source PAD of electrical connection the first source metal electrode; Corresponding second cell region is independently provided with the second gate end PAD of electrical connection second gate electrode, and the second source PAD of electrical connection the second source metal electrode.
Preferably, P type filling well region and N-type doped epitaxial layer are alternately arranged.
Preferably, P type is filled well region and is adopted deep groove etching and silicon backfilling process, is formed after surface planarisation process.
Compared with prior art, the utility model has following useful technique effect:
Semiconductor structure described in the utility model, fill well region by relatively independent the 2nd P type be arranged in N-type doped epitaxial layer and form isolation structure region, the first cell region arrange respectively its outside and inside and the second cell region realize isolation, thus the withstand voltage region of terminal having coordinated cell region periphery to arrange constitutes the injectron and high voltage startup pipe that can realize self-isolation respectively, the isolation achieving both is integrated, not only convenient and control chip carries out compatibility, and reduces chip design cost.And structure is simple, arranges rationally, device fabrication step can not be increased, simple possible.
Further, utilize the corresponding setting in isolation structure region of field oxide, achieve on the one hand being separated of the first cell region and the second cell region, on the other hand the field polycrystalline field plate combined above effectively can improve the surface electric field distribution of isolated area, realizes isolated area and there is identical OFF state blocking ability cellular region.
Further, corresponding grid end PAD and source PAD can be set at the correct position of respective cell region for switching tube and startup pipe, improve the ability of being suitable for.
Accompanying drawing explanation
Fig. 1 is the surface texture vertical view of semiconductor structure described in the utility model.
Fig. 2 is the profile of aa ' position in Fig. 1.
In figure: N-type dope semiconductor substrates 1, N-type doped epitaxial layer 2, well region 31 filled by one P type, well region 32 filled by 2nd P type, well region 33 filled by 3rd P type, P type doped region 4, N-type heavily doped region 5, first grid electrode 6, second gate electrode 7, first source metal electrode 8, second source metal electrode 9, drain metal electrode 10, field oxide 11, dielectric layer 12, gate oxide 13, first cell region A, isolation structure region B, second cell region C, cell region 100, terminal is withstand voltage region 101, first grid end PAD102, first source PAD103, second gate end PAD104, second source PAD105.
Embodiment
Below in conjunction with specific embodiment, the utility model is described in further detail, described in be to explanation of the present utility model instead of restriction.
A kind of semiconductor structure with self-isolation of the utility model, as shown in Figure 2, it comprises the N-type dope semiconductor substrates 1 and N-type doped epitaxial layer 2 that set gradually from top to bottom; N-type doped epitaxial layer 2 inside is provided with P type and fills well region, and P type is filled well region and comprised and to arrange from inside to outside and well region 31 filled by the identical P type of structure, the 2nd P type is filled well region 32 and the 3rd P type and filled well region 33; The upside of the one P type filling well region 31 and the 3rd P type filling well region 33 is respectively equipped with in type doped region, P type doped region 4, P 4 and is provided with N-type heavily doped region 5; One P type fills N-type doped epitaxial layer 2, P type doped region 4 and the N-type heavily doped region 5 common formation second cell region C of well region 31 and correspondence; The N-type doped epitaxial layer 2 that the 2nd described P type fills well region 32 and correspondence forms isolation structure region B jointly; The 3rd described P type fills N-type doped epitaxial layer 2, P type doped region 4 and the N-type heavily doped region 5 common formation first cell region A of well region 33 and correspondence; First cell region A, isolation structure region B and the second cell region C form cell region 100 jointly, and cell region 100 periphery arranges the withstand voltage region 101 of terminal; Be provided with oxide layer, dielectric layer 12 and upper metal level above cell region 100 successively, in the dielectric layer 12 in portion of oxide layer, polysilicon is set; The part that upper metal level correspondence is arranged above the first cell region A forms the first source metal electrode 8, the part that upper metal level correspondence is arranged above the second cell region C forms between the second source metal electrode 9, first source metal electrode 8 and the second source metal electrode 9 and mutually disconnects; The lower metal layer be arranged on below N-type dope semiconductor substrates 1 forms drain metal electrode 10; The part that polysilicon correspondence is arranged above the first cell region A forms first grid electrode 6, and the part that polysilicon correspondence is arranged above the second cell region C forms second gate electrode 7; First cell region A and the withstand voltage region 101 of terminal form switching tube; Second cell region C is separated with the first cell region A by isolation structure region B, forms and starts pipe.
In this preferred embodiment, as shown in Figure 2, oxide layer correspondence is arranged on the 2nd P type and fills well region 32 and at least one P type of being adjacent to fill the part that well region 31 and at least one the 3rd P type fill above well region 33 be field oxide 11, the oxide layer of remainder is gate oxide 13, and this preferred embodiment is arranged on the 2nd P type for oxide layer correspondence and fills well region 32 and a P type being adjacent and fill well region 31 and the 3rd P type and fill part above well region 33 for field oxide 11 and be described; Wherein, the first source metal electrode 8 is connected to above the P type doped region 4 of the 3rd P type filling well region 33 correspondence through dielectric layer 12 and gate oxide 13 correspondence; Second source metal electrode 9 is connected to a P type through dielectric layer 12 and gate oxide 13 correspondence and fills above the P type doped region 4 of well region 31 correspondence; And the partial polysilicon in first grid electrode 6 is arranged on the juncture area of field oxide 11 and gate oxide 13 near the side of the first cell region A.
As shown in Figure 1, the corresponding first cell region A of semicon-ductor structure surface is independently provided with the first grid end PAD102 of electrical connection first grid electrode 6, and the first source PAD103 of electrical connection the first source metal electrode 8; Corresponding second cell region C is independently provided with the second gate end PAD104 of electrical connection second gate electrode 7, and the second source PAD105 of electrical connection the second source metal electrode 9.As shown in Figure 2, P type filling well region and N-type doped epitaxial layer 2 are alternately arranged; And conducting resistance that width ratio between well region and N-type doped epitaxial layer 2 and concentration ratio should meet by described semiconductor structure filled by P type and requirement of withstand voltage determines jointly.P type is filled well region and is adopted deep groove etching and silicon backfilling process, is formed after surface planarisation process; P type is filled the degree of depth of well region, depth-to-width ratio and backfill doping content and is determined by designing requirement of withstand voltage.
The utility model is under the prerequisite not increasing technology difficulty and cost, can protect between injectron and high voltage startup pipe while insulation request, extra industrial manufacturing process can not be increased, can not requirement of withstand voltage be ensured, improve the scope of application, reduce the design cost of respective chip.
The utility model is adopted and is prepared with the following method:
1) one piece of N-type high-concentration dopant silicon chip is got as N-type dope semiconductor substrates 1, epitaxial growth N-type epitaxy layer 2;
2) adopt deep groove etching and silicon backfilling process, form the P type comprising a P type filling well region 31, the 2nd P type filling well region 32 and the 2nd P type filling well region 33 after surface planarisation process and fill well region;
3) adopt ion implantation and follow-up annealing process to form P type doped region 4, realize isolating the first cell region A and the second cell region C by isolation structure region B;
4) then field oxide and gate oxide is generated through overheated growth, then then depositing polysilicon on gate oxide, and carry out etching formation first grid electrode 6 and second gate electrode 7, then form N-type heavily doped region 5 through ion implantation, realize the contact area of N-type heavily doped region 5 and electrode;
5) through deposit aluminium and etching aluminium technique, form the first source metal electrode 8, second source metal electrode 9 as the source electrode of semiconductor structure by upper metal level, form the drain electrode of drain metal electrode 10 as semiconductor structure by lower metal layer; Finally carry out Passivation Treatment, thinning back side and back face metalization process.
Claims (7)
1. there is a semiconductor structure for self-isolation, it is characterized in that, comprise the N-type dope semiconductor substrates (1) and N-type doped epitaxial layer (2) that set gradually from top to bottom; N-type doped epitaxial layer (2) inside be provided with P type fill well region, P type fill well region comprise from inside to outside arrange and structure identical the one P type fill well region (31), the 2nd P type fill well region (32) and the 3rd P type filling well region (33); The upside that one P type fills well region (31) and the 3rd P type filling well region (33) is respectively equipped with P type doped region (4), is provided with N-type heavily doped region (5) in P type doped region (4);
Described P type filling well region (31) and the N-type doped epitaxial layer (2) of correspondence, P type doped region (4) and N-type heavily doped region (5) formation the second cell region (C) jointly; The N-type doped epitaxial layer (2) that the 2nd described P type fills well region (32) and correspondence forms isolation structure region (B) jointly; The 3rd described P type filling well region (33) and the N-type doped epitaxial layer (2) of correspondence, P type doped region (4) and N-type heavily doped region (5) formation the first cell region (A) jointly; First cell region (A), isolation structure region (B) and the second cell region (C) form cell region (100) jointly, and cell region (100) periphery arranges the withstand voltage region of terminal (101);
First cell region (A) and the withstand voltage region of terminal (101) form switching tube; Second cell region (C) is separated with the first cell region (A) by isolation structure region (B), forms and starts pipe.
2. a kind of semiconductor structure with self-isolation according to claim 1, it is characterized in that, described cell region (100) top is provided with oxide layer, dielectric layer (12) and upper metal level successively, arranges polysilicon in the dielectric layer (12) in portion of oxide layer; The corresponding part arranged in the first cell region (A) top of upper metal level forms the first source metal electrode (8), the corresponding part arranged in the second cell region (C) top of upper metal level forms the second source metal electrode (9), mutually disconnects between the first source metal electrode (8) and the second source metal electrode (9); The lower metal layer being arranged on N-type dope semiconductor substrates (1) below forms drain metal electrode (10); The corresponding part arranged in the first cell region (A) top of polysilicon forms first grid electrode (6), and the corresponding part arranged in the second cell region (C) top of polysilicon forms second gate electrode (7).
3. a kind of semiconductor structure with self-isolation according to claim 2, it is characterized in that, the part that oxide layer correspondence is arranged on the 2nd P type filling well region (32) and at least one P type filling well region (31) be adjacent and at least one the 3rd P type filling well region (33) top is field oxide (11), and the oxide layer of remainder is gate oxide (13).
4. a kind of semiconductor structure with self-isolation according to claim 3, it is characterized in that, the first source metal electrode (8) is connected to the 3rd P type through dielectric layer (12) and gate oxide (13) correspondence and fills top, P type doped region (4) corresponding to well region (33); Second source metal electrode (9) is connected to a P type through dielectric layer (12) and gate oxide (13) correspondence and fills top, P type doped region (4) corresponding to well region (31).
5. a kind of semiconductor structure with self-isolation according to claim 2, is characterized in that, the partial polysilicon in first grid electrode (6) is arranged on the juncture area of field oxide (11) and gate oxide (13).
6. a kind of semiconductor structure with self-isolation according to claim 2, it is characterized in that, corresponding first cell region (A) of described semicon-ductor structure surface is independently provided with the first grid end PAD (102) of electrical connection first grid electrode (6), and the first source PAD (103) of electrical connection the first source metal electrode (8); Corresponding second cell region (C) is independently provided with the second gate end PAD (104) of electrical connection second gate electrode (7), and the second source PAD (105) of electrical connection the second source metal electrode (9).
7. a kind of semiconductor structure with self-isolation according to claim 1, is characterized in that, well region filled by P type and N-type doped epitaxial layer (2) is alternately arranged.
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| CN201420460217.6U CN204179086U (en) | 2014-08-14 | 2014-08-14 | A kind of semiconductor structure with self-isolation |
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| CN201420460217.6U CN204179086U (en) | 2014-08-14 | 2014-08-14 | A kind of semiconductor structure with self-isolation |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157689A (en) * | 2014-08-14 | 2014-11-19 | 西安芯派电子科技有限公司 | Semiconductor structure with self-isolation |
| CN106960868A (en) * | 2016-01-11 | 2017-07-18 | 电子科技大学 | The resistance to nip of semiconductor devices being made up of semiconductor and the insulator containing conductive region |
-
2014
- 2014-08-14 CN CN201420460217.6U patent/CN204179086U/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104157689A (en) * | 2014-08-14 | 2014-11-19 | 西安芯派电子科技有限公司 | Semiconductor structure with self-isolation |
| CN106960868A (en) * | 2016-01-11 | 2017-07-18 | 电子科技大学 | The resistance to nip of semiconductor devices being made up of semiconductor and the insulator containing conductive region |
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Denomination of utility model: Semiconductor structure with self-isolation Effective date of registration: 20160817 Granted publication date: 20150225 Pledgee: Xi'an Hi-tech Emerging Industry Investment Fund Partnership (L.P.) Pledgor: XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: 2016610000034 |
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Date of cancellation: 20200820 Granted publication date: 20150225 Pledgee: Xi'an Hi-tech Emerging Industry Investment Fund Partnership (L.P.) Pledgor: XI'AN SEMIPOWER ELECTRONIC TECHNOLOGY Co.,Ltd. Registration number: 2016610000034 |
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