JPH1126780A - Semiconductor device including p-n junction - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device including p-n junction which has a high withstand voltage and suited for fine structures. SOLUTION: A semiconductor device comprises a p-n junction composed of a p-type semiconductor region 50 and an n-type semiconductor region 60. At least either of the regions 50, 60 has an insulation region formed so that at least a part thereof exists in a depletion layer 70 defined by the p-n junction when a reverse bias is applied. This semiconductor device allows the depletion layer at the p-n junction to be wider than that of a structure including no insulation region, thus obtaining a high withstand voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a pn junction and having a high breakdown voltage.

[0002]

2. Description of the Related Art Hitherto, high-voltage diodes have been widely used in peripheral circuits including semiconductor devices, for example, as protection diodes for protecting the semiconductor device from a voltage source. Similarly, the diode is required to have a higher breakdown voltage.

FIG. 10 shows an epitaxial rectifier diode as one of conventional examples of a pn junction diode. This pn junction diode 1 has an n-type silicon substrate 6
An n ⁻ -type epitaxy region 68 is formed on 6, and a p-type impurity is diffused into the epitaxial region 68 to form a p-type region 50. On the back surface of the silicon substrate 66, an n ⁺ -type diffusion region 64 in which, for example, gold is diffused is formed. Thus, the n-type region 60 is constituted by the silicon substrate 66, the diffusion region 64 and the epitaxial region 68. The p-type region 5
The anode electrode 52 is formed on the surface of the diffusion region 6.
The cathode electrode 62 is formed on the surface of the fourth electrode 4.

Such a pn junction diode is in a reverse bias state, that is, a state in which the anode electrode 52 is in a floating state or a state in which a negative voltage is applied to the electrode 52, and a state in which a positive voltage is applied to the cathode electrode 62. In this case, no current flows between the anode electrode 52 and the cathode electrode 62, and the transistor is turned off. On the other hand, this pn junction diode is in a positive bias state,
When a positive voltage is applied to the cathode electrode 62 and a negative voltage is applied to the cathode electrode 62, the anode electrode 52 and the cathode electrode 6
A current flows between the two, and the device is turned on.

The on / off control of such a pn junction diode is performed as follows.

That is, first, in the off state, that is, in the reverse bias state, by applying a negative voltage to the anode electrode 52, holes serving as majority carriers in the p-type region 50 are attracted to the anode electrode 52. Similarly, when a positive voltage is applied to the cathode electrode 62, electrons that are majority carriers in the n-type region 60 are attracted to the cathode electrode 62. That is, in the reverse bias state, the width of the depletion layer 2 is larger than the width of the depletion layer formed when no voltage is applied because majority carriers near the pn junction are attracted to the electrodes 52 and 62, respectively. The electrodes 52, 6
2 increases in proportion to the voltage applied to 2.

In this state, the majority carriers are attracted to each electrode, and almost no carriers pass through the depletion layer 2, so that almost no current flows. The slightly flowing current is due to minority carriers present inside the p-type and n-type regions. The current caused by the minority carriers gradually increases with an increase in the voltage applied to each of the electrodes 52 and 62. At a certain voltage or higher, a breakdown current flows. The voltage immediately before this breakdown current starts to flow is
It is physically determined by the impurity concentration and the impurity diffusion depth of each pn region forming the pn junction diode.

In the on state, that is, in the forward bias state, the anode electrode 52 of the pn junction diode 1
By applying a positive voltage to the cathode electrode 62 and a negative voltage to the cathode electrode 62, holes in the p-type region 50 are
Then, the electrons in the n-type region 60 flow to the anode electrode 52, and the carriers pass through the depletion layer 2 so that the current flows.

As described above, the ON / OFF state of the pn junction diode can be controlled by the voltage applied to the electrodes 52 and 62.

When a pn junction diode is used in, for example, a clamp circuit, the withstand voltage between the anode and cathode electrodes in the off state (reverse bias state) (hereinafter referred to as "off withstand voltage") is an extremely important factor. Become. For this reason, in a general pn junction diode, in order to secure a high off-state breakdown voltage, a method of forming a pn junction diode using a deep impurity diffusion layer, or a method of forming a breakdown voltage holding region formed of a thick epitaxial layer, or the like is known. It is used. However, these methods can be used when the pn junction diode and other devices are formed on the same wafer.
Not only is it difficult to use the same process, but also there is a problem that a long processing time is required for forming a deep impurity diffusion region and forming a thick epitaxial layer, and the cost is increased.

As a method for solving such a problem, a bevel structure shown in FIG. 11 may be employed. In this bevel structure, the cross-sectional area near the junction surface where the electric field is strongest is formed larger than the neutral region 56 of the p-type region 50. Specifically, in the bevel structure, the side surface is formed obliquely so that the cross-sectional area of the substrate of the pn junction diode increases from the p-type region 50 to the n-type region 60.
In such a structure, the p-type region has a relatively smaller cross-sectional area near the pn junction than the n-type region, so that the end of the depletion layer 3 in the p-type region is tried to satisfy the charge neutrality condition. Is spread to the neutral layer 56 side, and the angle of the edge portion of the depletion layer becomes gentle, so that the electric field concentration can be reduced, and as a result, the off breakdown voltage is improved.

However, in such a bevel structure, pn
After forming the junction, a step of obliquely polishing the element is required, and the element before polishing must be manufactured with a large area in advance to secure the element area required for assembly such as wire bonding There are several issues, such as:

[0013]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a high breakdown voltage and a pn junction structure suitable for miniaturization.

[0014]

According to the present invention, there is provided a semiconductor device including a pn junction in which a p-type region made of a p-type semiconductor and an n-type region made of an n-type semiconductor are joined. An insulating region is formed in at least one of the mold region and the n-type region, and the insulating region is formed in a state where at least a part thereof exists inside a depletion layer formed by a pn junction when reverse bias is applied. It is characterized by having been done.

According to this semiconductor device, the width of the depletion layer at the pn junction can be formed wider than that of the structure not including the insulating region, and a high breakdown voltage can be obtained. The following are conceivable reasons for obtaining such an effect.

The width of the depletion layer formed in the pn junction region is
It is determined by the impurity concentration of each pn region, the impurity diffusion depth, and the like. In the semiconductor device of the present invention, an insulating region is formed in at least one of the p-type region and the n-type region, and at least a part of the insulating region is formed inside a depletion layer formed when a reverse bias is applied. By being formed in an existing state, carriers are physically removed in a region where a depletion layer can be formed. Therefore, in order to satisfy the charge neutrality condition, the width of the depletion layer in the region where the insulating region is formed is larger than that in a case where the insulating region is not formed. This means that the total width of the depletion layer increases, and this expansion improves the breakdown voltage of the element.

FIG. 1 shows a semiconductor device to which the present invention is applied.
For example, a mode of an insulating region in a pn junction diode is schematically illustrated.

A pn junction diode 10 shown in FIG.
At 0, the p-type region 50 and the n-type region 60 are joined, and the insulating region 40a is formed in the p-type region 50.
An anode 52 is formed in the p-type region 50, and a cathode 62 is formed in the n-type region 60. At least a part of the insulating region 40a is in a depletion layer that satisfies a specific condition, that is, when it is assumed that an insulating region is not formed, and in a depletion layer formed in a reverse bias state. Is formed.

The insulating region 40a is, for example, a p-type region 50
The trench can be formed by embedding an insulating layer in the trench. When such a trench structure is adopted, a so-called trench isolation technique can be used.

The pn junction diode 10 shown in FIG.
0, by providing the insulating region 40a in the p-type region 50, the p-type region 5
Carrier (hole) in a region where a depletion layer can be formed in 0
Is physically removed. Therefore, in order to satisfy the charge neutrality condition, the depletion layer in the p-type region 50 is outward, that is, the state shown by a chain line in the figure (the end 72 of the depletion layer when the insulating region 40a is not formed). To the state shown by the solid line (the end 74 of the depletion layer when the insulating region 40a is formed). Therefore, the width of the depletion layer 70 is wider than that without the insulating region, and
The off breakdown voltage of the element is improved.

FIG. 1B shows an example of a pn junction diode 200 in which an insulating region 40 b is formed in an n-type region 60. In the pn junction diode 200, by providing the insulating region 40b in the n-type region 60, carriers (electrons) in a region where a depletion layer can be formed in the n-type region 60 in a reverse bias state are physically removed. It will be in a state where it was lost. Therefore, in order to satisfy the charge neutrality condition, the depletion layer in the n-type region 60 is directed outward, that is,
In the figure, the state is enlarged from the state shown by the chain line to the state shown by the solid line. Therefore, the width of the depletion layer 70 is increased as compared with the case where there is no insulating region, and the off breakdown voltage of the element is improved.

FIG. 1C shows that the insulating region 40a and the insulating region 40b are formed by the p-type region 50 and the n-type region 6 respectively.
5 shows an example of a pn junction diode 300 formed at zero. Also in this pn junction diode 300, FIG.
The pn junction diode 100 shown in (A) and (B),
For the same reason as 200, the width of the depletion layer 70 can be increased, and the off breakdown voltage is improved.

Further, in the semiconductor device according to the present invention, when a trench structure as shown in FIGS. 1A to 1C is employed, in order to prevent an electric field from being concentrated on a corner at the bottom of the trench, The inside of the trench was buried with an insulator. Thus, even when a voltage is applied to the element, an electric field is uniformly applied to the insulator inside the trench as well as inside the semiconductor.

The number of insulating regions formed in the semiconductor device of the present invention is not limited to one, but may be plural. Further, the insulator that forms the insulating region is not limited to an oxide such as silicon oxide, and various insulators such as a nitride can be used. Further, the insulating region may have a structure embedded in a semiconductor.
In this case, for example, after forming a trench from the surface of the semiconductor substrate, filling the trench with an insulating layer, further forming a semiconductor layer from above in a state of covering the insulating layer,
A method of burying the insulating region can be adopted.

The semiconductor device of the present invention can be applied to any semiconductor element having a pn junction, and can be applied not only to a pn junction diode but also to a transistor. For example, when this structure is formed in the base region of a bipolar transistor, a depletion layer between the base and the collector, which is generated when a voltage is applied to the collector region, is formed wider than a structure having no insulating region. In addition, the semiconductor device of the present invention can operate in a bipolar mode element, that is, in a base (channel, gate) region of an IGBT, thyristor, SIT device, IEGT, or the like, or a collector (drain) region of an epitaxial layer, or a power MOS. A similar effect can be obtained by applying the present invention to a body region or a drain region of a UMOS device or the like. Further, the semiconductor device of the present invention can be applied not only to a device that allows a current to flow vertically but also to a device of a horizontal type, such as an SOI structure.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) FIG. 2 schematically shows the basic structure of a pn junction diode according to the present invention. In this embodiment, a pn junction diode 1000 is used.
Is used, for example, as a rectifier diode, and a p-type region is formed in an n-type silicon substrate. Specifically, n
The mold region 60 includes an n-type silicon substrate 66 and an n ⁻ -type epitaxy region 68 formed on one surface of the silicon substrate 66, and a conductive material such as gold is formed on the other surface of the silicon substrate 66. An n ⁺ type diffusion region 64 formed by diffusion is formed. Then, the p-type region 50
Is formed by diffusing a p-type impurity into the epitaxial region 68. In the p-type region 50, an insulating layer 40 extending in the thickness direction of the silicon substrate 66 is formed. This insulating layer 40 is formed in a state where at least a part (lower end) thereof exists in the depletion layer 70 formed when a reverse bias voltage is applied to the pn junction diode 1000. Further, an anode electrode 52 is formed on the surface of the p-type region 50, and the anode electrode 52 is separated by an insulating layer 54 made of silicon oxide. Further, a cathode electrode 62 is formed on the surface of the n ⁺ type diffusion region 64.

In the pn junction diode 1000, at least in the off state (reverse bias state), as described above, the carrier in the insulating layer 40, that is, the holes are removed, and the insulating layer is formed. As compared with the case where there is no pn region, there is a difference in the total amount of impurities in each pn region. Therefore, in order to satisfy the charge neutrality condition, the depletion layer 70a in the p-type region 50 expands, and as a result, the entire width of the depletion layer 70 (p-side depletion layer 70a and n-side depletion layer 70b) increases. As a result, the off-breakdown voltage of the element is improved by the extent that the width of the depletion layer is increased.

Next, the results of a breakdown voltage measurement (simulation) performed to confirm that the off breakdown voltage is improved will be described. In performing the simulation, the sample conditions of the pn junction diode according to the present invention were set as follows.

N-type silicon substrate 66; thickness 20 μm, impurity concentration 1 × 10 ¹⁶ cm ⁻³ n ⁺ type diffusion region 64; thickness 15 μm, impurity concentration 1 × 1
0 ¹⁸ cm ⁻³ n ^- type epitaxy region 68; thickness 8 μm, impurity concentration 1 × 10 ¹⁵ cm ⁻³ p-type region 50; thickness 2.5 μm, impurity surface concentration 1 ×
10 ¹⁷ cm ^-3 insulating layer; width 1 μm, depth 2 μm Similarly, measurement of the withstand voltage of a pn junction diode having a conventional structure shown in FIG. Was done. FIG. 3 shows the results together. In FIG. 3, a curve indicated by a symbol a is a measurement result of the device according to the present embodiment, and a curve b
The curve shown by is the measurement result of the device having the conventional structure shown in FIG.

From FIG. 3, it has been confirmed that the formation of the insulating layer 40 in the p-type region 50 makes it possible to increase the off-breakdown voltage by at least about 10% as compared with the element having the conventional structure.

As described above, according to the present embodiment, the element area can be increased without increasing the film thickness of n ⁻ -type epitaxy region 68 for increasing the off-breakdown voltage as compared with the element having the conventional structure. Without this, the off breakdown voltage can be increased. Further, since the insulating layer 40 can be formed by a commonly used trench isolation technique, it can be formed simultaneously with other devices on the same wafer, and the process can be compared with the conventional bevel structure. It is advantageous.

In the pn junction diode 1000 shown in FIG. 2, an example in which the insulating layer 40 is provided in the p-type region 50 has been described. However, the present invention is not limited to this, and the insulating layer 40 may be formed in the n-type region 60. Alternatively, it may be provided in both the p-type region 50 and the n-type region 60.

Further, the present invention is not limited to the pn junction diode according to the above embodiment, but can be applied to any pn junction diode, and of course, to an element having no epitaxial region for increasing off-breakdown voltage.

(Second Embodiment) FIG. 4 schematically shows a basic structure of a main part of an electrostatic induction transistor (SIT) according to the present invention. In the SIT 2000A according to the present embodiment, an n ⁻ -type epitaxy region 82 is formed on the surface of an n ⁺ -type silicon substrate 80. In the n ⁻ -type epitaxy region 82, a p ⁻ -type channel region 84 formed by diffusing a p-type impurity is formed, and a p ⁺ -type gate region 86 is formed continuously from the channel region 84. . Further, an n ⁺ -type source region 88 formed by diffusing an n-type impurity is formed in the channel region 84. Then, the channel region 84
The insulating layer 4 is located at a position separated from the source region 88.
0 is formed. The insulating layer 40 includes at least
At the time of reverse bias, it is formed so as to be included in a depletion layer (not shown) formed at a junction region between p ⁻ type channel region 84 and n ⁻ type epitaxial region 82.

In the SIT2000A, at least in the reverse bias state, as described above, the insulating layer 40
The carrier of the portion, that is, the hole is removed, and the p carrier is compared with the case where the insulating layer is not formed.
A difference occurs in the total amount of impurities in each of the n regions. Therefore, in order to satisfy the charge neutrality condition, the width of the depletion layer in the p ⁻ type channel region 84 is increased, and as a result, the breakdown voltage between the source region and the drain region is improved.

Further, by using the structure of the present invention not only in the above-described channel region but also in a portion where a depletion layer of a pn junction region such as an epitaxial region, a gate region, and a source region is formed, the depletion of the pn junction region is achieved. The width of the layer can be widened, and the breakdown voltage determined by the width of these depletion layers can be improved.

(Third Embodiment) FIG. 5 schematically shows the structure of the main part of another SIT according to the present invention.
The SIT2000B according to the present embodiment is the same as the second
Having the same structure as the SIT2000A according to the second embodiment, except that the insulating layer 40 is formed not in the channel region 84 but in the n ⁺ -type silicon substrate 80 and the n ⁻ -type epitaxial region 82. This is different from the embodiment.

[0038] That is, SIT2000B is on the surface of the n ⁺ -type silicon substrate 80, n ^- -type Epitakyaru region 82
There is formed, n ^- type in Epitakyaru region 82 p ^- -type channel region 84 is formed, p ⁺ -type gate region 86 in succession in the channel region 84 is formed, further, the channel region 84 is n ⁺ -type A source region 88 is formed. The insulating layer 40 is formed on the n ⁺ type silicon substrate 80 and the n ⁻ type epitaxial region 82.
The insulating layer 40 has at least a reverse bias.
p ⁻ type channel region 84 and n ⁻ type epitaxial region 82
Formed in a depletion layer (not shown) formed at the junction region with.

In this SIT2000B, the breakdown voltage between the source region and the drain region is improved by increasing the width of the depletion layer in n ⁻ type epitaxial region 82.

The present invention can be applied not only to the electrostatic induction type device such as the SIT, but also to a bipolar device (not shown). As a result, the p-type channel region (p-type base region) is further depleted than when the insulating layer is not provided, and as a result, electrons from the n-type source region (n-type emitter region) are drained (collector region). ), And a larger drain current (collector current) than before can be obtained when a drain voltage (collector voltage) equivalent to that of a device having a conventional structure is applied.

(Fourth Embodiment) FIG. 6 schematically shows a basic structure of a main part of a power MOS transistor according to the present invention. In the MOS transistor 3000 according to the present embodiment, an n ⁻ -type epitaxial region 15 is formed on an n ⁺ -type silicon substrate 14 forming a drain region, and the silicon substrate 10 is formed. And
A p ⁺ -type body region 18 is formed on the surface of the epitaxial region 15, and an n ⁺ -type source region 12 is formed in the body region 18. Further, a gate insulating film 20 is formed on the surface of the silicon substrate 10 at a position adjacent to the source region 12. The portion immediately below the gate insulating film 20 forms the channel region 16. Further, an insulating layer 40 extending in the thickness direction of the silicon substrate 10 is formed in the body region 18.

The insulating layer 40 has at least
At the time of reverse bias, it is formed so as to be included in a depletion layer (not shown) formed at a junction region between p ⁺ -type body region 18 and n ⁻ -type epitaxial region 15.

A gate electrode 30 is formed on the gate insulating film 20, and a source electrode 32 and a drain electrode 34 are formed on the surfaces of the source region 12 and the drain region 14, respectively.
Are formed.

In the MOS transistor 3000, by controlling the voltage applied to the gate electrode 30, an n-channel is formed in the channel region 16, the source region 12 and the drain region 14 are conducted, and the silicon substrate 10 A drain current flows in the thickness direction (vertical direction). The drain current flows in proportion to the voltage applied to the drain electrode 34.

Also in the present embodiment, body region 18
Having the insulating layer 40, the width of the depletion layer formed in the junction region of the p ⁺ -type body region 18-n ⁻ -type epitaxial region 15 can be increased as compared with the structure without the insulating layer 40, Therefore, the breakdown voltage determined by the width of the depletion layer is improved.

The insulating layer 40 is formed on the body region 18.
In addition, it can be formed in either the epitaxial region 15 or the source region 12 or at a plurality of locations.

(Fifth Embodiment) FIG. 7 schematically shows a basic structure of a main part of a UMOS transistor according to the present invention. The MOS transistor 4000 according to this embodiment is basically the same as the fourth embodiment in that a drain current flows vertically in the substrate in the vertical direction, but the gate electrode has a trench structure. This is different from the fourth embodiment in the point.

More specifically, n ⁺
A silicon substrate 10 is composed of a silicon substrate 14 and an n ⁻ -type epitaxial region 15 which is a high resistance layer formed on the substrate. A p ⁻ type body region 18 is formed on the surface of epitaxial region 15, and an n ⁺ type source region 1 is formed on the surface of body region 18.
2 are formed. A gate insulating film 20 (only a part is shown in FIG. 7) is formed in the silicon substrate 10 in the vertical direction, and a gate electrode 30 is formed therein. A channel region 16 is formed on the surface of the gate insulating film 20. The insulating layer 40 is formed in the p ⁻ type body region 18.

The insulating layer 40 has at least
At the time of reverse bias, the p ⁻ type body region 18 and n ⁻
It is formed so as to be included in a depletion layer (not shown) formed at a junction region with the type epitaxial region 15.

In this MOS transistor 4000, similarly to the fourth embodiment, by controlling the voltage applied to the gate electrode 30, an n-channel is formed in the channel region 16, and the source region 12 and the drain The region 14 is electrically connected, and a drain current flows in the thickness direction (vertical direction) of the silicon substrate 10.

Also in the present embodiment, body region 18
Having the insulating layer 40, the width of the depletion layer formed in the junction region of the p ⁻ -type body region 18-n ⁻ -type epitaxial region 15 can be increased as compared with the structure without the insulating layer 40. Therefore, the breakdown voltage determined by the width of the depletion layer is improved.

The insulating layer 40 is formed on the body region 18.
In addition, it can be formed in either the epitaxial region 15 or the source region 12 or at a plurality of locations.

(Sixth Embodiment) FIG. 8 shows a vertical MOS / bipolar composite transistor (IGBT; Insulated Ga) employing a pn junction according to the present invention.
FIG. 9 schematically shows a basic structure of a main part of te Bipolar Transistor, and FIG. 9 shows an equivalent circuit thereof. The IGBT 5000 is a composite transistor in which a MOS transistor (M1) and a PNP transistor Q1 are connected by inverted Darlingdon. In FIG. 9, reference numeral Q2 indicates a parasitic pnp transistor. MOS according to the fourth embodiment described above
The difference in the cross-sectional structure from the transistor 3000 is that a p ⁺ type silicon layer 17 is provided in the lowermost layer of the device.

That is, the IGBT 5 according to the present embodiment
000 forms a silicon substrate 10 by forming an n ⁺ type silicon layer 54 (14) and an n ⁻ type epitaxial region 15 on a p ⁺ type silicon layer 17 forming a collector region. Then, the epitaxial region 15
Is formed with ap ⁺ -type body region 18, and an n ⁺ -type emitter region 52 (12) is formed in the body region 18. On the surface of the silicon substrate 10, a gate insulating film 20 is formed at a position adjacent to the emitter region 52. The portion immediately below the gate insulating film 20 forms the channel region 16. An insulating layer 40 is formed in the p ⁺ type body region 18.

The insulating layer 40 is included at least in a depletion layer (not shown) formed at the junction between the p ⁺ -type body region 18 and the n ⁻ -type epitaxial region 15 at the time of reverse bias. Formed.

Further, a gate electrode 30 is formed on the gate insulating film 20 by the emitter region 52 and the collector region 17.
Are formed with an emitter electrode 62 and a collector electrode 64, respectively.

In the IGBT 5000, by controlling the voltage of the gate electrode 30, the channel region 1
6, an n-channel is formed, and electrons flow from the emitter region 52 to the collector region 17 through the channel. Since holes are injected from the collector region 17 correspondingly,
Conductivity modulation occurs in the n ⁺ -type silicon layer 54, and the on-resistance decreases. Therefore, the IGBT is a device suitable for high breakdown voltage as compared with the MOS transistor.

The insulating layer 40 is formed on the body region 18.
In addition, it can be formed in either the epitaxial region 15 or the emitter region 52 or at a plurality of locations.

The present invention is not limited to the IGBT having the planar structure shown in FIG.
It is also applicable to GBT.

The preferred embodiment of the present invention has been described above, but the present invention is not limited to this, and can be applied to elements of various modes. For example, in the examples according to the fourth to sixth embodiments, the case where the present invention is applied to an n-channel MOS transistor has been described. Further, in Embodiments 1 to 3, the case where an n-type substrate is used has been described. However, the present invention can be similarly applied to an element using a p-type substrate, and the same operation and effect can be obtained.

[0061]

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views schematically showing a configuration example when the present invention is applied to a pn junction diode.

FIG. 2 is a sectional view schematically showing a basic structure of a pn junction diode according to the first embodiment of the present invention.

3 is a diagram showing a voltage-current curve in a reverse bias state obtained for a pn junction diode shown in FIG. 2 and a comparative example.

FIG. 4 is a sectional view schematically showing a basic structure of an SIT according to a second embodiment of the present invention.

FIG. 5 is a sectional view schematically showing a basic structure of an SIT according to a third embodiment of the present invention.

FIG. 6 is a sectional view schematically showing a basic structure of a vertical power MOS transistor according to a fourth embodiment of the present invention.

FIG. 7 is a sectional view schematically showing a basic structure of a trench gate type power MOS transistor according to a fifth embodiment of the present invention.

FIG. 8 is a sectional view schematically showing a basic structure of an IGBT according to a sixth embodiment of the present invention.

9 is an equivalent circuit of the IGBT shown in FIG.

FIG. 10 is a cross-sectional view schematically showing a basic structure of a conventional general pn junction diode.

FIG. 11 is a diagram showing a pn junction having a bevel structure.

[Explanation of symbols]

 REFERENCE SIGNS LIST 10 silicon substrate 12 source region 14 drain region 16 channel region 18 body region 20 gate insulating film 30 gate electrode 32 source electrode 34 drain electrode 40 insulating layer 50 p-type region 60 n-type region 70 depletion layer 100, 200, 300 pn junction diode

──────────────────────────────────────────────────続 き Continuing on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 29/80 (72) Inventor Takashi Suzuki 41-cho, Yokomichi, Oji, Nagakute-cho, Aichi-gun, Aichi Prefecture 1 Toyota Central Research Laboratory Co., Ltd. (72) Inventor Tsutomu Uesugi 41-41, Yokomichi, Nagakute-cho, Aichi-gun, Aichi-gun

Claims (1)

[Claims] In a semiconductor device including a pn junction in which a p-type region made of a p-type semiconductor and an n-type region made of an n-type semiconductor are joined, at least one of the p-type region and the n-type region includes:
A semiconductor device including a pn junction, wherein an insulating region is formed, and at least a part of the insulating region is formed inside a depletion layer formed by the pn junction when reverse bias is applied.