CN106887466A - A kind of two-dimentional class super junction LDMOS device and preparation method thereof - Google Patents
A kind of two-dimentional class super junction LDMOS device and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 8
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- 238000002347 injection Methods 0.000 claims description 26
- 239000007924 injection Substances 0.000 claims description 26
- 239000007943 implant Substances 0.000 claims description 21
- 239000004065 semiconductor Substances 0.000 claims description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052710 silicon Inorganic materials 0.000 claims description 11
- 239000010703 silicon Substances 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims description 4
- 238000000137 annealing Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 claims description 3
- 238000000605 extraction Methods 0.000 claims description 3
- 239000004020 conductor Substances 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 10
- 230000005684 electric field Effects 0.000 abstract description 7
- 238000004519 manufacturing process Methods 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract description 6
- 238000010276 construction Methods 0.000 abstract description 4
- 238000005516 engineering process Methods 0.000 description 5
- 238000005457 optimization Methods 0.000 description 4
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000011982 device technology Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 1
- 240000002853 Nelumbo nucifera Species 0.000 description 1
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- 230000005404 monopole Effects 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7825—Lateral DMOS transistors, i.e. LDMOS transistors with trench gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
Abstract
The invention discloses a kind of two-dimentional class super junction LDMOS device and preparation method thereof, on the one hand the device replaces conventional plane grid using groove profile grid, drain electrode heavily doped region is extended to and the same even depth in drift region simultaneously, so that P posts connect low potential and high potential respectively with N posts in the superjunction of drift region, PN junction is more easy to exhaust under reversed electric field；On the other hand varying doping thought is also introduced into new construction, the P post region in drift region is carried out into Doping, doping concentration is gradually reduced by source electrode to draining.The two-dimentional class super junction LDMOS structure of new Doping P post region of the invention can eliminate substrate-assisted depletion effect, balance drift region charge, and preferable on state characteristic is maintained while improving device electric breakdown strength；Also, process is simple, it is easy to manufacture, can further reduce production cost.
Description
Technical field
The invention belongs to semiconductor power device technology field, and in particular to a kind of two-dimentional class super junction LDMOS device and its
Preparation method.
Background technology
LDMOS device is the how sub- device of monopole type, with good turn-off characteristic, input impedance high, is easy to extensive
Integrated the advantages of, it is widely applied in many fields.In LDMOS optimization designs the topmost first purpose be exactly
Cause that conducting resistance is as small as possible while obtaining maximum breakdown voltage.Due to this two indexs device design in for drift
The parameter request of area's doping concentration and length is contradiction, and breakdown voltage high will certainly bring conducting resistance high.Therefore, lead to
Cross to device architecture, material etc. optimization come the contradiction of trade off breakdown voltage and conducting resistance all the time be research focus.At present,
Domestic and foreign scholars propose various new constructions, such as RESURF LDMOS, SJ LDMOS to this.
For the LDMOS for meeting RESURF conditions, device voltage endurance is improved, but its conducting resistance with puncture
Voltage remains the proportionate relationship of 2.5 powers, i.e. Ron μ BV2.5.Therefore, conducting resistance high limits LDMOS device and exists
The application in high pressure field.
The application of superjunction technology can cause that drift region electric fields uniform is distributed, and obtain breakdown voltage as high as possible, therefore
Low on-resistance can be obtained by improving the doping concentration in post area.The introduction of superjunction technology is by conducting resistance and breakdown voltage
Proportionate relationship be reduced to 1.3 powers, furthermore achieved that optimization between both is traded off, Recent study is relatively broad.
But superjunction technology is higher for the requirement of technique, P post region mutually exhausts with N posts area alternating-doping, and drift region is thicker, and deposits
In more serious substrate-assisted depletion effect.
The content of the invention
The technical problem of solution：Existing superjunction technology is higher for the requirement of technique, P posts in order to solve for the purpose of the present invention
Area is with N posts area alternating-doping mutually exhausts, drift region is thicker, substrate-assisted depletion effect technical problem, there is provided a kind of two dimension
Class super junction LDMOS device and preparation method thereof.
Technical scheme：A kind of two-dimentional class super junction LDMOS device, its structure cell include longitudinal direction silicon substrate from bottom to top and
Semiconductor active layer；Wherein, it is N-type drift region in semiconductor active layer bottom；In N-type drift region, in semiconductor active
Layer surface side is provided with P- bodies area, and adjacent the first heavily-doped implant area and the second heavily-doped implant area is provided with P- bodies area, the
The common exit in one heavily-doped implant area and the second heavily-doped implant area is source electrode；In semiconductor active layer surface opposite side
The 3rd heavy doping injection region is provided with, the exit of the 3rd heavy doping injection region is drain electrode；In N-type drift region, in P- bodies
It is P drift area between area and the 3rd heavy doping injection region；The P- bodies area side is provided with adjacent gate oxide and gate electrode,
Gate electrode is longitudinally completely covered P- bodies area；Field oxide is provided between gate electrode and source electrode and source electrode and drain electrode between.
Further, the silicon substrate and the first heavily-doped implant area are p-type；Second heavily-doped implant area and the 3rd heavily doped
Miscellaneous injection region is N-type.
Further, the 3rd heavy doping injection region extends longitudinally to and the same even depth of N-type drift region.
Further, the P drift area is the doping of three ranks, forms P1 areas, P2 areas and P3 areas, and doping concentration gradually drops
It is low.
Further, the doping concentration in the P drift area is P1 areas 3e15cm-3, P2 areas 2e15cm-3, P3 areas
5e14cm-3。
The preparation method of above-mentioned two-dimentional class super junction LDMOS device, comprises the following steps：
1st step, on a silicon substrate epitaxial growth N-type epitaxy layer formed N-type drift region；
2nd step, ion implanting forms P drift area in N-type drift region；
3rd step, using the same window, first carries out p-well injection boron, and junction depth is formed by annealing process, continues to inject arsenic forming the
Two heavy doping injection regions, the difference that the junction depth of diffusion is injected twice forms P- bodies area；
4th step, injects in P- bodies area and forms the first heavily-doped implant area, the ion note on the right side of N-type drift region and P drift area
Enter to form the 3rd heavy doping injection region；
5th step, etching groove and gate oxide is formed on the left of P- bodies area, draws gate electrode；
6th step, field oxide, extraction electrode are formed in device surface.
Further, the doping concentration in the 2nd Bu Zhong P drifts area is P1 areas 3e15cm-3, P2 areas 2e15cm-3, P3 areas
5e14cm-3。
Beneficial effect：
1., than common two-dimentional super junction LDMOS structure, two-dimentional class super junction LDMOS device of the invention is designed using groove grid, together
When heavy doping drain electrode be connected with N drift regions so that P drift area and N-type drift region are respectively low potential under device off state
And high potential, beneficial to exhausting for drift region.
2. compared with three-dimensional super junction LDMOS device, two-dimentional class super junction LDMOS device of the invention, superjunction area is by transverse direction
P post region and N posts area are constituted, meanwhile, P post region uses Doping, and doping concentration is gradually reduced from source to drain terminal, on the one hand,
The P post region of Doping can introduce new peak electric field at junction interface, and the bulk electric field to device is modulated, and then improve
Device is pressure-resistant；On the other hand, the doping concentration in N posts area can be improved to P post region Doping, conducting resistance is entered one during ON state
Step is reduced.Compared with three-dimensional super junction LDMOS device, new construction technique proposed by the present invention realizes more simple, low production cost.
Brief description of the drawings
Fig. 1 is the generalized section of ordinary two dimensional class super junction LDMOS device；
Fig. 2 is a kind of generalized section with Uniform Doped P post region two dimension class super junction LDMOS device of the present invention；
Fig. 3 is of the present invention a kind of with Doping P post region two dimension class super junction LDMOS device；
Wherein, 1 be silicon substrate, 2 be N-type drift region, 3 be P- bodies area, 4 be gate oxide 4,6 be the first heavily-doped implant area, 7
For the second heavily-doped implant area, 8 be the 3rd heavy doping injection region, 10 be P drift area, 13 be field oxide, Source be source
Electrode, Drain drain electrodes, Gate are gate electrode.
Specific embodiment
Specific embodiment of the invention is described in further detail below.
Embodiment 1
Fig. 2 is Uniform Doped P post region two dimension class super junction LDMOS device architecture schematic diagram proposed by the present invention, and structure cell includes
Longitudinal direction silicon substrate 1 and semiconductor active layer from bottom to top；It is N-type drift region 2 in semiconductor active layer bottom；Positioned at N-type drift
Move in area 2, be provided with P- bodies area 3 in semiconductor active layer surface side, P- bodies area 3 is interior to be provided with the first adjacent heavily-doped implant area
6 and the second heavily-doped implant area 7, the common exit in the first heavily-doped implant area 6 and the second heavily-doped implant area 7 is source electrode
S；The 3rd heavy doping injection region 8 is provided with semiconductor active layer surface opposite side, the exit of the 3rd heavy doping injection region 8 is leakage
Electrode D；It is P drift area 10 in N-type drift region 2, between P- bodies area 3 and the 3rd heavy doping injection region 8；The P- bodies
3 areas side are provided with adjacent gate oxide 4, and the exit of gate oxide 4 is gate electrode 5, and the longitudinal direction of gate electrode 5 is completely covered P- bodies
Area 3；Between gate electrode 5 and source electrode S, field oxide 13 is provided between source electrode S and drain electrode D.The silicon substrate 1, P- bodies
Area 3, the first heavily-doped implant area 6 are p-type；Second heavily-doped implant area 7 and the 3rd heavy doping injection region 8 are N-type.Described 3rd
The post area in heavily-doped implant area 8 extends longitudinally to and the same even depth of N-type drift region 2.
With ordinary two dimensional class super junction LDMOS device（As shown in Figure 1）Compare, two-dimentional class super junction LDMOS device of the invention
One side lead-ingroove grid（Trench-Gate）Structure so that P drift area connects with source electrode p-well region, P under device off state
Drift region is low-potential state；On the other hand, by heavy doping drain electrode extend to the same even depth in drift region, with N-type drift region phase
Connect, N drift regions are high potential state to device in the off case.As shown in Fig. 2 under off state, P drift area floats with N-type
The PN junction for moving area's composition is coupled with reversed electric field, it is easier to which charge depletion is so as to play voltage support effect.
The manufacture method of above-mentioned Uniform Doped P post region two dimension class super junction LDMOS device is comprised the following steps（Such as Fig. 2 institutes
Show, be introduced by taking N-shaped LDMOS as an example, p-type LDMOS only need to be by the ion implanting type of each step conversely, Each part
Doping type is opposite）：
1st step, in the certain thickness N-type epitaxy layer of Epitaxial growth of P-type silicon substrate 1, as N-type drift region 2；
2nd step, ion implanting forms P drift area 10 in N-type epitaxy layer；
3rd step, using the same window, first carries out p-well injection boron, and impurity is made to diffusion in vivo by prolonged annealing process,
Certain junction depth is formed, injection donor impurity arsenic is then proceeded to and is formed source class contact 7.Because boron is faster than arsenic diffusion, inject twice
The difference of the junction depth of diffusion is formed P- bodies area 3；
4th step, injects heavily doped region PXing Zhu areas 6 in P- bodies area 3, and ion implanting forms heavily doped N-type note on the right side of drift region
Enter area 8, heavily doped N-type injection region 8 is then the drain electrode of the LDMOS device；
5th step, etching groove and gate oxide 4 is formed on the left of p-well, draws gate electrode 5；
6th step, field oxide 11, extraction electrode 9 are formed in device surface.
Breakdown voltage high is highly important performance indications for LDMOS device with low conducting resistance, for reality
The good compromise of existing breakdown voltage and conducting resistance, the doping concentration for adjusting regional is most important with width.
According to the manufacture method of two-dimentional class super junction LDMOS device of the present invention, in the 1st step, the doping of P-type silicon substrate
Concentration is 4e13cm-3。
According to the manufacture method of two-dimentional class super junction LDMOS device of the present invention, in the 2nd step, superjunction area is by horizontal P
Post and N posts are constituted, and P posts are located on N posts, are distributed in drift region surface, and the doping that such construction ratio can improve N posts is dense
Degree, in the conducting resistance of the identical resistance to low device of drops.The depth for obtaining optimal P post region and N posts area is emulated by MEDICI
Than being 1/1, optimal doping concentration is that the doping concentration of P post region is 3e15 cm in superjunction area-3, the doping concentration of N posts is
3e15cm-3, below or above the breakdown voltage that the optimal value of emulation can all reduce device.Under identical doping concentration, with
The increase of drift region length, the breakdown voltage of device also can be improved and then.
Embodiment 2
Fig. 3 is the two-dimentional class super junction LDMOS device architecture schematic diagram of Doping P post region proposed by the present invention, the P drift
Area is adulterated for three ranks, forms P1 areas, P2 areas and P3 areas, and doping concentration is gradually reduced.
P post region in superjunction area is carried out into Doping, doping concentration is gradually reduced from source to test leakage.This P post region is adopted
Principle and working mechanism are：Device reversely it is pressure-resistant when, according to substrate-assisted depletion effect mechanism, drift region can produce from
Source is to drain terminal gradually increased excess carriers.The present invention is by P post region Doping, can fully reduce excess charge
Generation, by the optimization design to P post region doping concentration and width, the electricity between P post region and N posts area in superjunction can be caused
Lotus reaches poised state, reduces the substrate-assisted depletion effect influence pressure-resistant to device.On the one hand, the P post region of Doping
New peak electric field can be introduced at junction interface, the bulk electric field to device is modulated, and then it is pressure-resistant to improve device；The opposing party
Face, the doping concentration in N posts area can be improved to P post region Doping, and conducting resistance is further reduced during ON state.
On the basis of Uniform Doped P post region two dimension class super junction LDMOS device, by increasing by two pieces of mask plates by P post region
Doping is carried out, doping concentration is gradually reduced from source to drain terminal, be distributed in ladder, be followed successively by P1：3e15cm-3、P2：
2e15cm-3、P3:5e14cm-3。
Compared with three-dimensional super junction LDMOS structure, device technology of the present invention is more simple, beneficial to the manufacturing and drop
Low cost.
Structure, step, numerical value in above-described embodiment etc. are signal, on the premise of inventive concept is not violated, this
The those skilled in the art in field can be replaced on an equal basis, it is also possible to make some deformations and improvement, and these belong to the present invention
Protection domain.
Claims (7)
1. a kind of two-dimentional class super junction LDMOS device, structure cell includes longitudinal direction silicon substrate from bottom to top（1）And semiconductor active
Layer；It is characterized in that：It is N-type drift region in semiconductor active layer bottom（2）；Positioned at N-type drift region（2）Above, have in semiconductor
Active layer surface side is provided with P- bodies area（3）, P- bodies area（3）Inside it is provided with the first adjacent heavily-doped implant area（6）It is heavily doped with second
Miscellaneous injection region（7）, the first heavily-doped implant area（6）With the second heavily-doped implant area（7）Common exit be source electrode；Half
Conductor active layer surface opposite side is provided with the 3rd heavy doping injection region（8）, the 3rd heavy doping injection region（8）Exit for electric leakage
Pole；Positioned at N-type drift region（2）Above, in P- bodies area（3）With the 3rd heavy doping injection region（8）Between be P drift area（10）；Institute
State P- bodies（3）Area side is provided with adjacent gate oxide（4）, gate oxide（4）Exit be gate electrode, gate electrode is longitudinally complete
All standing P- bodies area（3）；Field oxide is provided between gate electrode and source electrode and source electrode and drain electrode between（13）.
2. two-dimentional class super junction LDMOS device according to claim 1, it is characterised in that：The silicon substrate（1）With the first weight
Doping injection region（6）It is p-type；Second heavily-doped implant area（7）With the 3rd heavy doping injection region（8）It is N-type.
3. two-dimentional class super junction LDMOS device according to claim 1, it is characterised in that：The 3rd heavy doping injection region
（8）Extend longitudinally to and N-type drift region（2）Same even depth.
4. the two-dimentional class super junction LDMOS device according to any one of claims 1 to 3, it is characterised in that：The P drift
Area（10）For three ranks are adulterated, P1 areas, P2 areas and P3 areas are formed, doping concentration is gradually reduced.
5. two-dimentional class super junction LDMOS device according to claim 4, it is characterised in that：The doping in the P drift area is dense
Du Wei P1 area 3e15cm-3, P2 areas 2e15cm-3, P3 areas 5e14cm-3。
6. the preparation method of the two-dimentional class super junction LDMOS device described in claim 1, it is characterised in that：Comprise the following steps：
1st step, on a silicon substrate epitaxial growth N-type epitaxy layer formed N-type drift region；
2nd step, ion implanting forms P drift area in N-type drift region；
3rd step, using the same window, first carries out p-well injection boron, and junction depth is formed by annealing process, continues to inject arsenic forming the
Two heavy doping injection regions, the difference that the junction depth of diffusion is injected twice forms P- bodies area；
4th step, injects in P- bodies area and forms the first heavily-doped implant area, the ion note on the right side of N-type drift region and P drift area
Enter to form the 3rd heavy doping injection region；
5th step, etching groove and gate oxide is formed on the left of P- bodies area, draws gate electrode；
6th step, field oxide, extraction electrode are formed in device surface.
7. the preparation method of two-dimentional class super junction LDMOS device according to claim 6, it is characterised in that：P-type in 2nd step
The doping concentration of drift region is P1 areas 3e15cm-3, P2 areas 2e15cm-3, P3 areas 5e14cm-3。
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108493247A (en) * | 2018-02-28 | 2018-09-04 | 南京邮电大学 | A kind of SJ-VDMOS devices and manufacturing method with P post region and N columns area Doping |
| CN110120423A (en) * | 2019-05-05 | 2019-08-13 | 南京邮电大学 | A kind of LDMOS device and preparation method thereof |
| CN110310983A (en) * | 2019-07-31 | 2019-10-08 | 电子科技大学 | A kind of hyperconjugation VDMOS device |
| CN110416285A (en) * | 2019-07-31 | 2019-11-05 | 电子科技大学 | A kind of superjunction power DMOS device |
| CN111477681A (en) * | 2020-04-23 | 2020-07-31 | 西安电子科技大学 | Double-channel uniform electric field modulation transverse double-diffusion metal oxide semiconductor field effect transistor and manufacturing method thereof |
| CN111477680A (en) * | 2020-04-23 | 2020-07-31 | 西安电子科技大学 | Double-channel uniform electric field modulation transverse double-diffusion metal oxide wide-band-gap semiconductor field effect transistor and manufacturing method thereof |
| CN111834462A (en) * | 2018-06-28 | 2020-10-27 | 华为技术有限公司 | Semiconductor device and manufacturing method |
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