CN102790092A - Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device - Google Patents
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The invention relates to a transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device and belongs to the technical field of semiconductor power devices. The device is characterized in that concentration of first conductive type semiconductor reduced-field layers 3 is increased, area of the first conductive type semiconductor reduced-field layers 3 in the width direction of the device is reduced, and extra second conductive type semiconductor current channels 16 are provided among the reduced-field layers 3, so that area of a current flow path is increased; in addition, a shorter conductive path is provided, and concentration of a second conductive type semiconductor drift region 16 can be increased, so that on-resistance of the device is greatly lowered. Compared with conventional transverse high-voltage DMOS devices with reduced-field layers, the transverse high-voltage DMOS device has smaller on-resistance when chip area is identical (or has smaller chip area when conducting capability is identical). The high-voltage DMOS device can be applied to various products of consumer electronics, display drivers and the like. Current capability of the transverse high-voltage DMOS device is increased by 17% when compared with that of existing dual-channel transverse high-voltage DMOS devices.
Description
Technical field
The invention belongs to the semiconductor power device technology field, relate to horizontal high-pressure MOS component and manufacturing approach thereof.
Background technology
Horizontal high pressure DMOS (Double-diffused MOSFET) is a kind of as power device; It is in body silicon or SOI (Silicon On Insulator) in critical role is all arranged; Development along with smart-power IC; Laterally high pressure DMOS device is again because its source electrode, grid and drain electrode are positioned at silicon chip surface, is easy to through interconnector with device and the low voltage logic monolithic is integrated develops rapidly.The conducting resistance R of horizontal high pressure DMOS device
OnThere is Ron ∝ BV with device withstand voltage BV
2.3～2.6Relation, promptly along with the rising conducting resistance R of device withstand voltage BV
OnAlso constantly rise; In order to overcome this contradictory relation; People such as J.A.APPLES have proposed RESURF (Reduced SURface Field) and have reduced the surface field technology; Proposed the breakdown Model of horizontal high pressure DMOS device, this model was pointed out high pressure DMOS device before device breakdown, and the drift region exhausts respectively on horizontal and vertical both direction; Through drift region junction depth, substrate charge density and trap charge density are brought in the depletion width computing formula, estimating drift region unit are impurity density is 1.2 * 10
12Cm
-2The time device breakdown is withstand voltage reaches the highest, this technology plays an important role on device withstand voltage improves, but produces little effect to reducing conducting resistance.Hu Xiarong; People such as silver China fir have proposed the Triple RESURF technology in SOI and the body silicon at " A new high voltage SOI LDMOS with triple RESURF structure " and " Design of 700V triple RESURF nLDMOS with low on-resistance " respectively; This technology is through falling a layer (like Fig. 1, shown in 2) to introducing in the drift region; It is extra reversed charge; And the charge carrier quantity of participating in conduction is increased, and solved the contradiction between conducting resistance and the device withstand voltage to a certain extent, but still satisfied not of the specification requirement of the power integrated circuit of high speed development to horizontal high pressure DMOS device.
Summary of the invention
Technical problem
The present invention provides a kind of horizontal high pressure DMOS device and manufacturing approach thereof.Said horizontal high pressure DMOS device has a horizontal high pressure DMOS device that falls the field layer with tradition to be compared, and its conducting resistance further reduces and not extra chip occupying area (or under the situation of identical ducting capacity, having littler chip area).Said structure making process is simple, and technology difficulty is relatively low.
Technical scheme of the present invention is following:
A kind of horizontal high pressure DMOS device; As shown in Figure 3, comprise that medium 13 before a layer 3, the first conductive type semiconductor buried regions 4, the first conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, polygate electrodes 9, the second conductive type semiconductor drain region 10, the second conductive type semiconductor source region 11, the first conductive type semiconductor body contact zone 12, the metal, source metal 14, drain metal 15 fall in the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, first conductive type semiconductor; The second conductive type semiconductor drift region 2 is positioned at the first conductive type semiconductor substrate, 1 surface; 2 inside, the second conductive type semiconductor drift region have first conductive type semiconductor and fall a layer 3; It is drain metal 15 that 2 tops, the second conductive type semiconductor drift region, one side has 10 surfaces, 10, the second conductive type semiconductor drain regions, the second conductive type semiconductor drain region; What link to each other with the second conductive type semiconductor drift region, 2 top opposite sides is to have the second conductive type semiconductor source region 11 and the first conductive type semiconductor body contact zone 12 separate and that all link to each other with source metal 14 in 6, the first conductive type semiconductor tagmas 6, the first conductive type semiconductor tagma; The first conductive type semiconductor buried regions 4 is between the first conductive type semiconductor tagma 6 and the first conductive type semiconductor substrate 1, and its side contacts with the second conductive type semiconductor drift region 2; The region surface that the first conductive type semiconductor tagma 6 and the second conductive type semiconductor drift region 2 join is a gate oxide 8; The remaining surface of the second conductive type semiconductor drift region 2 covers field oxide 7, and gate oxide 8 and gate oxide 8 are polygate electrodes 9 with the region surface that field oxide 7 joins; Fill the preceding medium 13 of metal between polygate electrodes 9, source metal 14 and the drain metal 15.Shown in Figure 4 is along the profile of BB ' line among Fig. 3; Compare with the horizontal high pressure DMOS of tradition shown in Figure 2 section; What horizontal high pressure DMOS device provided by the invention was different with existing horizontal high pressure DMOS device is; Horizontal high pressure DMOS device provided by the invention falls in the layer 3 at said first conductive type semiconductor and evenly to embed to such an extent that the second conductive type semiconductor current channel 16 arranged along the Width of device; And suitably improve the doping content that layer 3 falls in first conductive type semiconductor and fall an effect to keep, the doping content that suitably improves the second conductive type semiconductor current channel 16 simultaneously is to keep charge balance and to reduce break-over of device resistance.
Horizontal high pressure DMOS device provided by the invention; As shown in Figure 5; It is that its length and doping content are reduced to the second conductive type semiconductor drain region 10 by the second conductive type semiconductor source region 11 gradually along the discontinuous construction of the piecewise linearity varying doping of device horizontal direction that a layer 3 falls in said first conductive type semiconductor; First conductive type semiconductor falls in the layer 3 and equally evenly to embed to such an extent that the second conductive type semiconductor current channel 16 arranged along the Width of device.
Horizontal high pressure DMOS device provided by the invention, its operation principle and traditional horizontal high pressure DMOS device are similar, all are the puncture voltages that the utilization charge balance concept improves device, but the break-over of device loss among the present invention is lower than laterally high pressure DMOS device of tradition.Fig. 1 is traditional horizontal high pressure DMOS device, comprises that medium 13 before a layer 3, the first conductive type semiconductor buried regions 4, the first conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, grid 9, the second conductive type semiconductor drain region 10, the second conductive type semiconductor source region 11, the first conductive type semiconductor body contact zone 12, the metal, source metal 14, drain metal 15 fall in the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, first conductive type semiconductor.Electric current flows to the second conductive type semiconductor drain region 10 from the second conductive type semiconductor source region 11 through the second conductive type semiconductor drift region 2 during break-over of device; Because an existence of layer 3 falls in first conductive type semiconductor; The area of current flow path diminishes; And the flow path of electric current when drift region 2 is elongated, so the conducting resistance of device becomes greatly, conduction loss increases.Fig. 3 is a horizontal high pressure DMOS device of the present invention; Shown in Figure 4 is along BB ' profile among Fig. 3; Have a horizontal high pressure DMOS who falls layer structure and compare with existing; Device provided by the invention is through improving the concentration of the first conductive type semiconductor field layer 3; In falling a layer 3, evenly embedding the second conductive type semiconductor current channel 16 along the device widths direction (has been equivalent to reduce first conductive type semiconductor and has fallen the area of layer 3 on the device widths direction, thereby increased the area of current flow path, relatively short conductive path also is provided simultaneously; And can increase the concentration of the second conductive type semiconductor current channel 16, to keep charge balance and to reduce break-over of device resistance.）
The invention has the beneficial effects as follows:
The present invention falls a concentration of layer 3 through improving first conductive type semiconductor; Reduce first conductive type semiconductor and fall the area of layer 3 on the device widths direction; The second extra conductive type semiconductor current channel 16 is provided falling between the layer 3, has increased the area of current flow path, relatively short conductive path also is provided simultaneously; And can increase the concentration of the second conductive type semiconductor drift region 16, greatly reduce break-over of device resistance.Have a horizontal high pressure DMOS device that falls the field layer with routine and compare, horizontal high pressure DMOS device provided by the invention has littler conducting resistance (or under the situation of identical ducting capacity, having littler chip area) under the situation of identical chips area.High-voltage semi-conductor device provided by the invention can be applicable in the multiple products such as consumer electronics, display driver.The existing horizontal high pressure DMOS of the binary channels device current capability of its current capacity has 17% raising.
Description of drawings
Fig. 1 is the existing horizontal high pressure DMOS device architecture sketch map that falls field layer structure that has.
Fig. 2 is that existing to have a horizontal high pressure DMOS device that falls layer structure be that structure shown in Figure 1 is along AA ' generalized section along the line.
Fig. 3 is a kind of horizontal high pressure DMOS device architecture sketch map provided by the invention.
Fig. 4 is that a kind of horizontal high pressure DMOS device provided by the invention is that structure shown in Figure 3 is along BB ' generalized section along the line.
Fig. 5 is a kind of horizontal high pressure DMOS device architecture sketch map provided by the invention.
Among Fig. 1 to Fig. 5: 1 is the first conductive type semiconductor substrate; 2 is second conductive type semiconductor drift regions; 3 is that a layer falls in first conductive type semiconductor; 4 is first conductive type semiconductor buried regions; 6 is first conductive type semiconductor tagmas; The 7th, field oxide; The 8th, gate oxide; The 9th, polygate electrodes; 10 is second conductive type semiconductor drain regions; 11 is second conductive type semiconductor source regions; 12 is first conductive type semiconductor body contact zones; The 13rd, medium before the metal; The 14th, source metal; The 15th, drain metal; 16 is second conductive type semiconductor current channels.
Fig. 6 (a) has the horizontal high pressure DMOS of binary channels device through the silvaco ATLAS of three-dimension device simulation software definition existing to fall layer 3 a position view in transverse section having first conductive type semiconductor.
Fig. 6 (b) has the horizontal high pressure DMOS of binary channels device through the silvaco ATLAS of three-dimension device simulation software definition existing to have second conductive type semiconductor, 16 position view in transverse section.
Fig. 7 is existing relation curve sketch map with binary channels horizontal high pressure DMOS device and high pressure DMOS device provided by the invention drain-source current and drain-source voltage when linear zone.Wherein dotted line is the horizontal high pressure DMOS of existing binary channels device drain-source current and drain-source voltage relation curve, and solid line is multiple current path high pressure DMOS device drain-source current provided by the invention and drain-source voltage relation curve.Can know that by figure when Vds=10V, the electric current of the horizontal high pressure DMOS of existing binary channels device is 25 μ A/ μ m; Device current provided by the invention is 30 μ A/ μ m, and current capacity has improved 17% than traditional structure.
Embodiment
A kind of horizontal high pressure DMOS device; As shown in Figure 3, comprise that medium 13 before a layer 3, the first conductive type semiconductor buried regions 4, the first conductive type semiconductor tagma 6, field oxide 7, gate oxide 8, polygate electrodes 9, the second conductive type semiconductor drain region 10, the second conductive type semiconductor source region 11, the first conductive type semiconductor body contact zone 12, the metal, source metal 14, drain metal 15 fall in the first conductive type semiconductor substrate 1, the second conductive type semiconductor drift region 2, first conductive type semiconductor; The second conductive type semiconductor drift region 2 is positioned at the first conductive type semiconductor substrate, 1 surface; 2 inside, the second conductive type semiconductor drift region have first conductive type semiconductor and fall a layer 3; It is drain metal 15 that 2 tops, the second conductive type semiconductor drift region, one side has 10 surfaces, 10, the second conductive type semiconductor drain regions, the second conductive type semiconductor drain region; What link to each other with the second conductive type semiconductor drift region, 2 top opposite sides is to have the second conductive type semiconductor source region 11 and the first conductive type semiconductor body contact zone 12 separate and that all link to each other with source metal 14 in 6, the first conductive type semiconductor tagmas 6, the first conductive type semiconductor tagma; The first conductive type semiconductor buried regions 4 is between the first conductive type semiconductor tagma 6 and the first conductive type semiconductor substrate 1, and its side contacts with the second conductive type semiconductor drift region 2; The region surface that the first conductive type semiconductor tagma 6 and the second conductive type semiconductor drift region 2 join is a gate oxide 8; The remaining surface of the second conductive type semiconductor drift region 2 covers field oxide 7, and gate oxide 8 and gate oxide 8 are polygate electrodes 9 with the region surface that field oxide 7 joins; Fill the preceding medium 13 of metal between polygate electrodes 9, source metal 14 and the drain metal 15.Shown in Figure 4 is along the profile of BB ' line among Fig. 3; Compare with the horizontal high pressure DMOS of tradition shown in Figure 2 section; What horizontal high pressure DMOS device provided by the invention was different with existing horizontal high pressure DMOS device is; Horizontal high pressure DMOS device provided by the invention falls in the layer 3 at said first conductive type semiconductor and evenly to embed to such an extent that the second conductive type semiconductor current channel 16 arranged along the Width of device; And suitably improve the doping content that layer 3 falls in first conductive type semiconductor and fall an effect to keep, the doping content that suitably improves the second conductive type semiconductor current channel 16 simultaneously is to keep charge balance and to reduce break-over of device resistance.
Horizontal high pressure DMOS device provided by the invention; As shown in Figure 5; It is that its length and doping content are reduced to the second conductive type semiconductor drain region 10 by the second conductive type semiconductor source region 11 gradually along the discontinuous construction of the piecewise linearity varying doping of device horizontal direction that a layer 3 falls in said first conductive type semiconductor; First conductive type semiconductor falls in the layer 3 and equally evenly to embed to such an extent that the second conductive type semiconductor current channel 16 arranged along the Width of device.
Horizontal high pressure DMOS power device provided by the invention; Can select to realize with epitaxy technique; Also can be chosen in the technology of injecting and spreading with energetic ion on the body silicon realizes; Its technology difficulty is low, and is workable, selects dissimilar substrates and impurity can produce the horizontal high pressure DMOS device of n raceway groove and p raceway groove.
Critical process step
Adopt photoetching and ion implantation technology; In the second conductive type semiconductor drift region 2, injecting first conductive type semiconductor forms first conductive type semiconductor and falls a layer 3; A layer 3 falls in said first conductive type semiconductor can a step form single CONCENTRATION DISTRIBUTION; Also but multistep forms the structure that piecewise linearity is mixed, and in the first conductive type semiconductor substrate 1, forms the first conductive type semiconductor buried regions tagma 4 simultaneously; It is 5E11cm that an implantation dosage in the layer 3 and first conductive type semiconductor buried regions tagma 4 falls in said first conductive type semiconductor
-2～1E13cm
-2Adopt photoetching and ion implantation technology, inject second conductive type semiconductor to form the second conductive type semiconductor current channel 16 of high concentration in the second conductive type semiconductor drift region 2 that the first adjacent conductive type semiconductor falls between the layer 3; The implantation dosage of the said second conductive type semiconductor current channel 16 is 1E12cm
-2～1E14cm
-2
Need to prove that the described first conductive type semiconductor buried regions 4 when the thin or first conductive type semiconductor tagma, 6 junction depths are dark in the second conductive type semiconductor drift region 2, can not done.Said first conductive type semiconductor falls layer 3 and first a conductive type semiconductor buried regions 4 and can form step by step, also can form simultaneously.When the said second conductive type semiconductor drift region 2 concentration are enough high or first conductive type semiconductor and the width of the second conductive type semiconductor conductive channel that embeds in the layer 3 falls when enough wide, improve the process of the second conductive type semiconductor current channel, 16 concentration and can not do.The said second conductive type semiconductor drift region 2 can be injected and once formation of diffusion through ion, also can form through epitaxy technique.
Claims (2)
1. a horizontal high pressure DMOS device comprises that layer (3), first a conductive type semiconductor buried regions (4), the first conductive type semiconductor tagma (6), field oxide (7), gate oxide (8), polygate electrodes (9), the second conductive type semiconductor drain region (10), the second conductive type semiconductor source region (11), the first conductive type semiconductor body contact zone (12), the preceding medium (13) of metal, source metal (14), drain metal (15) fall in the first conductive type semiconductor substrate (1), the second conductive type semiconductor drift region (2), first conductive type semiconductor; The second conductive type semiconductor drift region (2) is positioned at first conductive type semiconductor substrate (1) surface; Inside, the second conductive type semiconductor drift region (2) has first conductive type semiconductor and falls a layer (3); Top, the second conductive type semiconductor drift region (2) one side has the second conductive type semiconductor drain region (10), and surface, the second conductive type semiconductor drain region (10) is drain metal (15); What link to each other with top, the second conductive type semiconductor drift region (2) opposite side is the first conductive type semiconductor tagma (6), has the second conductive type semiconductor source region (11) and the first conductive type semiconductor body contact zone (12) separate and that all link to each other with source metal (14) in the first conductive type semiconductor tagma (6); The first conductive type semiconductor buried regions (4) is positioned between the first conductive type semiconductor tagma (6) and the first conductive type semiconductor substrate (1), and its side contacts with the second conductive type semiconductor drift region (2); The region surface that the first conductive type semiconductor tagma (6) and the second conductive type semiconductor drift region (2) join is gate oxide (8); The remaining surface of the second conductive type semiconductor drift region (2) covers field oxide (7), and gate oxide (8) and gate oxide (8) are polygate electrodes (9) with the region surface that field oxide (7) joins; Fill the preceding medium (13) of metal between polygate electrodes (9), source metal (14) and the drain metal (15); It is characterized in that, fall in the layer (3) at said first conductive type semiconductor and evenly embed to such an extent that the second conductive type semiconductor current channel (16) arranged along the Width of device; And suitably improve the doping content that layer (3) falls in first conductive type semiconductor and fall an effect to keep, the doping content that suitably improves the second conductive type semiconductor current channel (16) simultaneously is to keep charge balance and to reduce break-over of device resistance.
2. horizontal high pressure DMOS device according to claim 1; It is characterized in that; It is that its length and doping content are reduced to the second conductive type semiconductor drain region (10) by the second conductive type semiconductor source region (11) gradually along the discontinuous construction of the piecewise linearity varying doping of device horizontal direction that a layer (3) falls in said first conductive type semiconductor; First conductive type semiconductor falls in the layer (3) and equally evenly to embed to such an extent that second conductive type semiconductor (16) arranged along the Width of device.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104269441A (en) * | 2014-10-22 | 2015-01-07 | 桂林电子科技大学 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
| CN104752500A (en) * | 2013-12-25 | 2015-07-01 | 上海华虹宏力半导体制造有限公司 | Radio-frequency LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and technological method |
| CN104009090B (en) * | 2014-05-29 | 2017-05-31 | 西安电子科技大学 | A kind of lateral double diffusion metal oxide semiconductor FET |
| CN104269403B (en) * | 2014-10-22 | 2017-08-22 | 桂林电子科技大学 | Linear spacing distribution fixed charge island SOI pressure-resistance structures and power device |
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| CN102097469A (en) * | 2009-12-10 | 2011-06-15 | 世界先进积体电路股份有限公司 | Semiconductor structure and manufacture method thereof |
| CN101771085A (en) * | 2010-01-20 | 2010-07-07 | 电子科技大学 | High-voltage semi-conductor device and manufacturing method thereof |
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| CN104269441B (en) * | 2014-10-22 | 2017-05-10 | 桂林电子科技大学 | SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device |
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