CN102097484A - Multichannel LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof - Google Patents
Multichannel LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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- H01L29/42312—Gate electrodes for field effect devices
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- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
- H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
Abstract
The invention discloses a multichannel LDMOS (laterally diffused metal oxide semiconductor) and a preparation method thereof. The multichannel LDMOS comprises a source region 5, a drain region 6, a gate dielectric layer 10, a field oxide layer 11, a metal front dielectric layer 12, a drift region 2, a substrate well contact region 4, a substrate well 7, source electrode metal 8 and drain electrode metal 9 which are all arranged in a substrate 1, wherein no gap is arranged between the substrate well 7 and the drift region 2; the conduction type of the drift region 2 is the same as that of a channel of the multichannel LDMOS; and the conduction type of the substrate well 7 is opposite to that of the channel of the multichannel LDMOS. The multichannel LDMOS also comprises a buried layer strip array which comprises at least one row of a plurality of first buried layer strips 3A distributed laterally, the buried layer strip array is arranged below the field oxide layer 11, is defined by the drift region 2 and keeps a distance from the field oxide layer 11; and the conduction type of the first buried layer strips 3A is opposite to that of the channel of the multichannel LDMOS. According to the invention, the on resistance of an LDMOS transistor is effectively reduced.
Description
Technical field
The present invention relates to the semiconductor power device technology field, relate in particular to a kind of multichannel LDMOS and preparation method thereof.
Background technology
Along with the high speed development of microelectric technique, high pressure BCD technology has been widely used in analog circuit fields such as LED driving, Switching Power Supply.Wherein power tube mainly adopts lateral direction bilateral diffusion MOS device (LateralDouble-diffused MOSFET), reduces the main direction that its conduction resistance (conducting resistance * area) becomes high pressure BCD technological development satisfying under the prerequisite of its requirement of withstand voltage.Tradition LDMOS adopts single resurf (reduced surface field, reduce surface field) or 2 times of resurf technology, along with the develop rapidly of modern analog circuit, this structure more and more can not satisfy the requirement of chip designer to the chip of small size high reliability.This is had the people proposed SJ (Super Junction, super trap) DMOS, but this structure is higher to technological requirement, has only Very few companies can produce this type of device in the world; The more power device VDMOS of another kind of application need prepare special techniques such as extension and thin slice, and cost is higher, and the manufacturing cycle is longer; The devices such as IGBT that have less conducting resistance in addition are subjected to factor restrictions such as its turn-off speed is slow, cut-in voltage is high, reliability is relatively poor, integrated comparatively complexity also seldom to be used in high pressure BCD technology field.In addition, U.S. Power Integrations company has proposed a kind of LDMOS that utilizes binary channels to reduce conducting resistance, this structure is utilized 2.5 times of resurf technology, can form binary channels LDMOS, and its conduction resistance has reduced about 30% than 2 times of resurf LDMOS commonly used at present.
Fig. 1 is the structural representation of 2 times of resurf ldmos transistors of tradition.As shown in Figure 1,2 times of resurf LDMOS of tradition only have a conductive path, see the drift region 2a of the below of trap 3a among Fig. 1, the purpose of area 1a and trap 3a all is in order to help drift region 2a to exhaust, 2 times of resurf principles that Here it is, the concentration that improves drift region 2a can reduce its conducting resistance, but drift region 2a can't lean on 1a and 3a to exhaust when its concentration reaches certain value, and withstand voltage decline this moment does not reach application requirements.
Fig. 2 is the structural representation of binary channels ldmos transistor in the prior art.As shown in Figure 2, the difference of the LDMOS of channel structure and 2 times of resurf LDMOS shown in Figure 1 is, trap 3b is embedded in the body by the surface, current path just has two passages like this, compared to Figure 1 LDMOS has had more the surface channel of a high concentration, when the drift region of two kinds of structures has under the same dose condition, the conducting resistance of structure shown in Figure 2 is littler than structure shown in Figure 1.Because Fig. 2 has two passages, and its drift region 2b is easier to be depleted, and when satisfying the withstand voltage condition of identical height, the drift region 2b of structure shown in Figure 2 can have higher concentration, its conducting resistance is also just littler like this, 2.5 times of resurf principles that Here it is in addition.But the conducting resistance of LDMOS still has the space of reduction.
Summary of the invention
The technical problem to be solved in the present invention is, conducting resistance or the withstand voltage defective that does not reach application requirements at LDMOS in the prior art, a kind of have low on-resistance and high withstand voltage multichannel LDMOS are provided, the complicated defective of technology that has simultaneously low on-resistance and high withstand voltage multichannel LDMOS at preparation in the prior art provides a kind of processing step simple and to the preparation method of the less demanding multichannel LDMOS of process equipment.
The technical solution adopted for the present invention to solve the technical problems is:
A kind of multichannel LDMOS is provided, comprise the source region that is arranged in substrate, the drain region, gate dielectric layer, field oxide, medium before the metal, the drift region, substrate trap contact zone, the substrate trap, source metal and drain metal, between described substrate trap and described drift region continuously every, the conduction type of described drift region is identical with the channel type of described multichannel LDMOS, the conduction type of described substrate trap is opposite with the channel type of described multichannel LDMOS, also comprise the buried regions strip array, described buried regions strip array comprises that at least one horizontal row is to a plurality of first buried regions bars of arranging, described buried regions strip array is positioned at described field oxide below, surrounded and described field oxide one segment distance of distance by described drift region, the conduction type of the described first buried regions bar is opposite with the channel type of described multichannel LDMOS.
Among a kind of multichannel LDMOS of the present invention, comprise also being positioned under the described substrate trap and the buried regions that contacts with described substrate trap that described buried regions is identical with the conduction type of the described first buried regions bar.
Among a kind of multichannel LDMOS of the present invention, described buried regions strip array also comprises at least one row and the corresponding a plurality of second buried regions bars of described a plurality of first buried regions bar, described a plurality of first buried regions bars among every row and described a plurality of second buried regions bar interphase distribution, and the conductivity type opposite of described second buried regions bar and the described first buried regions bar.
Among a kind of multichannel LDMOS of the present invention, the conduction type of the raceway groove of described multichannel LDMOS is the n type, and the described first buried regions bar is the p type.
Among a kind of multichannel LDMOS of the present invention, the conduction type of the raceway groove of described multichannel LDMOS is the p type, and the described first buried regions bar is the n type.
The present invention also provides the preparation method of a kind of multichannel LDMOS, may further comprise the steps:
S1, form the drift region in substrate, the conduction type of described drift region is identical with the channel type of multichannel LDMOS to be formed;
S2, carry out the active area etching and carry out the silicon selective oxidation forming field oxide;
S3, in described drift region, form the buried regions strip array, described buried regions strip array comprises that at least one horizontal row is to a plurality of first buried regions bars of arranging, described buried regions strip array is positioned at described field oxide below and described field oxide one segment distance of distance, the conductivity type opposite of the raceway groove of the conduction type of the described first buried regions bar and described multichannel LDMOS;
S4, in described substrate, form the substrate trap, between described substrate trap and described drift region continuously every, and the conductivity type opposite of the raceway groove of the conduction type of described substrate trap and described multichannel LDMOS;
S5, formation gate dielectric layer, the part of described gate dielectric layer is above described substrate trap, and another part is above described drift region;
S6, ion inject substrate trap contact zone, source region and the drain region that forms;
S7, formation contact hole, deposit form the preceding medium of metal and metal is leaked in the source.
Among the preparation method of a kind of multichannel LDMOS of the present invention, among the step S3, also be included in the described substrate and form buried regions, described buried regions is positioned under the described substrate trap and with described substrate trap and contacts, and described buried regions is identical with the conduction type of the described first buried regions bar.
Among the preparation method of a kind of multichannel LDMOS of the present invention, described buried regions strip array also comprises at least one row and the corresponding a plurality of second buried regions bars of described a plurality of first buried regions bar, described a plurality of first buried regions bars among every row and described a plurality of second buried regions bar interphase distribution, and the conductivity type opposite of described second buried regions bar and the described first buried regions bar.
Among the preparation method of a kind of multichannel LDMOS of the present invention, comprise and adopt the method for energetic ion injection and high temperature knot to inject p type impurity and/or n type impurity.
Among the preparation method of a kind of multichannel LDMOS of the present invention, among the step S3, comprise injection at least once described p type impurity and/or n type impurity, and each injection energy is different so that form many rows buried regions bar of different depth, every inject once correspondingly increases the knot time of described drift region and the implantation dosage of corresponding impurity more in step S2.
The beneficial effect of a kind of multichannel LDMOS of the present invention and preparation method thereof is: increased the conductive channel among the LDMOS by increasing the buried regions strip array, and then reduced the conduction resistance of LDMOS, improved the withstand voltage of LDMOS, and its preparation method have processing step simple, to advantages such as process equipment are less demanding.The high-voltage power integrated circuit that is made of this LDMOS device can be used in the multiple products such as consumer electronics, display driver.
Description of drawings
The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:
Fig. 1 is the structural representation of 2 times of resurf ldmos transistors of tradition;
Fig. 2 is the structural representation of binary channels ldmos transistor in the prior art;
Fig. 3 is the generalized section of high pressure multichannel ldmos transistor according to an embodiment of the invention;
Fig. 4 is the structural representation of high pressure multichannel ldmos transistor according to an embodiment of the invention;
Fig. 5 is the structural representation of high pressure multichannel ldmos transistor in accordance with another embodiment of the present invention;
Fig. 6 is the structural representation of high pressure multichannel ldmos transistor in accordance with another embodiment of the present invention;
Fig. 7-the 12nd, the generalized section of formation multichannel ldmos transistor under the BCD technology according to an embodiment of the invention;
Figure 13 is the preparation method's of multichannel ldmos transistor a flow chart under the BCD technology according to an embodiment of the invention;
Figure 14 utilizes three-dimensional artificial software silvaco multichannel ldmos transistor of the present invention to be carried out the simulation architecture figure of emulation;
Figure 15 is the withstand voltage curve chart of 2 times of resurf ldmos transistors of tradition, 2.5 times of resurf binary channels LDMOS and multichannel ldmos transistor of the present invention;
Figure 16 is the IV characteristic Simulation figure of 2 times of resurf ldmos transistors of tradition, 2.5 times of resurf binary channels LDMOS and multichannel ldmos transistor of the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
Fig. 4 is the structural representation of high pressure multichannel ldmos transistor according to an embodiment of the invention, and Fig. 3 shows the generalized section of this embodiment.In the present embodiment, high pressure multichannel ldmos transistor is arranged in substrate 1, comprise drift region 2, substrate trap 7, substrate trap contact zone 4, source region 5, drain region 6, gate dielectric layer 10, source metal 8, drain metal 9, field oxide 11, the preceding medium 12 of metal and buried regions strip array, the buried regions strip array comprises that again a horizontal row is to a plurality of first buried regions bar 3A that arrange.In addition, the multichannel ldmos transistor can also comprise with the buried regions bar that comprises a plurality of first buried regions bar 3A and arranges corresponding buried regions 3B.2 of substrate trap 7 and drift regions continuously every, the conduction type of drift region 2 is identical with the channel type of multichannel LDMOS, the conduction type of substrate trap 7 is opposite with the channel type of multichannel LDMOS.Drain region 6 be positioned at drain metal 9 times, surrounded by drift region 2.Source region 5 and substrate trap contact zone 4 be in source metal side by side 8 times, surrounded by substrate trap 7.Gate dielectric layer 10 is on the gate oxide 11, and 9 of gate dielectric layer 10, source metal 8 and drain metal are isolated mutually by before-metal medium layer 12.The buried regions strip array is positioned at field oxide 11 belows, is surrounded by drift region 2 and distance field oxide layer 11 1 segment distances, and the conduction type of the first buried regions bar 3A is opposite with the channel type of multichannel LDMOS.Buried regions 3B is positioned at substrate trap 7 times and contacts with substrate trap 7, and buried regions 3B is identical with the conduction type of the first buried regions bar 3A.
The multichannel ldmos transistor can be the n-LDMOS transistor, also can be the p-LDMOS transistor.When the multichannel ldmos transistor was n-LDMOS, substrate 1 was the p type, and the first buried regions bar 3A is the p type, and drift region 2 is the n type, and substrate trap 7 is the p type, and source region 5 and drain region 6 are the n type, and substrate trap contact zone 4 is all the p type mutually with the conduction type of substrate trap 7.When the multichannel ldmos transistor was p-LDMOS, substrate 1 was the n type, and the first buried regions bar 3A is the n type, and drift region 2 is the p type, and substrate trap 7 is the n type, and source region 5 and drain region 6 are the p type, and substrate trap contact zone 4 is all the n type mutually with the conduction type of substrate trap 7.
Multichannel LDMOS provided by the invention is a kind of power device of transverse conductance, on the basis of channel structure shown in Figure 2, the buried regions trap has been made strip.The buried regions trap of list structure can be realized by domain, promptly buried regions trap 3 corresponding regions is done into strips the wide 0.5um-1.5um of bar, 0.5um-1.5um at interval on domain.Because the first buried regions bar 3A can exhaust simultaneously in X, Y, Z direction, has the stronger ability that exhausts, therefore form 3D resurf structure, this moment is because the buried regions trap has been vacated the drift region 2 of half after doing into strips, make that current channel structure more shown in Figure 3 is more, can have littler conducting resistance.Simultaneously, it is withstand voltage that the introducing of 7 times buried regions 3B of substrate trap can improve the ON state of LDMOS, makes it have bigger safety operation area.
Fig. 5 is the structural representation of high pressure multichannel ldmos transistor in accordance with another embodiment of the present invention.In the present embodiment, high pressure multichannel ldmos transistor is arranged in substrate 1, comprise drift region 2, substrate trap 7, substrate trap contact zone 4, source region 5, drain region 6, gate dielectric layer 10, source metal 8, drain metal 9, field oxide 11, the preceding medium 12 of metal and buried regions strip array, the buried regions strip array comprises N row buried regions bar row (N for arbitrarily more than or equal to 1 natural number) again, the a plurality of first buried regions bar 3A that laterally arrange are drawn together in the package of wherein every row's buried regions bar, and between each buried regions bar row certain intervals are arranged.In addition, the multichannel ldmos transistor can also comprise with each buried regions bar and arranges corresponding buried regions 3B.2 of substrate trap 7 and drift regions continuously every, the conduction type of drift region 2 is identical with the channel type of multichannel LDMOS, the conduction type of substrate trap 7 is opposite with the channel type of multichannel LDMOS.Drain region 6 be positioned at drain metal 9 times, surrounded by drift region 2.Source region 5 and substrate trap contact zone 4 be in source metal side by side 8 times, surrounded by substrate trap 7.Gate dielectric layer 10 is on the gate oxide 11, and 9 of gate dielectric layer 10, source metal 8 and drain metal are isolated mutually by before-metal medium layer 12.The buried regions strip array is positioned at field oxide 11 belows, is surrounded by drift region 2 and distance field oxide layer 11 1 segment distances, and the conduction type of the first buried regions bar 3A is opposite with the channel type of multichannel LDMOS.Buried regions 3B is positioned at substrate trap 7 times and contacts with substrate trap 7, and buried regions 3B is identical with the conduction type of the first buried regions bar 3A.
The multichannel ldmos transistor can be the n-LDMOS transistor, also can be the p-LDMOS transistor.When the multichannel ldmos transistor was n-LDMOS, substrate 1 was the p type, and the first buried regions bar 3A is the p type, and drift region 2 is the n type, and substrate trap 7 is the p type, and source region 5 and drain region 6 are the n type, and substrate trap contact zone 4 is all the p type mutually with the conduction type of substrate trap 7.When the multichannel ldmos transistor was p-LDMOS, substrate 1 was the n type, and the first buried regions bar 3A is the n type, and drift region 2 is the p type, and substrate trap 7 is the n type, and source region 5 and drain region 6 are the p type, and substrate trap contact zone 4 is all the n type mutually with the conduction type of substrate trap 7.
Multichannel LDMOS provided by the invention is a kind of power device of transverse conductance, on the basis of multi-channel structure shown in Figure 4, with vertically expansion of buried regions bar row, formed more conductive channel, can have littler conducting resistance, principle according to this configuration can produce the ldmos transistor of vertical N passage in theory, and its conducting resistance can infinitely reduce.
Fig. 6 is the structural representation of high pressure multichannel ldmos transistor in accordance with another embodiment of the present invention.In the present embodiment, high pressure multichannel ldmos transistor is arranged in substrate 1, comprise drift region 2, substrate trap 7, substrate trap contact zone 4, source region 5, drain region 6, gate dielectric layer 10, source metal 8, drain metal 9, field oxide 11, the preceding medium 12 of metal and buried regions strip array, the buried regions strip array comprises at least one buried regions bar row again, and a plurality of first buried regions bar 3A and a plurality of second buried regions bar, the 3 ' A that laterally arranges drawn together in each buried regions bar package.In addition, the multichannel ldmos transistor can also comprise with the buried regions bar and arranges corresponding buried regions 3B.2 of substrate trap 7 and drift regions continuously every, the conduction type of drift region 2 is identical with the channel type of multichannel LDMOS, the conduction type of substrate trap 7 is opposite with the channel type of multichannel LDMOS.Drain region 6 be positioned at drain metal 9 times, surrounded by drift region 2.Source region 5 and substrate trap contact zone 4 be in source metal side by side 8 times, surrounded by substrate trap 7.Gate dielectric layer 10 is on the gate oxide 11, and 9 of gate dielectric layer 10, source metal 8 and drain metal are isolated mutually by before-metal medium layer 12.The buried regions strip array is positioned at field oxide 11 belows, is surrounded by drift region 2 and distance field oxide layer 11 1 segment distances.In the buried regions strip array, among each buried regions bar row, each first buried regions bar 3A and each the second buried regions bar, 3 ' A interphase distribution, and the conduction type of the first buried regions bar 3A is opposite with the channel type of multichannel LDMOS, and the conductivity type opposite of the second buried regions bar, the 3 ' A and the first buried regions bar 3A.Although only show row's buried regions bar row among Fig. 6, this is for the purpose of simplifying the description, and is not used in restriction the present invention, can comprise the buried regions strip array of any appropriate level in an embodiment of the present invention.In addition, buried regions 3B is positioned at substrate trap 7 times and contacts with substrate trap 7, and buried regions 3B is identical with the conduction type of the first buried regions bar 3A.
The multichannel ldmos transistor can be the n-LDMOS transistor, also can be the p-LDMOS transistor.When the multichannel ldmos transistor was n-LDMOS, substrate 1 was the p type, and the first buried regions bar 3A is the p type, the second buried regions bar, 3 ' A is the n type, and drift region 2 is the n type, and substrate trap 7 is the p type, source region 5 and drain region 6 are the n type, and substrate trap contact zone 4 is all the p type mutually with the conduction type of substrate trap 7.When the multichannel ldmos transistor was p-LDMOS, substrate 1 was the n type, and the first buried regions bar 3A is the n type, the second buried regions bar, 3 ' A is the p type, and drift region 2 is the p type, and substrate trap 7 is the n type, source region 5 and drain region 6 are the p type, and substrate trap contact zone 4 is all the n type mutually with the conduction type of substrate trap 7.
Multichannel LDMOS provided by the invention is a kind of power device of transverse conductance, on the basis of the multi-channel structure shown in the Figure 4 and 5, increased by the second buried regions bar, 3 ' A, and the conductivity type opposite of the second buried regions bar, the 3 ' A and the first buried regions bar 3A, thereby satisfying under the identical withstand voltage condition, the multichannel LDMOS of structure shown in Figure 6 can have than Fig. 4 and the littler conducting resistance of structure shown in Figure 5.
Figure 13 is the preparation method's of multichannel ldmos transistor a flow chart under the BCD technology according to an embodiment of the invention.Flow chart shown in Figure 10 is described with reference to figure 5-12.In the embodiment shown in Fig. 5-13, the preparation method of multichannel ldmos transistor starts from step S1 under the BCD technology.
In step S1, as shown in Figure 7, adopt energetic ion to inject and the method for high temperature knot in substrate 1 formation drift region 2, the conduction type of drift region 2 is identical with the channel type of multichannel LDMOS to be formed.With n-LDMOS is example, adopts p type substrate 1, and the resistivity of p type substrate 1 is about the 50-150 ohmcm, and n type impurity implantation dosage is about 2E12cm-2-5E12cm-2, and the knot temperature is about 1200 degree, and the knot time was about 200 minutes-400 minutes.
In step S2, as shown in Figure 8, carry out the active area etching and carry out the silicon selective oxidation forming field oxide 11.The thickness of field oxide 11 is about 5000A-7000A, and field oxide 11 can significantly reduce the surface field of multichannel ldmos transistor.
In step S3, as shown in Figure 9, the method that adopts the energetic ion injection is at the 2 formation buried regions strip arrays in the drift region, the buried regions strip array comprises that at least one horizontal row is to a plurality of first buried regions bar 3A that arrange, the buried regions strip array is positioned at field oxide 11 belows and distance field oxide layer 11 1 segment distances, the conductivity type opposite of the conduction type of the first buried regions bar 3A and the raceway groove of multichannel LDMOS.The buried regions trap of list structure can be realized by domain, promptly buried regions trap 3 corresponding regions is done into strips the wide 0.5um-1.5um of bar, 0.5um-1.5um at interval on domain.With n-LDMOS is example, can inject p type impurity, and this p type impurity can be boron, and implantation dosage is about 1E12cm-2-4E12cm-2, injects energy and is about 900KeV-1500KeV.In addition, can also form buried regions 3B, buried regions 3B is positioned at substrate trap 7 times and contacts with substrate trap 7, and buried regions 3B is identical with the conduction type of the first buried regions bar 3A.The buried regions 3B and the first buried regions bar 3A can form simultaneously, also can form step by step.
In another embodiment of the present invention, when forming multichannel ldmos transistor as shown in Figure 5, need inject by the repeatedly ion that difference is injected energy and realize, the implantation dosage that also will suitably increase knot time of drift region 2 and drift region 2 corresponding impurity simultaneously is so that drift region 2 can surround whole buried regions strip arrays.With n-LDMOS is example, every increase by one row's buried regions bar, and the n type impurity implantation dosage of corresponding n type drift region 2 promotes 1E12cm-2.
In another embodiment of the present invention, when forming multichannel ldmos transistor as shown in Figure 6, also need to inject another kind of impurity with the conductivity type opposite of the impurity that forms the first buried regions bar 3A to form the second buried regions bar, 3 ' A.With n-LDMOS is example, also need to inject for example phosphorus of n type impurity, implantation dosage is about 2E12-4E12, injects energy 900Kev-1500Kev, and the implantation dosage of phosphorus is corresponding so that these two kinds of buried regions bar interphase distributions with implantation dosage and injection energy of this row's boron with the injection energy among every row.
In step S4, as shown in figure 10, the method that adopts energetic ion to inject forms substrate trap 7 at substrate 1,2 of substrate trap 7 and drift regions continuously every, and the conduction type of substrate trap 7 is opposite with the channel type of multichannel LDMOS.With n-LDMOS is example, injects the p type substrate trap 7 that p type impurity forms LDMOS in p type substrate 1, and p type impurity dose can be 4E12cm-2-7E12cm-2.
In step S5, as shown in figure 10, form gate dielectric layer 10, the part of gate dielectric layer 10 is above substrate trap 7, and another part is above drift region 2, and the thickness of gate dielectric layer is about 30nm～60nm.
In step S6, as shown in figure 11, ion injects and forms substrate trap contact zone 4, source region 5 and drain region 6.With n-LDMOS is example, injects p type impurity and forms p type substrate trap contact zone 4, injects n type impurity and forms n+ source region 5 and n+ drain region 6, injects the order of p type impurity and n type impurity and can put upside down.Wherein p type impurity can be boron, and implantation dosage is about 1E15cm-2-5E15cm-2, and n type impurity can be phosphorus, and implantation dosage is about 1E15cm-2-5E15cm-2.
In step S7, as shown in figure 12, form contact hole, the preceding medium 12 of deposit formation metal and metallization and form source metal 8 and drain metal 9.Wherein, the thickness of medium is about 7000A-15000A before the metal.Metal has very crucial effect as the field plate of source end and drain terminal to device withstand voltage.
Be to be understood that, though above relate to some technological parameters, for example impurity implantation dosage, knot temperature, knot time etc., but for these examples just to purpose of explanation, and be not used in restriction the present invention, in various embodiment of the present invention, can be according to concrete process environments, process materials, process equipment etc. to the adjustment of making amendment of these technological parameters, and do not break away from the spirit and scope of the present invention.
Figure 14 utilizes three-dimensional artificial software silvaco multichannel ldmos transistor of the present invention to be carried out the simulation architecture figure of emulation.Figure 15 is the withstand voltage curve chart of 2 times of resurf ldmos transistors of tradition, 2.5 times of resurf binary channels LDMOS and multichannel ldmos transistor of the present invention.Figure 16 is the IV characteristic Simulation figure of 2 times of resurf ldmos transistors of tradition, 2.5 times of resurf binary channels LDMOS and multichannel ldmos transistor of the present invention.From Figure 15 and 16 as can be seen, the traditional 2 times of resurf ldmos transistors of multichannel ldmos transistor of the present invention and 2.5 times of resurf binary channels LDMOS have the withstand voltage of lower conducting resistance and Geng Gao.
The invention provides a kind of can with integrated multichannel LDMOS of high pressure BCD technology and preparation method thereof.The present invention has increased the buried regions strip array by the energetic ion injection mode, has realized multichannel LDMOS.Owing to increased conductive channel, this structure conduction resistance of 2 times of resurf LDMOS of tradition has a clear superiority in, and also has certain advantage owing to buried structure is done into strips than traditional double passage LDMOS.Because substrate trap 71 places introduce buried regions 3B, make traditional 2 times of resurf LDMOS of the present invention and common double passage LDMOS that certain advantage also be arranged on ON state is withstand voltage simultaneously.The more important thing is to have provided the concrete technological process that realizes structure of the present invention, this flow process can be integrated with high pressure BCD technology, has been used for experiment at present.Characteristics such as high-voltage semi-conductor device of the present invention has high withstand voltage (greater than 600v), low conduction resistance, switching speed is fast, reliability is high, integration is good, wherein conduction resistance has descended about 42% than traditional double resurfLDMOS, and the traditional double passage LDMOS structure that proposes than PI company has descended about 15%; Its manufacture method have processing step comparatively simple, less demanding to process equipment, have characteristics such as higher integration and reliability.
In addition, multi-channel structure provided by the present invention is compared with high voltage power device of the same type, has on device architecture following characteristics are arranged: the first, and less conduction resistance, less chip area; The second, high withstand voltage (greater than 600V) and switching speed are fast, are fit to low frequency, intermediate frequency and frequency applications; The 3rd, have the safety operation area of broad, characteristics such as reliability height; The 4th, comparatively simple on the manufacturing process, be easy to integratedly, this cover processing procedure is being applied to a cover high pressure BCD technology and Related product exploitation, and obtains initial success, has good integration and compatibility.The high-voltage power integrated circuit that is made of this device can be used in the multiple products such as consumer electronics, display driver.
Though the present invention describes by specific embodiment, it will be appreciated by those skilled in the art that, without departing from the present invention, can also carry out various conversion and be equal to alternative the present invention.In addition, at particular condition or material, can make various modifications to the present invention, and not depart from the scope of the present invention.Therefore, the present invention is not limited to disclosed specific embodiment, and should comprise the whole execution modes that fall in the claim scope of the present invention.
Claims (10)
1. multichannel LDMOS, comprise the source region (5) that is arranged in substrate (1), drain region (6), gate dielectric layer (10), field oxide (11), medium (12) before the metal, drift region (2), substrate trap contact zone (4), substrate trap (7), source metal (8) and drain metal (9), between described substrate trap (7) and described drift region (2) continuously every, the conduction type of described drift region (2) is identical with the channel type of described multichannel LDMOS, the conduction type of described substrate trap (7) is opposite with the channel type of described multichannel LDMOS, it is characterized in that, also comprise the buried regions strip array, described buried regions strip array comprises that at least one horizontal row is to a plurality of first buried regions bars (3A) of arranging, described buried regions strip array is positioned at described field oxide (11) below, surrounded and described field oxide (11) one segment distances of distance by described drift region (2), the conduction type of the described first buried regions bar (3A) is opposite with the channel type of described multichannel LDMOS.
2. multichannel LDMOS according to claim 1 is characterized in that, also comprises being positioned under the described substrate trap (7) and the buried regions (3B) that contacts with described substrate trap (7), and described buried regions (3B) is identical with the conduction type of the described first buried regions bar (3A).
3. multichannel LDMOS according to claim 1 and 2, it is characterized in that, described buried regions strip array also comprises at least one row and described a plurality of corresponding a plurality of second buried regions bars of the first buried regions bar (3A) (3 ' A), described a plurality of first buried regions bars (3A) among every row and described a plurality of second buried regions bars (3 ' A) interphase distribution, and the conductivity type opposite of described second buried regions bar (3 ' A) and the described first buried regions bar (3A).
4. multichannel LDMOS according to claim 3 is characterized in that, the conduction type of the raceway groove of described multichannel LDMOS is the n type, and the described first buried regions bar (3A) is the p type.
5. multichannel LDMOS according to claim 3 is characterized in that, the conduction type of the raceway groove of described multichannel LDMOS is the p type, and the described first buried regions bar (3A) is the n type.
6. the preparation method of a multichannel LDMOS is characterized in that, may further comprise the steps:
S1, form drift region (2) in substrate (1), the conduction type of described drift region (2) is identical with the channel type of multichannel LDMOS to be formed;
S2, carry out the active area etching and carry out the silicon selective oxidation forming field oxide (11);
S3, in described drift region (2), form the buried regions strip array, described buried regions strip array comprises that at least one horizontal row is to a plurality of first buried regions bars (3A) of arranging, described buried regions strip array is positioned at described field oxide (11) below and described field oxide (11) one segment distances of distance, the conductivity type opposite of the conduction type of the described first buried regions bar (3A) and the raceway groove of described multichannel LDMOS;
S4, in described substrate (1), form substrate trap (7), between described substrate trap (7) and described drift region (2) continuously every, and the conductivity type opposite of the raceway groove of the conduction type of described substrate trap (7) and described multichannel LDMOS;
S5, formation gate dielectric layer (10), the part of described gate dielectric layer (10) is in the top of described substrate trap (7), and another part is in the top of described drift region (2);
S6, ion inject substrate trap contact zone (4), source region (5) and drain region (6) that form;
S7, formation contact hole, deposit form the preceding medium (12) of metal and metal (8,9) is leaked in the source.
7. the preparation method of multichannel LDMOS according to claim 6, it is characterized in that, among the step S3, also be included in and form buried regions (3B) in the described substrate (1), described buried regions (3B) is positioned under the described substrate trap (7) and with described substrate trap (7) and contacts, and described buried regions (3B) is identical with the conduction type of the described first buried regions bar (3A).
8. according to the preparation method of claim 6 or 7 described multichannel LDMOS, it is characterized in that, described buried regions strip array also comprises at least one row and described a plurality of corresponding a plurality of second buried regions bars of the first buried regions bar (3A) (3 ' A), described a plurality of first buried regions bars (3A) among every row and described a plurality of second buried regions bars (3 ' A) interphase distribution, and the conductivity type opposite of described second buried regions bar (3 ' A) and the described first buried regions bar (3A).
9. the preparation method of multichannel LDMOS according to claim 8 is characterized in that, comprises adopting the method for energetic ion injection and high temperature knot to inject p type impurity and/or n type impurity.
10. the preparation method of multichannel LDMOS according to claim 9, it is characterized in that, among the step S3, comprise injection at least once described p type impurity and/or n type impurity, and each injection energy is different so that form many rows buried regions bar (3A and/or 3 ' A) of different depth, every inject once correspondingly increases the knot time of described drift region (2) and the implantation dosage of corresponding impurity more in step S2.
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| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN103811547A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Layout structure and method for reducing peak electric field of LDMOS device |
| CN104681610A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Nldmos device |
| CN109378340A (en) * | 2018-09-22 | 2019-02-22 | 天津大学 | A kind of double trap p-type LDMOS using more buried layer technologies |
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| CN117293192A (en) * | 2023-11-27 | 2023-12-26 | 北京智芯微电子科技有限公司 | Multi-channel semiconductor device, process, chip and electronic equipment |
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| CN103091533A (en) * | 2011-11-03 | 2013-05-08 | 上海华虹Nec电子有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN103091533B (en) * | 2011-11-03 | 2014-12-10 | 上海华虹宏力半导体制造有限公司 | Current sampling circuit achieved by laterally diffused metal oxide semiconductor (LDMOS) devices |
| CN102790092A (en) * | 2012-08-24 | 2012-11-21 | 电子科技大学 | Transverse high-voltage DMOS (double-diffusion metal oxide semiconductor) device |
| CN103811547A (en) * | 2012-11-15 | 2014-05-21 | 上海华虹宏力半导体制造有限公司 | Layout structure and method for reducing peak electric field of LDMOS device |
| CN104681610A (en) * | 2013-12-03 | 2015-06-03 | 上海华虹宏力半导体制造有限公司 | Nldmos device |
| CN104681610B (en) * | 2013-12-03 | 2017-08-08 | 上海华虹宏力半导体制造有限公司 | Nldmos device |
| CN109378340A (en) * | 2018-09-22 | 2019-02-22 | 天津大学 | A kind of double trap p-type LDMOS using more buried layer technologies |
| CN112530805A (en) * | 2019-09-19 | 2021-03-19 | 无锡华润上华科技有限公司 | Transverse double-diffusion metal oxide semiconductor device, manufacturing method and electronic device |
| CN112530805B (en) * | 2019-09-19 | 2022-04-05 | 无锡华润上华科技有限公司 | Transverse double-diffusion metal oxide semiconductor device, manufacturing method and electronic device |
| CN111370467A (en) * | 2020-03-30 | 2020-07-03 | 电子科技大学 | Semiconductor device and manufacturing method thereof |
| CN111370467B (en) * | 2020-03-30 | 2023-09-29 | 电子科技大学 | Semiconductor device and manufacturing method thereof |
| CN111933687A (en) * | 2020-07-07 | 2020-11-13 | 电子科技大学 | Lateral power device with high safety working area |
| CN111968974A (en) * | 2020-08-28 | 2020-11-20 | 电子科技大学 | Integrated power semiconductor device and manufacturing method |
| CN117293192A (en) * | 2023-11-27 | 2023-12-26 | 北京智芯微电子科技有限公司 | Multi-channel semiconductor device, process, chip and electronic equipment |
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