CN109378340A - A kind of double trap p-type LDMOS using more buried layer technologies - Google Patents
A kind of double trap p-type LDMOS using more buried layer technologies Download PDFInfo
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- CN109378340A CN109378340A CN201811111236.7A CN201811111236A CN109378340A CN 109378340 A CN109378340 A CN 109378340A CN 201811111236 A CN201811111236 A CN 201811111236A CN 109378340 A CN109378340 A CN 109378340A
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- 238000005516 engineering process Methods 0.000 title claims abstract description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052751 metal Inorganic materials 0.000 claims abstract description 24
- 239000002184 metal Substances 0.000 claims abstract description 24
- 239000000758 substrate Substances 0.000 claims abstract description 14
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 13
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 12
- 239000010931 gold Substances 0.000 claims abstract description 12
- 229910052737 gold Inorganic materials 0.000 claims abstract description 12
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims abstract description 12
- 229910052721 tungsten Inorganic materials 0.000 claims abstract description 12
- 239000010937 tungsten Substances 0.000 claims abstract description 12
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 9
- 239000010980 sapphire Substances 0.000 claims abstract description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 8
- 229920005591 polysilicon Polymers 0.000 claims abstract description 8
- 238000000926 separation method Methods 0.000 claims abstract description 8
- 238000002955 isolation Methods 0.000 claims abstract description 5
- 150000002500 ions Chemical class 0.000 claims description 9
- -1 phosphonium ions Chemical class 0.000 claims description 9
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 3
- 229910052796 boron Inorganic materials 0.000 claims description 3
- 229910052698 phosphorus Inorganic materials 0.000 claims description 3
- 239000011574 phosphorus Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 8
- 238000013461 design Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000011982 device technology Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 102000004129 N-Type Calcium Channels Human genes 0.000 description 1
- 108090000699 N-Type Calcium Channels Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
Abstract
The invention discloses a kind of double trap p-type LDMOS using more buried layer technologies, including Sapphire Substrate layer, Sapphire Substrate layer upper surface is depth n well layer, different depth n well layer are separated by silica deep trench isolation, the depth n well layer upper surface is equipped with high voltage p-well layer, the high voltage p-well layer is interior respectively from top to bottom to be equipped with N-shaped buried layer and p-type buried layer, the high voltage p-well layer passes through drain electrode p- buffer strip, p+ doped layer and tungsten metal throuth hole are connected with drain metal gold electrode, n well layer is equipped on the left of the high voltage p-well layer, n well layer is connected by tungsten metal throuth hole with source metal gold electrode by n+ doped layer with p+ doped layer simultaneously, high voltage p-well layer upper surface is laid with silica separation layer and polysilicon gate respectively from the bottom to top, the polysilicon gate prolongs Shen to n by silica separation layer upper surface Well layer upper surface.The pressure voltage of device can be increased to 700V or more on the basis of not increasing device size by the present invention, and is hindered small than conducting and will not be weakened other performance parameters.
Description
Technical field
The present invention relates to semiconductor power device technology fields, and in particular to a kind of double trap p-types using more buried layer technologies
LDMOS (high pressure transverse diffusion metal oxide semiconductor field effect pipe).
Background technique
P-type LDMOS is easy to since drain electrode, source electrode and grid are all in chip surface through inside connection and low-voltage signal electricity
The advantages that road integrates becomes the key for realizing the technology of power integrated circuit and high voltage integrated circuit.But its substrate auxiliary consumption
Effect exacerbates the intrinsic charge imbalance problem of device to the greatest extent, therefore the development of p-type LDMOS is slow compared with low voltage field effect transistor
Slowly.Therefore the p-type LDMOS that development can eliminate substrate-assisted depletion effect will become grinding for semiconductor power device technology field
Study carefully hot spot.
Currently, in VLSI designs, in order to constantly improve integrated level and device speed, it is necessary to device
The characteristic size of part further decreases.To prevent the breakdown of p-channel transistor in single trap technique that must be continuously increased n-type silicon substrate
Doping concentration, which results in the source and drain junction capacity of excessive n-channel, are unfavorable for the design of high speed circuit.With traditional single trap technique
Technology is compared, and twin well process will form p-type in two kinds of traps respectively and n-type channel, this design method bring the advantage that two
The impurity concentration energy independent control of trap, so as to avoid the doping in excessively, bring is adversely affected, therefore twin well process is answered
Design for p type LDMOS has obtained extensive research.
In order to improve the pressure voltage of device, conventional high-tension device is realized by increasing the length of drift region.In this way
The problem of bringing is exactly to increase the ratio conducting resistance of device, influences the performance of device.Therefore it finds one kind and is not increasing drift
Section length, while the method that the pressure voltage of device can be improved again is to study the main direction of studying of high tension apparatus.However it buries more
Layer is as a kind of emerging semiconductor processing technology, because its technique manufacturing method is simple, and becomes resolver part pressure resistance bottleneck
Preferred manner.
Summary of the invention
In order to solve the problems in the existing technology, the present invention provides a kind of double trap p-types using more buried layer technologies
LDMOS solves the problems, such as that the pressure voltage of p-type LDMOS in the prior art is low, higher than conducting resistance.
The technical scheme is that a kind of double trap p-type LDMOS using more buried layer technologies, including Sapphire Substrate layer,
Sapphire Substrate layer upper surface is depth n well layer, and different depth n well layer are separated by silica deep trench isolation, the depth n well layer
Upper surface is equipped with high voltage p-well layer, and the high voltage p-well layer is interior respectively from top to bottom to be equipped with N-shaped buried layer and p-type buried layer, the high pressure p
Well layer is connected by drain electrode p- buffer strip, p+ doped layer and tungsten metal throuth hole with drain metal gold electrode, the high pressure p well layer
Left side is equipped with n well layer, and n well layer is by n+ doped layer with p+ doped layer simultaneously by tungsten metal throuth hole and source metal gold electrode phase
Even, high voltage p-well layer upper surface is laid with silica separation layer and polysilicon gate, the polysilicon gate respectively from the bottom to top
Pole Shen is prolonged to n well layer upper surface by silica separation layer upper surface.
The depth n well layer uses ion implanting, injects a large amount of phosphonium ions and is formed.
The N-shaped buried layer uses ion implanting, injects a large amount of phosphonium ions and is formed.
The n well layer and high voltage p-well layer are injected separately into phosphorus using ion implanting and boron ion is formed.
The invention has the benefit that the 1, present invention proposes a kind of double trap p-type LDMOS using more buried layer technologies, it can be with
The pressure voltage of device is increased to 700V or more on the basis of not increasing device size, and hinders small than conducting and will not weaken
Other performance parameters；
2, the present invention can be directly used for high voltage integrated circuit design, and can be used as power-ourput device use；
3, the present invention utilizes TRIPLE RESURF LDMOS technology, in the feasibility in view of cost and technology
The performance of device is set to reach best, power consumption is preferably minimized.
Detailed description of the invention
A kind of double trap p-type LDMOS structure schematic diagrames using more buried layer technologies of Fig. 1 present invention；
In figure: 1. Sapphire Substrates；2. depth n well layer；3.n well layer；4. high voltage p-well layer；5.n type buried layer；6.p type buried layer；
7. drain p- buffer strip；8. the first p+ doped layer；9. the first tungsten metal throuth hole；10. drain metal gold electrode；11. the 2nd p+ mixes
Diamicton；12.n+ doped layer；13. the second tungsten metal throuth hole；14. source metal gold electrode；15. silica separation layer；More than 16.
Polysilicon gate；17. third tungsten metal throuth hole；18. grid metal gold electrode；19. silica deep trench isolation.
Specific embodiment
The present invention is described in further detail below in conjunction with the accompanying drawings.
A kind of double trap p-type LDMOS using more buried layer technologies of the invention as shown in Figure 1, include Sapphire Substrate layer
1,1 upper surface of Sapphire Substrate layer is laid with depth n well layer 2, and deep n well layer 2 uses ion implanting, injects a large amount of phosphonium ion shape
At being respectively arranged on the left side and the right side n well layer 3 and high voltage p-well layer 4 in the depth n well layer 2, wherein include in the high voltage p-well layer 4
N-shaped buried layer 5, p-type buried layer 6, drain electrode p- buffer strip 7 and the first p+ doped layer 8, the N-shaped buried layer 5 use ion implanting phosphonium ion
It is formed, the n well layer 3 and high voltage p-well layer 4 are to be injected separately into phosphorus using ion implanting and boron ion is formed, the high voltage p-well layer
4 are connected by drain electrode p- buffer strip 7, the first p+ doped layer 8 and the first tungsten metal throuth hole 9 with drain metal gold electrode 10.The n
Include the 2nd p+ doped layer 11 and n+ doped layer 12 in well layer, and passes through the 2nd p+ doped layer 11, n+ doped layer 12 and the second tungsten
Metal throuth hole 13 is connected with source metal gold electrode 14, and 3 upper surface of high voltage p-well layer 4 and n well layer is spread respectively from the bottom to top
If silica separation layer 15 and polysilicon gate 16 simultaneously pass through third tungsten metal throuth hole 17 and grid metal gold electrode 18, different devices
Part is isolated by silica deep trench isolation 19.
A kind of double trap p-type LDMOS using more buried layer technologies, gate breakdown voltage involved in this example reach at least
700V, unit length are less than 80m Ω/mm, gate capacitance per unit area about 2fF/um than conducting2, threshold voltage is not higher than 3V, work
Temperature is -40 DEG C~125 DEG C.
This example n-type substrate it is raw (on) realize, but during application invention, can be realized in p-substrate system
Similar structure, although can be done to these examples in the case where basic principle and spirit according to invention has been illustrated and described
(work) goes out to change, and the scope of the present invention is limited by claims and its equivalent.
Claims (4)
1. a kind of double trap p-type LDMOS using more buried layer technologies, which is characterized in that including Sapphire Substrate layer, the sapphire
Substrate layer upper surface is depth n well layer, and different depth n well layer are separated by silica deep trench isolation, and the depth n well layer upper surface is equipped with
High voltage p-well layer, the high voltage p-well layer is interior respectively from top to bottom to be equipped with N-shaped buried layer and p-type buried layer, and the high voltage p-well layer passes through leakage
Pole p- buffer strip, p+ doped layer and tungsten metal throuth hole are connected with drain metal gold electrode, and n trap is equipped on the left of the high voltage p-well layer
Layer, n well layer are connected by tungsten metal throuth hole with source metal gold electrode by n+ doped layer with p+ doped layer simultaneously, the high pressure p
Well layer upper surface is laid with silica separation layer and polysilicon gate respectively from the bottom to top, and the polysilicon gate is by silica
Prolong Shen to n well layer upper surface in separation layer upper surface.
2. using double trap p-type LDMOS of more buried layer technologies according to claim 1, which is characterized in that the depth n well layer is adopted
With ion implanting, injects a large amount of phosphonium ions and formed.
3. using double trap p-type LDMOS of more buried layer technologies according to claim 1, which is characterized in that the N-shaped buried layer is adopted
With ion implanting, injects a large amount of phosphonium ions and formed.
4. using double trap p-type LDMOS of more buried layer technologies according to claim 1, which is characterized in that the n well layer and height
Pressure p well layer is injected separately into phosphorus using ion implanting and boron ion is formed.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201811111236.7A CN109378340A (en) | 2018-09-22 | 2018-09-22 | A kind of double trap p-type LDMOS using more buried layer technologies |
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| CN201811111236.7A CN109378340A (en) | 2018-09-22 | 2018-09-22 | A kind of double trap p-type LDMOS using more buried layer technologies |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112349764A (en) * | 2019-08-08 | 2021-02-09 | 天津大学 | RESURF LDMOS device with field limiting ring structure |
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| US20040178443A1 (en) * | 2003-03-10 | 2004-09-16 | Semiconductor Components Industries, Llc. | LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance |
| EP2071629A1 (en) * | 2007-12-14 | 2009-06-17 | Sanyo Electric Co., Ltd. | Lateral semiconductor device |
| CN102097484A (en) * | 2011-01-12 | 2011-06-15 | 深圳市联德合微电子有限公司 | Multichannel LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof |
| CN103904123A (en) * | 2014-04-10 | 2014-07-02 | 无锡友达电子有限公司 | Thin gate-oxide N-type LDMOS structure capable effectively reducing on-resistance |
| CN106158963A (en) * | 2015-02-18 | 2016-11-23 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of buried layer |
| CN108172623A (en) * | 2018-03-02 | 2018-06-15 | 成都信息工程大学 | A kind of high energy ion implantation buried layer binary channels LDMOS device and its manufacturing method |
-
2018
- 2018-09-22 CN CN201811111236.7A patent/CN109378340A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040178443A1 (en) * | 2003-03-10 | 2004-09-16 | Semiconductor Components Industries, Llc. | LDMOS transistor with enhanced termination region for high breakdown voltage with low on-resistance |
| EP2071629A1 (en) * | 2007-12-14 | 2009-06-17 | Sanyo Electric Co., Ltd. | Lateral semiconductor device |
| CN102097484A (en) * | 2011-01-12 | 2011-06-15 | 深圳市联德合微电子有限公司 | Multichannel LDMOS (laterally diffused metal oxide semiconductor) and preparation method thereof |
| CN103904123A (en) * | 2014-04-10 | 2014-07-02 | 无锡友达电子有限公司 | Thin gate-oxide N-type LDMOS structure capable effectively reducing on-resistance |
| CN106158963A (en) * | 2015-02-18 | 2016-11-23 | 旺宏电子股份有限公司 | There is semiconductor device and the manufacture method thereof of buried layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN112349764A (en) * | 2019-08-08 | 2021-02-09 | 天津大学 | RESURF LDMOS device with field limiting ring structure |
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