CN100421256C - SOI LIGBT device unit of integrated ESD diode - Google Patents
SOI LIGBT device unit of integrated ESD diode Download PDFInfo
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- CN100421256C CN100421256C CNB2006100508993A CN200610050899A CN100421256C CN 100421256 C CN100421256 C CN 100421256C CN B2006100508993 A CNB2006100508993 A CN B2006100508993A CN 200610050899 A CN200610050899 A CN 200610050899A CN 100421256 C CN100421256 C CN 100421256C
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 20
- 229920005591 polysilicon Polymers 0.000 claims abstract description 20
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000003139 buffering effect Effects 0.000 claims description 9
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical group [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052760 oxygen Inorganic materials 0.000 abstract description 2
- 239000001301 oxygen Substances 0.000 abstract description 2
- 230000005611 electricity Effects 0.000 abstract 1
- 238000002955 isolation Methods 0.000 abstract 1
- 230000003068 static effect Effects 0.000 abstract 1
- 238000000034 method Methods 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000010276 construction Methods 0.000 description 5
- 230000005684 electric field Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 150000002500 ions Chemical class 0.000 description 4
- 230000015556 catabolic process Effects 0.000 description 3
- 230000001413 cellular effect Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000000087 stabilizing effect Effects 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 230000002146 bilateral effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- -1 phosphonium ion Chemical class 0.000 description 1
- 230000002028 premature Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to an SOI LIGBT device unit of an integrated electrostatic damage resisting diode. A conventional SOI LIGBT results in electrostatic damage because high-voltage static electricity breaks down gates. The SOI LIGBT device unit of the present invention comprises a semiconductor substrate, a buried oxide layer, a drift region, a well region, a well contact region, a cathode region, a cathode region of an ESD resisting diode, a gate oxide layer, a buffer region, an anode region, an anode contact zone, an anode short dot region, a field oxygen region, a polysilicon gate electrode region, a gate isolation oxide layer, contact holes, metal electrode leading wires and interconnecting wires. The SOI LIGBT device unit of the present invention integrates the ESD resisting diode in the structure of the SOI LIGBT device unit, so that the ESD resisting diode has a strong ESD resisting capacity without needing to be externally connected with any device. The SOI LIGBT device unit of the present invention can obviously improve the self-protective performance of ESD resistance of an SOI LIGBT device, can decease and lower the volumes, the weights and the costs of various power electronic systems adopting the SOI LIGBT device, and can enhance the system reliability.
Description
Technical field
The present invention relates to SOI (semiconductor on insulator) LIGBT (lateral insulated gate bipolar transistor) device cell of a kind of integrated anti-ESD (electrostatic damage) diode.
Background technology
SOI LIGBT device is owing to its smaller volume, weight, higher working temperature and stronger anti-irradiation ability, lower cost and higher reliability have extensive use as contactless power electronic switching or analog line driver in technology such as intelligent electric power electronics, hot environment power electronics, space power electronics and vehicles power electronics.Conventional SOI LIGBT (as shown in Figure 1, with SOINLIGBT being example) is at the N of the SOI substrate that contains buried oxidation layer 1-1
-Drift region 1-2 goes up and forms field oxide; Adopt double ion to inject polysilicon autoregistration doping techniques at nearly cathodic region end and form short channel NMOSFET and polysilicon gate field plate, additional P
+Ion implantation doping realizes the contact of P trap; Draw gate metal electrode 1-4, N by polysilicon gate
+P
+Cathodic metal electrode 1-3 is drawn in the district; Inject the formation N type buffering area 1-6 that mixes at nearly anode tap by phosphonium ion, carry out shallow p type impurity injection at this doped region and form the anode region, and draw anode metal electrode drain electrode 1-5 and anode metal field plate.This SOI LIGBT device does not have integrated anti-ESD mechanism and function, because its intrinsic MOS structure causes the high-pressure electrostatic more than the kilovolt easily in encapsulation, transportation, assembling and use.If there is not the protection of voltage stabilizing didoe clamper, easily caused the device permanent failure by this high-pressure electrostatic puncture because gate oxide is very thin.It is this because high-pressure electrostatic causes that grid puncture the device permanent failure that is caused and are called electrostatic damage (ESD).In addition; compare with SOI LDMOS device; if there is not the anti-ESD diode protection of grid; because a large amount of minority carriers that SOI LIGBT anode injects to the drift region during on-state have changed the Potential Distributing of device inside at the device turn off process; cause that control gate zone electric field is concentrated, cause SOI LIGBT device premature failure easily.At present, business-like SOI LIGBT device in use needs external discrete voltage stabilizing didoe to be protected, and has increased volume, weight and cost, and has reduced reliability.
Summary of the invention
The object of the invention is at the deficiencies in the prior art, and a kind of structure with SOI LIGBT device cell of self-anti-esd protection function is provided, thereby significantly improves the anti-esd protection performance of SOI LIGBT device oneself.
The present invention includes Semiconductor substrate, buried oxidation layer, drift region, well region, trap contact zone, cathodic region, anti-ESD diode cathode district, gate oxide, buffering area, anode region, anode contact zone, anode in short circuit Dian Qu, an oxygen district, polysilicon gate polar region, polysilicon isolating oxide layer, contact hole and metal electrode lead-in wire and interconnection line.
Buried oxidation layer is isolated substrate and drift region fully.Placed in the middle with the trap contact zone in the well region of a side of drift region, the offside in next-door neighbour cathodic region is provided with anti-ESD diode cathode district at interval.The next-door neighbour is provided with the anode region below the anode contact zone in the buffering area of the opposite side of drift region.The anode in short circuit point district of running through this anode region up and down is set in anode region central authorities.Well region top between cathodic region and drift region is provided with the edge of gate oxide and covered cathode district and drift region.In the trap contact zone, cathodic region, anti-ESD diode cathode district, gate oxide, anode contact zone and anode in short circuit point district be provided with field oxide and cover each area edge with exterior domain.Neighbour at the extremely coupled field oxide of gate oxide partly is provided with polysilicon gate, adopt oxide layer to cover to realize each surface, district isolates and respectively in the cathodic region, anti-ESD diode cathode district, multi-crystal silicon area and anode contact zone distinguish upper surface with anode in short circuit point contact hole be set.On contact hole and part field oxide, metal electrode and interconnection line are set.
The present invention will be owing to will resist the ESD diode to be integrated among the SOI LIGBT device unit construction; make it need not external any device and just have stronger anti-ESD ability; can significantly improve the anti-esd protection performance of SOI LIGBT device oneself; reduce to adopt volume, weight and the cost of the various power electronic systems of this kind device, and improve system reliability.
Description of drawings
Fig. 1 is conventional SOI NLIGBT cellular construction schematic cross-section;
Fig. 2 is a cellular construction schematic cross-section of the present invention;
Fig. 3 is a cellular construction domain schematic diagram of the present invention;
Fig. 4 is the schematic diagram that concerns of silicon monolateral sudden change PN junction puncture voltage and low-doped side doping content.
Embodiment
As shown in Figures 2 and 3, the present invention includes semiconductor chip, buried oxidation layer 2 is divided into two parts up and down with semiconductor chip, and the bottom is a substrate 1, and top is N
- Top layer semiconductor 3.
At N
-One side of top layer semiconductor 3 is arranged to a P type well region 4, and as tagma and the anti-ESD diode anode district of MOSFET, opposite side is arranged to a N type buffering buffering area 9.
Central authorities at P type well region 4 are arranged to P
+Type P trap contact zone 5, one sides are arranged to a N
+ Type source region 6 is as negative electrode, and opposite side leaves certain distance a N is set
+The anti-ESD diode cathode of type district 7.Wherein at N
+ Type source region 6 and N
-P type well region 4 part tops between the top layer semiconductor 3 are provided with gate oxide 8 and cover N
+ Type source region 6 and N
-The edge of top layer semiconductor 3.
Among N type buffering buffering area 9, a p type anode district 10 is set, among p type anode district 10, carries out heavy doping and form P
+Type anode contact zone 11 is at P
+The central authorities of type anode contact zone 11 are arranged to one and penetrate P
+The N in type anode contact zone 11 and p type anode district 10
+Type anode in short circuit point 12.
At P
+Type P trap contact zone 5, N
+ Type source region 6, N
+The anti-ESD diode cathode of type district 7, oxide layer 8, P
+Type anode contact zone 11 and N
+Zone beyond the type anode in short circuit point 12 is arranged to thick field oxide layer 13 and is covered each area edge.
A part that polysilicon is set on gate oxide 8 and covers connected thick field oxide layer 13 is as polysilicon gate grid field plate region 14.Cover the polysilicon isolating oxide layer 15 of polysilicon gate grid field plate region 14.
At P
+Type anode contact zone 11 and N
+Type anode in short circuit point 12, N
+The anti-ESD diode cathode of type district 7, polysilicon gate grid field plate region 14 1 ends, N
+ Type source region 6 and P
+5 tops, type P trap contact zone are provided with contact porose area 16, are provided with metal electrode 17 in each contact porose area 16, respectively as P
+Type anode contact zone 11 and N
+The drain electrode of type anode in short circuit point 12, N
+The negative electrode in the anti-ESD diode cathode of type district 7, grid, the N of polysilicon gate grid field plate region 14
+ Type source region 6 and P
+The source electrode of type P trap contact zone 5, the grid and the N of polysilicon gate grid field plate region 14
+The negative electrode in the anti-ESD diode cathode of type district 7 connects by the interconnection line on the thick field oxide layer 13.
N among Fig. 2 and Fig. 3 and P are exchanged the SOIPLIGBT device unit construction that then can obtain the anti-ESD diode of integrated grid.
According to PN junction diode reverse breakdown principle, for monolateral sudden change N
+The P knot, its puncture voltage is approximate by the following formula decision,
In the formula, ε
rThe=11.9th, the dielectric constant of silicon, ε
0=8.854e-12F/m is a permittivity of vacuum, and q=1.602e-19C is an electronic charge, when the doping content of a low-doped side
During scope, the critical avalanche breakdown electric field strength of silicon is about E
Cr=(4-8) e5V/m.By adjusting N
ACan change B
VD, as shown in Figure 4.According to this figure as can be known, desire makes the puncture voltage of anti-ESD diode be not less than 10V, makes the P well region not be higher than 1.3e17cm in the doping content of this part usually
-3
For the gradual PN junction of linearity, its puncture voltage is approximate by the following formula decision,
By formula as seen, reduce maximum field intensity E by reducing linear gradual PN junction doping content gradient
mThereby, can improve its puncture voltage.Because linear gradual PN junction doping content gradient adopts linear gradual PN junction can significantly improve the puncture voltage of anti-ESD diode much smaller than the doping content gradient of single side abrupt junction, but can cause that process complexity increases, the technology incompatibility worsens.
And under the conditional likelihood situation, the puncture voltage of the bilateral sudden change PN junction of silicon is also apparently higher than the puncture voltage of the monolateral sudden change PN junction of silicon, and this is because thinning the dredging of the Electric Field Distribution of PN junction depletion region causes maximum field intensity E
mDue to the reduction.Promptly can consider at the N that carries out anti-ESD diode
+The N type that carries out low concentration before mixing in the district earlier in this district mixes and will obviously improve the puncture voltage of anti-ESD diode, but also can make process complexity that increase is arranged slightly.
The N of anti-ESD diode
+The district is mainly determined by several like this partial distances with the domain spacing of P trap ohmic contact regions: the horizontal maximum depletion width of (1) anti-ESD diode; (2) anti-ESD diode N
+The horizontal injection junction depth in district; (3) the horizontal injection junction depth of P trap ohmic contact regions; (4) technology controlling and process allowance.
The N of anti-ESD diode
+District's area mainly according to puncture spark electric current, puncture the moment heat radiation and the technology controlling and process allowance requires to calculate.According to the difference of SOI LIGBT element layout structure, an anti-ESD diode may be shared by adjacent two or more SOI LIGBT device cells, so carry out the N of anti-ESD diode
+Need consider the general requirement of shared SOI LIGBT device cell when distinguishing area design.And when an anti-ESD diode may be adjacent two or more SOILIGBT device cells when shared, the result of layout design will have obviously different with structure shown in Figure 3, and then difference is little to be in the device cell on border.
In mos semiconductor device and production of integrated circuits, the most high-quality thermal oxidation SiO that adopt of gate oxide
2, its critical breakdown electric field intensity is near 1e7V/cm, i.e. 1V/nm.Therefore, for 25～40nm thick grating oxide layer commonly used, it is withstand voltage between 25～40V.Integrated for the ease of intelligent power, when device was in running order, gate drive voltage was generally got 5V.So, be not subjected to ESD and can operate as normal under certain disturbed condition be being arranged in order to ensure SOI LIGBT device, requiring the withstand voltage of anti-ESD diode is more than 2 times of gate drive voltage at least, promptly greater than 10V.
If the employing single side abrupt junction is considered the technology controlling and process allowance, the doping content that can extrapolate the P trap according to formula (1) should not be higher than 1.3e17cm
-3In order to improve the anti-controllable silicon latch-up of SOI LIGBT device ability, must reduce the lateral resistance of P trap as far as possible, this requires the doping content of P trap high as far as possible.For solving this contradiction, we propose at first to utilize the channelling effect of ion injection, strengthen dark implanting impurity ion dosage when the P trap is carried out ion implantation doping in the certain limit of the central area of doping window; In the annealing progradation, make foreign ion distribute again within the specific limits then, can under the situation that influences P trap surface doping concentration hardly, suitably improve the doping content of P trap inside like this, thereby both can guarantee withstand voltage, the threshold voltage of metal-oxide-semiconductor of anti-ESD diode and the blocking-up requirement of withstand voltage of SOI LIGBT device, can improve the anti-breech lock ability of SOI LIGBT device again.
In addition, at the N of anti-ESD diode
+When mix in the district, can consider to adopt the oxide layer mask to inject the graded profiles that forms impurity, so just can obtain not mutated PN junction, thereby can reduce requirement P trap surface doping concentration, be that P trap surface doping concentration is higher can be than abrupt junction the time, therefore also can alleviate this contradiction.But can make process complexity that increase is arranged slightly like this.
Claims (1)
1. the SOI LIGBT device cell of integrated anti-ESD diode is characterized in that this device cell comprises semiconductor chip, and buried oxidation layer (2) is divided into two parts up and down with semiconductor chip, and the bottom is substrate (1), and top is N
-Top layer semiconductor (3);
Be arranged to a P type well region (4) in a side of top layer semiconductor (3), as tagma and the anti-ESD diode anode district of MOSFET, opposite side is arranged to a N type buffering area (9);
Central authorities at P type well region (4) are arranged to P
+A N is arranged in type P trap contact zone (5), a side
+Type source region (6) is as negative electrode, and opposite side is arranged to a N at interval
+The anti-ESD diode cathode of type district (7); Wherein at N
+Type source region (6) and N
-P type well region (4) part top between the top layer semiconductor (3) is provided with gate oxide (8), and gate oxide (8) covers N
+Type source region (6) and N
-The edge of top layer semiconductor (3);
A p type anode district (10) is set among N type buffering area (9), among p type anode district (10), carries out heavy doping and form P
+Type anode contact zone (11) is at P
+The central authorities of type anode contact zone (11) are provided with one and penetrate P
+The N of type anode contact zone (11) and p type anode district (10)
+Type anode in short circuit point (12);
At P
+Type P trap contact zone (5), N
+Type source region (6), N
+The anti-ESD diode cathode of type district (7), gate oxide (8), P
+Type anode contact zone (11) and N
+Type anode in short circuit point (12) zone in addition is provided with thick field oxide layer (13);
Polysilicon gate grid field plate region (14) is set on gate oxide (8) and covers the part of connected thick field oxide layer (13), cover the polysilicon isolating oxide layer (15) of polysilicon gate grid field plate region (14);
At P
+Type anode contact zone (11), N
+The anti-ESD diode cathode of type district (7), polysilicon gate grid field plate region (14) one ends, N
+Type source region (6) and P
+Top, type P trap contact zone (5) is provided with contact porose area (16), is provided with metal electrode (17) in each contact porose area (16), respectively as P
+Type anode contact zone (11) and N
+Drain electrode, the N of type anode in short circuit point (12)
+Grid, the N of the negative electrode in the anti-ESD diode cathode of type district (7), polysilicon gate grid field plate region (14)
+Type source region (6) and P
+The source electrode of type P trap contact zone (5), the grid and the N of polysilicon gate grid field plate region (14)
+The negative electrode in the anti-ESD diode cathode of type district (7) connects by the interconnection line on the thick field oxide layer (13).
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| CNB2006100508993A CN100421256C (en) | 2006-05-24 | 2006-05-24 | SOI LIGBT device unit of integrated ESD diode |
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|---|---|---|---|
| CNB2006100508993A CN100421256C (en) | 2006-05-24 | 2006-05-24 | SOI LIGBT device unit of integrated ESD diode |
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| CN1851923A CN1851923A (en) | 2006-10-25 |
| CN100421256C true CN100421256C (en) | 2008-09-24 |
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| CN1851923A (en) | 2006-10-25 |
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Assignee: Hangzhou Hangxin Electronic Industry Co., Ltd. Assignor: Hangzhou Electronic Science and Technology Univ Contract fulfillment period: 2008.10.16 to 2013.10.16 contract change Contract record no.: 2008330001719 Denomination of invention: SOI LIGBT device unit of integrated ESD diode Granted publication date: 20080924 License type: Exclusive license Record date: 2008.11.5 |
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