CN102136491B - Static discharge protection device for gate insulation dual junction transistor - Google Patents
Static discharge protection device for gate insulation dual junction transistor Download PDFInfo
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Abstract
The invention provides a static discharge protection device for a gate insulation dual junction transistor, which comprises a semiconductor substrate, a high-voltage N-type well arranged in the semiconductor substrate, a patterned insulation region arranged on the high-voltage N-type well and defining a first active region and a second active region, an N-type double diffusion region arranged in the first active region of the high-voltage N-type well, a P-type heavily-doped drain region arranged in the N-type double diffusion region, and a P-type body doped region arranged in the second active region of the high-voltage N-type well, wherein the N-type double diffusion region keeps a specific distance from the P-type body doped region to expose the high-voltage N-type well; a pair of neighboring N-type and P-type heavily-doped source regions are arranged in the P-type body doped region; moreover, a gate structure is arranged on the high-voltage N-type well; one end of the gate structure is connected with the N-type heavily-doped source region; and the other end of the gate structure extends on the patterned insulation region.
Description
The application is for dividing an application, and original application day is on November 03rd, 2008, and application number is 200810174775.5, and denomination of invention is: protecting component for electrostatic discharge of grid insulating double-junction transistor.
Technical field
The invention relates to a kind of electrostatic discharge protective device, particularly relevant for a kind of grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge.
Background technology
Tradition high voltage static discharge (Electrostatic Discharge, abbreviation ESD) protective element comprises lateral diffused metal oxide half-power transistor (LDMOS Power Transistor), metal oxide semitransistor (MOSFET), thyristor (SCR), double carrier transistor (BJT), diode (Diode) and an oxide transistor (Field Oxide Device, FOD).In high-pressure electrostatic discharge protection because its too high trigger voltage (trigger voltage) and the excessively low voltage (holding voltage) of holding, not to cause internal circuit to damage first to be exactly to cause latch-up (latch-up) to occur, so add extra drive circuit or go to make trigger voltage to reduce and make by modulation layout parameter (layout parameter) and hold the operating voltage (operation voltage) that voltage surpasses element, so just can be used as high-pressure electrostatic discharge-preventing protection element.
In traditional superhigh pressure element (ultra-HV device), often utilizing has silicon (SOI) substrate and relevant technique thereof on the insulating barrier, and isolation other element causes interelement ghost effect with minimizing because of operation with high pressure.Have silicon (SOI) substrate and relevant technique thereof that the heat radiation of ESD element is caused adverse influence on the insulating barrier and utilize, so industry is needed the heat dissipation problem of effectively processing the ESD element badly.Especially, in the technique of superhigh pressure element, the loose concentration of the control of trap (well) is all on the low side, so that relative impedance is also just higher, is unfavorable for the startup (uniform turn-on) of the more uniformity of ESD element.
Summary of the invention
In view of this; in order to overcome the shortcoming of above-mentioned background technology, thereby utilize grid insulating double-junction transistor (IGBT) element as protecting component for electrostatic discharge, and the layout of the drain region of improvement IGBT element; the more startup of uniformity is to promote the protection usefulness of ESD.
Another embodiment of the present invention provides a kind of grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge to comprise: the semiconductor substrate; One high pressure N-type trap is in this semiconductor base; The isolated area of one patterning is arranged on this high pressure N-type trap, defines one first active region and one second active region; One N-type double diffusion district is arranged in this first active region of this high pressure N-type trap; The dense doped drain region of one P-type is arranged in this N-type double diffusion district; One P-type body doped region is in this second active region of this high pressure N-type trap, and wherein this N-type double diffusion district and this P-type body doped region specific range of being separated by exposes this high pressure N-type trap; An a pair of adjacent N-type and the dense doping source region of a P-type are arranged in this P-type body doped region; And one grid structure on this high pressure N-type trap, one end and the dense doping source region of this N-type join, its other end extends on the isolated area of this patterning.
Further embodiment of this invention provides a kind of grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge to comprise: the semiconductor substrate; One high pressure N-type trap is in this semiconductor base; The isolated area of one patterning is arranged on this high pressure N-type trap, defines one first active region and one second active region; One P-type double diffusion district is arranged in this first active region of this high pressure N-type trap; The dense doped drain region of one P-type is arranged in this P-type double diffusion district; One P-type body doped region is in this second active region of this high pressure N-type trap, and wherein this P-type double diffusion district and this P-type body doped region specific range of being separated by exposes this high pressure N-type trap; An a pair of adjacent N-type and the dense doping source region of a P-type are arranged in this P-type body doped region; And one grid structure on this high pressure N-type trap, one end and the dense doping source region of this N-type join, its other end extends on the isolated area of this patterning.
Further embodiment of this invention provides a kind of grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge to comprise: the semiconductor substrate; One high pressure P-type trap is in this semiconductor base; One high pressure N-type trap is in this semiconductor base; The isolated area of one patterning is arranged on this semiconductor base, defines one first active region in this high pressure N-type trap and one second active region and one the 3rd active region in this high pressure P-type trap; The dense doped drain region of one P-type is arranged in this first active region; The dense doping source region of one N-type is arranged in this second active region, and the dense doping source region of a P-type is arranged in the 3rd active region; And one grid structure on this high pressure P-type trap, one end and the dense doping source region of this N-type join, its other end extends on the isolated area of this patterning.
Yet another embodiment of the invention provides a kind of grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge to comprise: the semiconductor substrate; The isolated area of one patterning is arranged on this semiconductor base, defines one first active region and one second active region; One grid structure is arranged on this first active region of this semiconductor base; One N-type double diffusion district is positioned at a side of this grid structure, and arranges in this first active region of this semiconductor base; One N-type trap is arranged in this N-type double diffusion district, and its bottom extends to this semiconductor base; The dense doped drain region of one P-type is arranged in this N-type trap; The dense doping source region of one N-type is arranged in this semiconductor base of opposite side of this grid structure; And the dense diffusion region of a P-type is arranged in this second active region of this semiconductor base.
Description of drawings
Figure 1A is the generalized section that shows according to grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge of one embodiment of the invention;
Figure 1B is the plane figure of the first active region that shows the IGBT-ESD element of Figure 1A;
Fig. 2 A shows the according to another embodiment of the present invention generalized section of IGBT-ESD element;
Fig. 2 B and Fig. 2 C show respectively the plane figure of the different embodiment of the first active region of the IGBT-ESD element of Fig. 2 A;
Fig. 3 A is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention;
Fig. 3 B is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention;
Fig. 4 A is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention;
Fig. 4 B is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention; And
Fig. 5 is the generalized section that shows IGBT-ESD element according to yet another embodiment of the invention.
Drawing reference numeral:
100a, 100b, 300a, 300b, 400a, 400b, 500～IGBT-ESD element;
101,401～P-type silicon base;
102～buried oxide;
402～N-type buried horizon;
103,403～P-type epitaxial loayer;
105～isolated area;
110,310,410,510～semiconductor base;
115,315,415b, 415d, 515～high pressure N-type trap;
415a, 415c, 415e～high pressure P-type trap;
316a, 516～N-type double diffusion district;
316b～P-type double diffusion district;
416～extra dense the doped region of P-type;
117,217a, 217b, 317,417, the dense doped drain region of 517～P-type;
120,320～P-type body doped region;
122,322,422, the dense diffusion region of 522～P-type;
124,324,424, the dense doping source region of 524～N-type;
524 '～N-type light dope (NLDD) district;
426～extra dense the doped region of P-type;
The isolated area of 130a-130c, 330a-330c, 430a-430f, 530a-530c～patterning;
135a, 135b～source electrode;
140,340,440,540～grid structure;
145a, 145b～drain electrode;
OD1～the first active region;
OD2～the second active region.
Embodiment
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below:
Below describe and be accompanied by the example of graphic explanation in detail with each embodiment, as reference frame of the present invention.In graphic or specification were described, similar or identical part was all used identical figure number.And in graphic, the shape of embodiment or thickness can enlarge, and to simplify or convenient the sign.Moreover, graphic in the part of each element will be to describe respectively explanation, in addition, only for disclosing the ad hoc fashion of the present invention's use, it is not to limit the present invention to specific embodiment.
Figure 1A is the generalized section that shows according to grid insulating double-junction transistor (IGBT) protecting component for electrostatic discharge of one embodiment of the invention.In Figure 1A, one grid insulating double-junction transistor (IGBT) electrostatic discharge protective (ESD) element 100a comprises that isolated area 130a, 130b, the 130c of semiconductor substrate 110 and a patterning are arranged on this semiconductor base 110, defines one first active region OD1 and one second active region OD2.According to one embodiment of the invention, this semiconductor base 110 is that silicon (SOI) substrate is arranged on the insulating barrier, and for example a P-type silicon base 101 has a buried oxide 102 on it, and a P-type epitaxial loayer 103 is formed on the buried oxide 102.One isolated area 105 makes other element separation in IGBT-ESD element 100a and the substrate 110.
One high pressure N-type trap 115 is formed among this first active region OD1 of this semiconductor base, one P-type body doped region 120 is in this second active region OD2 of this semiconductor base, wherein this high pressure N-type trap 115 and this P-type body doped region 120 specific range of being separated by exposes this semiconductor base.One diffusion region 113 is extended close from this high pressure N-type trap 115 to this P-type body doped region 120.The dense doped drain region 117 of one P-type is arranged in this high pressure N-type trap 115, and drain electrode 145a, 145b and dense doped drain region 117 electrical contacts of this P-type.The a pair of adjacent dense doping source region 124 of a N-type and the dense diffusion region 122 of a P-type are arranged in this P-type body doped region 120, source electrode 135a, 135b respectively with the dense doping source region 124 of N-type and the dense diffusion region of P-type 122 electrical contacts.One grid structure 140 is on this semiconductor base, and one end and the dense doping source region 124 of this N-type join, and its other end extends on the isolated area 130b of this patterning.
According to one embodiment of the invention, the area of the dense doped drain region 117 of P-type can be greater than the first active region OD1, but less than the area of high pressure N-type trap 115, its plane figure as shown in Figure 1B.
Fig. 2 A shows the according to another embodiment of the present invention generalized section of IGBT-ESD element.In Fig. 2 A, IGBT-ESD element 100b is identical in fact with the IGBT-ESD element 100a of Figure 1A, for asking simple and clear event, omits identical narration at this.Difference is, the area of the dense doped drain region 217a of P-type is less than the area of this high pressure N-type trap 115, and its plane figure is shown in Fig. 2 B.In high pressure N-type trap 115, between high pressure N-type trap 115 and the dense doped drain region 217a of P-type, there is a special shaped doped interface, can disperse and reduce approximately 0.7V of ESD voltage.According to another embodiment of the present invention, the island district that the dense doped drain region 217b of P-type is a plurality of separation is arranged in the high pressure N-type trap 115, and its plane figure is shown in Fig. 2 C.Owing between each island district 217b and the high pressure N-type trap 115, all having a special shaped doped interface, can disperse and reduce ESD voltage, so that the startup (uniform turn-on) of the more uniformity of IGBT-ESD element energy.
Fig. 3 A is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention.In Fig. 3 A, an IGBT-ESD element 300a comprises semiconductor substrate 310, and for example P-type silicon base, an and high pressure N-type trap 315 is arranged in this semiconductor base 310.The isolated area 330a of one patterning, 330b, 330c are arranged on this high pressure N-type trap 315, define one first active region and one second active region.One N-type double diffusion district 316a is arranged in the first active region of high pressure N-type trap 315, and the dense doped drain region 317 of a P-type is arranged among the N-type double diffusion district 316a.One P-type body doped region 320 is arranged in the second active region of this high pressure N-type trap 315, and wherein this N-type double diffusion district 316a and this P-type body doped region 320 specific range of being separated by exposes this high pressure N-type trap.The a pair of adjacent dense doping source region 324 of a N-type and the dense diffusion region 322 of a P-type are arranged in this P-type body doped region 320.One grid structure 340 is on this high pressure N-type trap 315, and one end and the dense doping source region 324 of this N-type join, and its other end extends on the isolated area 330b of this patterning.
Fig. 3 B is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention.In Fig. 3 B, an IGBT-ESD element 300b is identical in fact with the IGBT-ESD element 300a of Fig. 3 A, for asking simple and clear event, omits identical narration at this.Difference is, IGBT-ESD element 300b has a P-type double diffusion district 316b and is arranged in the first active region of high pressure N-type trap 315, and the dense doped drain region 317 of a P-type is arranged among this P-type double diffusion district 316b.Because the dense doped drain region 317 of P-type and P-type double diffusion district 316b are all the P-type and mix, the usefulness that therefore more can promote the ESD element.
Fig. 4 A is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention.In Fig. 4 A, an IGBT-ESD element 400a comprises semiconductor substrate 410, one high pressure N-type trap 415b in this semiconductor base, and one high pressure P-type trap 415c is in this semiconductor base.The isolated area 430a-430d of one patterning is arranged on this semiconductor base, defines one first active region in this high pressure N-type trap 415b and one second active region and one the 3rd active region in this high pressure P-type trap 415c.High pressure P-type trap 415a is arranged at isolated area 430a below.The dense doped drain region 417 of one P-type is arranged in this first active region, and the dense doping source region 424 of a N-type is arranged in this second active region, and the dense doped diffusion region 422 of a P-type is arranged in the 3rd active region.One grid structure 440 is on this high pressure P-type trap 415c, and one end and the dense doping source region 424 of this N-type join, and its other end extends on the isolated area 430b of this patterning.
Fig. 4 B is the generalized section that shows according to the IGBT-ESD element of further embodiment of this invention.In Fig. 4 B, an IGBT-ESD element 400b comprises semiconductor substrate 410, and for example a P-type silicon base 401 has a P-type epitaxial loayer 403 on it, and a N-type buried horizon 402 is arranged between this P-type silicon base 401 and this P-type epitaxial loayer 403.One high pressure N-type trap 415b is in this semiconductor base, and one high pressure P-type trap 415c is in this semiconductor base.The isolated area 430a-430f of one patterning is arranged on this semiconductor base, defines one first active region in this high pressure N-type trap 415b and one second active region and one the 3rd active region in this high pressure P-type trap 415c.High pressure N-type trap 415d is arranged at isolated area 430e below.The dense doped drain region 417 of one P-type is arranged in this first active region, and the dense doping source region 424 of a N-type is arranged in this second active region, and the dense doped diffusion region 422 of a P-type is arranged in the 3rd active region.Moreover an extra dense doped region 416 of P-type is arranged among high pressure P-type trap 415a, and an extra dense doped region 426 of P-type is arranged among high pressure P-type trap 415e.One grid structure 440 is on this high pressure P-type trap 415c, and one end and the dense doping source region 424 of this N-type join, and its other end extends on the isolated area 430c of this patterning.
Fig. 5 is the generalized section that shows IGBT-ESD element according to yet another embodiment of the invention.In Fig. 5, an IGBT-ESD element 500 comprises: semiconductor substrate 510, the isolated area 530a-530c that reaches a patterning is arranged on this semiconductor base 510, defines one first active region and one second active region.One grid structure 540 is arranged on this first active region of this semiconductor base, and a N-type double diffusion district 516 is positioned at a side of this grid structure 540, and arranges in this first active region of this semiconductor base 510.One N-type trap 515 is arranged in this N-type double diffusion district 516, and its bottom extends to the dense doped drain region 517 of these semiconductor base 510, one P-types and is arranged in this N-type trap 515.The dense doping source region 524 of one N-type is arranged in this semiconductor base of opposite side of this grid structure 540, and a N-type light dope (NLDD) district 524 ' extends to the clearance wall below of this grid structure 540.The dense diffusion region 522 of one P-type is arranged in this second active region of this semiconductor base.
It should be noted, the area of the dense doped drain region of P-type of the IGBT-ESD element of various embodiments of the present invention is less than the area of this high pressure N-type trap, so that between high pressure N-type trap and the dense doped drain region of P-type, have a special shaped doped interface, can disperse and reduce approximately 0.7V of ESD voltage.What is more, the dense doped drain region of P-type is the island district of a plurality of separation, be arranged in the high pressure N-type trap, so that between each island district and the high pressure N-type trap, all there is a special shaped doped interface, can disperse and reduce ESD voltage, so that the startup (uniform turn-on) of the more uniformity of IGBT-ESD element energy.
Though the present invention discloses as above with preferred embodiment; so it is not to limit scope of the present invention; have in the technical field under any and usually know the knowledgeable; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention defines and is as the criterion when looking appended claim scope.
Claims (4)
1. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:
The semiconductor substrate;
One high pressure N-type trap is in described semiconductor base;
The isolated area of one patterning is arranged on the described high pressure N-type trap, defines one first active region and one second active region;
One N-type double diffusion district is arranged in described first active region of described high pressure N-type trap;
The dense doped drain region of one P-type is arranged in the described N-type double diffusion district;
One P-type body doped region is in described second active region of described high pressure N-type trap, and wherein said N-type double diffusion district and the described P-type body doped region specific range of being separated by exposes described high pressure N-type trap;
The a pair of adjacent dense doping source region of a N-type and the dense doping source region of a P-type are arranged in the described P-type body doped region; And
One grid structure is on described high pressure N-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.
2. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:
The semiconductor substrate;
One high pressure N-type trap is in described semiconductor base;
The isolated area of one patterning is arranged on the described high pressure N-type trap, defines one first active region and one second active region;
One P-type double diffusion district is arranged in described first active region of described high pressure N-type trap;
The dense doped drain region of one P-type is arranged in the described P-type double diffusion district;
One P-type body doped region is in described second active region of described high pressure N-type trap, and wherein said P-type double diffusion district and the described P-type body doped region specific range of being separated by exposes described high pressure N-type trap;
The a pair of adjacent dense doping source region of a N-type and the dense doping source region of a P-type are arranged in the described P-type body doped region; And
One grid structure is on described high pressure N-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.
3. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:
The semiconductor substrate;
One high pressure P-type trap is in described semiconductor base;
One high pressure N-type trap is in described semiconductor base;
The isolated area of one patterning is arranged on the described semiconductor base, defines one first active region in described high pressure N-type trap and one second active region and one the 3rd active region in described high pressure P-type trap;
The dense doped drain region of one P-type is arranged in described the first active region;
The dense doping source region of one N-type is arranged in described the second active region, and the dense doping source region of a P-type is arranged in described the 3rd active region; And
One grid structure is on described high pressure P-type trap, one end and the dense doping source region of described N-type join, its other end extends on the isolated area of described patterning, the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.
4. a protecting component for electrostatic discharge of grid insulating double-junction transistor is characterized in that, described protecting component for electrostatic discharge of grid insulating double-junction transistor comprises:
The semiconductor substrate;
The isolated area of one patterning is arranged on the described semiconductor base, defines one first active region and one second active region;
One grid structure is arranged on described first active region of described semiconductor base;
One N-type double diffusion district is positioned at a side of described grid structure, and arranges in described first active region of described semiconductor base;
One N-type trap is arranged in the described N-type double diffusion district, and its bottom extends to described semiconductor base;
The dense doped drain region of one P-type is arranged in the described N-type trap;
The dense doping source region of one N-type is arranged in the described semiconductor base of opposite side of described grid structure; And
The dense diffusion region of one P-type is arranged in described second active region of described semiconductor base, and the area of the dense doped drain region of wherein said P-type is less than the area of described the first active region, and the dense doped drain region of described P-type comprises the island district of a plurality of separation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110035850 CN102136491B (en) | 2008-11-03 | 2008-11-03 | Static discharge protection device for gate insulation dual junction transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 201110035850 CN102136491B (en) | 2008-11-03 | 2008-11-03 | Static discharge protection device for gate insulation dual junction transistor |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810174775 Division CN101728384B (en) | 2008-11-03 | 2008-11-03 | Protecting component for electrostatic discharge of grid insulating double-junction transistor |
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| CN102136491A CN102136491A (en) | 2011-07-27 |
| CN102136491B true CN102136491B (en) | 2013-04-10 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE102013103082A1 (en) * | 2012-03-26 | 2013-09-26 | Intel Mobile Communications GmbH | Low voltage ESD limitation using high voltage devices |
| CN107887375B (en) * | 2016-09-29 | 2021-11-09 | 联华电子股份有限公司 | Semiconductor electrostatic discharge protection element |
| CN107887379B (en) * | 2016-09-30 | 2020-07-10 | 中芯国际集成电路制造(上海)有限公司 | Electrostatic discharge protection structure and forming method thereof |
| CN108269857B (en) * | 2016-12-30 | 2020-09-04 | 无锡华润上华科技有限公司 | Junction field effect transistor and manufacturing method thereof |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583365A (en) * | 1993-02-24 | 1996-12-10 | Sgs-Thomson Microelectronics, S.R.L. | Fully depleted lateral transistor |
| US7057215B1 (en) * | 2002-08-02 | 2006-06-06 | National Semiconductor Corporation | PMOS based LVTSCR and IGBT-like structure |
| CN1851923A (en) * | 2006-05-24 | 2006-10-25 | 杭州电子科技大学 | SOI LIGBT device unit of integrated ESD diode |
| CN101145580A (en) * | 2006-09-15 | 2008-03-19 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
-
2008
- 2008-11-03 CN CN 201110035850 patent/CN102136491B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5583365A (en) * | 1993-02-24 | 1996-12-10 | Sgs-Thomson Microelectronics, S.R.L. | Fully depleted lateral transistor |
| US7057215B1 (en) * | 2002-08-02 | 2006-06-06 | National Semiconductor Corporation | PMOS based LVTSCR and IGBT-like structure |
| CN1851923A (en) * | 2006-05-24 | 2006-10-25 | 杭州电子科技大学 | SOI LIGBT device unit of integrated ESD diode |
| CN101145580A (en) * | 2006-09-15 | 2008-03-19 | 三洋电机株式会社 | Semiconductor device and manufacturing method thereof |
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