CN102593181B

CN102593181B - Silicon-on-insulator (SOI) underlay-based high-voltage metal oxide semiconductor tube and manufacturing method

Info

Publication number: CN102593181B
Application number: CN201210086466.9A
Authority: CN
Inventors: 俞国强; 张邵华
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2012-03-28
Filing date: 2012-03-28
Publication date: 2014-12-10
Anticipated expiration: 2032-03-28
Also published as: CN102593181A

Abstract

The invention provides a silicon-on-insulator (SOI) underlay-based high-voltage metal oxide semiconductor tube and a manufacturing method thereof, which can thoroughly eliminate parasitical latch effect existing in a traditional bulk silicon circuit through an all-dielectric isolation technology of a deep groove on the basis of an SOI substrate slice. A high-voltage metal-oxide semiconductor (MOS) tube with thick gate oxide, being prepared by a double-gate-oxide process flow is adopted, so that the reliability is good, and the starting voltage can be improved. A drain-region junction terminal expanding technology is formed in a drain region structure of the high-voltage MOS tube, and a source-region junction terminal expanding technology is formed in a source region structure of the high-voltage MOS tube to be used for adjusting a threshold voltage of devices, so that double functions can be realized. The source-region junction terminal expanding technology is combined with the drain-region junction terminal expanding technology to use, and a double-region junction terminal expanding technology is formed, so that the voltage resistance of the device can be further improved, the size of the device can be reduced, the pattern area can be reduced, and the integration degree of a chip can be improved. The source-region structure is provided with an aluminum field plate above a polycrystalline field plate to be short-circuited with a source electrode, so that the voltage resistance of the device can be improved.

Description

High-voltage metal oxide semiconductor pipe and manufacture method based on SOI substrate

Technical field

The present invention relates to integrated circuit and manufacture field, relate in particular to a kind of high-voltage metal oxide semiconductor pipe and manufacture method based on SOI substrate.

Background technology

Silicon in dielectric substrate (SOI:Silicon On Insulator) technology, as a kind of Fully dielectric isolation technology, has the incomparable superiority of many body silicon technologies.That the burning property management (metal-oxide-semiconductor) of SOI has is low in energy consumption, antijamming capability is strong, integration density is high, speed high (parasitic capacitance is little), technique is simple, capability of resistance to radiation is strong, and has thoroughly eliminated the advantages such as the parasitic latch-up of body silicon MOS device.Metal-oxide semiconductor (MOS) power IC device has the advantages such as switching characteristic is good, power consumption is little, and MOS power device has greater advantage in the range of application of 10-600V.Therefore, the MOS power device of conventional bulk silicon technological is prepared on SOI substrate, integrates both advantages, eliminated the latch-up in integrated circuit completely, other various aspects of performance of integrated circuit is also had been further upgraded.

Summary of the invention

The object of this invention is to provide a kind of high performance high-voltage metal oxide semiconductor pipe and manufacture method thereof based on SOI substrate.

For addressing the above problem, the invention provides a kind of high-voltage metal oxide semiconductor pipe based on SOI substrate, comprise, a kind of high-voltage metal oxide semiconductor pipe based on SOI substrate, comprises SOI substrate;

Deep trench, is arranged in described SOI substrate; Drain structure, be arranged in described SOI substrate, described drain structure ecto-entad comprises drain region first kind trap, first kind buffering area, drain region and the dense injection region of the drain region first kind that Second Type buffering area, drain region and concentration increase progressively successively, and the dense injection region of the first kind, described drain region is as drain electrode; Source region structure, be arranged in described SOI substrate, comprise source region Second Type trap, be arranged in source region Second Type trap Second Type buffering area, source region, be arranged in the source region first kind trap of Second Type buffering area, described source region and the dense injection region of the source region first kind of adjacent setting and the dense injection region of source region Second Type, source region first kind trap is connected with the dense injection region of the first kind, described source region, and the dense injection region of the first kind, described source region and the dense injection region of source region Second Type are jointly as source electrode; Field oxygen, is arranged in described drain structure, is positioned at a side of closing on source region structure; Grid oxygen, is arranged between described oxygen and the dense injection of the source region first kind; Grid, comprises polysilicon gate and the polycrystalline field plate of adjacent setting, and described polysilicon gate is arranged on described grid oxygen, and described polycrystalline field plate is arranged on described oxygen; Interlayer dielectric layer, is arranged on described SOI substrate surface.

Further, the concentration of Second Type buffering area, described drain region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described drain region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of first kind buffering area, described drain region is 3 × 10 ¹⁷cm ^-3～9 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described drain region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3.

Further, the concentration of Second Type buffering area, described drain region is 4 × 10 ¹⁶cm ^-3, the concentration of described drain region first kind trap is 8 × 10 ¹⁶cm ^-3, the concentration of first kind buffering area, described drain region is 6 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, drain region is 7 × 10 ¹⁹cm ^-3.

Further, the concentration of described source region Second Type trap is 8 × 10 ¹⁵cm ^-3～4 × 10 ¹⁶cm ^-3, the concentration of Second Type buffering area, described source region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described source region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described source region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, the concentration of the dense injection region of Second Type, described source region is 1 × 10 ²⁰cm ^-3～5 × 10 ²⁰cm ^-3.

Further, the concentration of described source region Second Type trap is 2 × 10 ¹⁶cm ^-3, the concentration of Second Type buffering area, described source region is 4 × 10 ¹⁶cm ^-3, the concentration of source region first kind trap is 8 × 10 ¹⁶cm ^-3, the concentration of the dense injection region of the first kind, source region is 7 × 10 ¹⁹cm ^-3, the concentration of the dense injection region of Second Type, source region is 3 × 10 ²⁰cm ^-3.

Further, the thickness of described oxygen is 600nm～1500nm.

Further, described grid oxygen adopts Dual Gate Oxide structure, comprise thin grid oxygen and the thick grid oxygen of adjacent setting, described thin grid oxygen is arranged on the dense injection region of the source region first kind and the dense injection region of source region Second Type, and described thick grid oxygen is arranged between described oxygen and described thin grid oxygen.

Further, the thickness of described thick grid oxygen is 300nm～800nm, and the thickness of described thin grid oxygen is 12nm～36nm.

Further, described SOI substrate comprises the top silicon layer of substrate slice, buried oxidation layer and the Second Type of the first kind from bottom to up successively.

Further, the thickness of described buried oxidation layer is 1um～2um.

Further, described top silicon layer thickness is 5um～20um, in described top silicon layer, has dopant, and doping content is 3 × 10 ¹⁵m ^-3～7 × 10 ¹⁵cm ^-3.

Further, the degree of depth of described deep trench is 5um～20um.

Further, in described deep trench, there is the filler that comprises silicon dioxide and unadulterated polysilicon.

Further, the material of described interlayer dielectric layer is phosphorosilicate glass.

Further, on the described interlayer dielectric layer of described polycrystalline field plate top, be provided with aluminium field plate, described aluminium field plate and described source electrode are electrical connected.

Further, the described first kind is P type, and described Second Type is N-type; Or the described first kind is N-type, described Second Type is P type.

The present invention also provides a kind of manufacture method of the high-voltage metal oxide semiconductor pipe based on SOI substrate, comprises,

SOI substrate is provided, and forms deep trench in described SOI substrate;

In described SOI substrate, form source region Second Type trap;

Carry out ion implantation technology, form Second Type buffering area, drain region and Second Type buffering area, source region, Second Type buffering area, described source region is arranged in described source region Second Type trap;

Carry out ion implantation technology, form drain region first kind trap and source region first kind trap, described drain region first kind trap is arranged in Second Type buffering area, described drain region, and described source region first kind trap is arranged in Second Type buffering area, described source region;

Close on being positioned at of described drain structure and in a side of source region structure, form an oxygen;

Between described oxygen and the dense injection of the source region first kind, form grid oxygen;

On described grid oxygen and described oxygen, form grid structure, described grid structure comprises polysilicon gate and the polycrystalline field plate of adjacent setting, and described polysilicon gate is positioned on described grid oxygen, and described polycrystalline field plate is positioned on described oxygen;

Carry out ion implantation technology, in the first kind trap of described drain region, form first kind buffering area, drain region;

Carry out ion implantation technology, in first kind buffering area, described drain region, form the dense injection region of the drain region first kind, in Second Type buffering area, described source region, form the dense injection region of the source region first kind and the dense injection region of source region Second Type of adjacent setting;

On described SOI substrate, deposition forms interlayer dielectric layer.

Further, the concentration of Second Type buffering area, described drain region is with 4 × 10 ¹⁶cm-3, the concentration of described drain region first kind trap is 8 × 10 ¹⁶cm ^-3, the concentration of first kind buffering area, described drain region is 6 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, drain region is 7 × 10 ¹⁹cm ^-3.

Further, the thickness of described oxygen is 600nm～1500nm.

Further, described SOI substrate comprises the top silicon layer of substrate slice, buried oxidation layer and the Second Type of the first kind from bottom to up successively, the thickness of described buried oxidation layer is 1um～2um, described top silicon layer thickness is 5um～20um, in described top silicon layer, have dopant, doping content is 3 × 10 ¹⁵cm ^-3～7 × 10 ¹⁵cm ^-3.

Further, the degree of depth of described deep trench is 5um～20um.

Further, form the step of source region Second Type trap in described SOI substrate before, comprising: at described SOI Grown the first silicon oxide layer; Described the first silicon oxide layer, after forming the step of described drain region first kind trap and source region first kind trap, and is removed before forming the step of described oxygen.

Further, the thickness of described the first silicon oxide layer is 20nm～50nm, and the growth temperature of described the first silicon oxide layer is 800 DEG C～900 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes.

Further, the step that forms source region Second Type trap in described SOI substrate comprises: on described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation source region Second Type trap; Form the region dopant implant ion of source region Second Type trap to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process.

Further, the doping ion that forms the region injection of source region Second Type trap to wish is phosphonium ion, and implantation dosage is 1.0E12～6.0E12ions/cm ², Implantation Energy is 60KeV～120KeV.

Further, in described SOI substrate, form in the step of source region Second Type trap, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and preferably, the annealing temperature of described high-temperature annealing process is 1100 DEG C～1200 DEG C, annealing atmosphere is nitrogen, and annealing time is 200～300 minutes.

Further, the step that forms Second Type buffering area, drain region and Second Type buffering area, source region comprises: on described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation Second Type buffering area, drain region and Second Type buffering area, source region; Form the region dopant implant ion of Second Type buffering area, drain region and Second Type buffering area, source region to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process.

Further, the doping ion that forms the region injection of Second Type buffering area, drain region and Second Type buffering area, source region to wish is phosphonium ion, and implantation dosage is 2.0E12～8.0E12ions/cm ², Implantation Energy is 60KeV～120KeV.

Further, in the step of formation Second Type buffering area, drain region and Second Type buffering area, source region, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and preferably, the annealing temperature of described high-temperature annealing process is 1100 DEG C～1200 DEG C, annealing atmosphere is nitrogen, and annealing time is 100～200 minutes.

Further, the step that forms drain region first kind trap and source region first kind trap comprises: on described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation drain region first kind trap and source region first kind trap; Form the region dopant implant ion of drain region first kind trap and source region first kind trap to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process.

Further, the doping ion that forms the region injection of drain region first kind trap and source region first kind trap to wish is boron ion, and implantation concentration is 5.0E12～3E13ions/cm ², Implantation Energy is 40KeV～100KeV.

Further, in the step of formation drain region first kind trap and source region first kind trap, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and preferably, the annealing temperature of described high-temperature annealing process is 1100 DEG C～1200 DEG C, annealing atmosphere is the atmosphere of nitrogen and oxygen, and annealing time is 100～200 minutes.

Further, between the step of formation drain region first kind trap, source region first kind trap and a formation oxygen, comprise: on described SOI substrate, form successively the second silicon oxide layer and silicon nitride layer.

Further, the thickness of described the second silicon oxide layer is 30nm～60nm, and growth temperature is 850 DEG C～1000 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes.

Further, the step that forms an oxygen comprises: on described silicon nitride layer, form the photoresist of patterning, expose the silicon nitride layer in a wish formation oxygen region; Silicon nitride layer described in etching, exposure wish forms second silicon oxide layer in the region of an oxygen; Remove the photoresist of patterning; On the second silicon oxide layer exposing, form described oxygen.

Further, the thickness of described silicon nitride layer is 100nm～300nm, adopts low-pressure chemical vapor phase deposition technique, and deposition temperature is 700 DEG C～800 DEG C.

Further, the growth temperature of described oxygen is 850 DEG C～1000 DEG C, and growth atmosphere is wet oxygen, and growth time is 280～400 minutes.

Further, the step that forms thick grid oxygen comprises: on described silicon nitride layer, form the photoresist of patterning, exposure wish forms the silicon nitride layer in thick grid oxygen region; Silicon nitride layer described in etching, exposure wish forms second silicon oxide layer in thick grid oxygen region; Remove the photoresist of patterning; Remove the second silicon oxide layer by hydrofluoric acid wet method, exposure wish forms the SOI substrate in thick grid oxygen region; On the SOI substrate exposing, form described thick grid oxygen.

Further, the thickness of described thick grid oxygen is 300nm～800nm, adopts in boiler tube and mixes the formation of oxychloride method, and growth temperature is 900 DEG C～1100 DEG C, adopts the oxychloride technique of mixing of chloride gaseous state thing to grow, and growth time is 50～100 minutes.

Further, the step that forms thin grid oxygen comprises: wet method is removed the remaining silicon nitride layer of SOI substrate surface; Rewetting method is removed remaining the second silicon oxide layer, and exposure wish forms the SOI substrate in thin grid oxygen region; Finally on the SOI substrate exposing, form described thin grid oxygen.

Further, the thickness of described thin grid oxygen is 12nm～36nm, adopts in boiler tube and mixes the formation of oxychloride method, and growth temperature is 800 DEG C～950 DEG C, adopts the oxychloride technique of mixing of chloride gaseous state thing to grow, and growth time is 20～60 minutes.

Further, the step of formation grid structure comprises: deposit one deck polysilicon layer on described SOI substrate; To described polysilicon layer dopant implant ion; Form the photoresist of patterning, expose the polysilicon layer of wish formation grid; Polysilicon layer described in etching, to form grid structure; Remove the photoresist of patterning.

Further, adopt low-pressure chemical vapor phase deposition method growing polycrystalline silicon layer, the thickness of polysilicon layer is 250nm～600nm.

The doping ion further injecting to described polysilicon layer is phosphonium ion, and implantation dosage is 5.0E15～1.0E16ions/cm ², Implantation Energy is 40KeV～100KeV.

Further, the step of formation first kind buffering area, drain region comprises: on described SOI substrate, form the 3rd silicon oxide layer; Form the photoresist of patterning, form the region of first kind buffering area, drain region to expose wish; Form the region dopant implant ion of first kind buffering area, drain region to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process; Remove described the 3rd silicon oxide layer.

Further, the thickness of described the 3rd silicon oxide layer is 20nm～50nm, and growth temperature is 800 DEG C～900 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes.

Further, the doping ion that forms the region injection of first kind buffering area, drain region to wish is boron ion, and implantation dosage is 3.0E13～1.3E14ions/cm ², Implantation Energy is 40KeV～100KeV.

Further, form in the high-temperature annealing process of first kind buffering area, drain region, annealing temperature is 1000 DEG C～1150 DEG C, and annealing atmosphere is nitrogen, and annealing time is 100～200 minutes.

The step of further, the dense injection of the formation drain region first kind, the dense injection region of the source region first kind and the dense injection region of Second Type, source region comprises: on described SOI substrate, form the 4th silicon oxide layer; Form the photoresist of patterning, form the 4th silicon oxide layer in the region of the dense injection region of Second Type, source region to expose wish; Form the region dopant implant ion of the dense injection region of Second Type, source region to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process for the first time; Form the photoresist of patterning, expose the 4th silicon oxide layer in the region of the wish formation dense injection region of the first kind, source region and the dense injection region of the first kind, drain region; Form the region dopant implant ion of the dense injection region of the first kind, source region and the dense injection region of the first kind, drain region to wish; Remove the photoresist of patterning; Carry out high-temperature annealing process for the second time; Remove described the 4th silicon oxide layer.

Further, the thickness of described the 4th silicon oxide layer is 10nm～30nm, and growth temperature is 800 DEG C～900 DEG C, and growth atmosphere is dry oxygen, and growth time is 20～60 minutes.

Further, the doping ion that forms the region injection of the dense injection region of Second Type, source region to wish is arsenic ion, and implantation dosage is 4.0E15～1.0E16ions/cm ², Implantation Energy is 80KeV～120KeV.

Further, in high-temperature annealing process for the first time, annealing temperature is 900 DEG C～1000 DEG C, and annealing atmosphere is nitrogen oxygen atmosphere, and annealing time is 30～60 minutes.

Further, the doping ion that forms the region injection of the dense injection region of the first kind, source region and the dense injection region of the first kind, drain region to wish is boron difluoride ion, and implantation dosage is 1.0E15～5.0E15ions/cm ², Implantation Energy is 80KeV～120KeV.

Further, in high-temperature annealing process for the second time, annealing temperature is 900 DEG C～1000 DEG C, and annealing atmosphere is nitrogen, and annealing time is 30～60 minutes.

Further, the described first kind is P type, and described Second Type is N-type, or the described first kind is N-type, and described Second Type is P type.

In sum, compared with prior art, high-voltage metal oxide semiconductor pipe and the manufacture method tool based on SOI substrate of the present invention has the following advantages:

1. the drain structure of the high-voltage metal oxide semiconductor pipe based on SOI substrate of the present invention has formed drain region knot termination extension technology by drain region first kind trap, first kind buffering area, drain region and the dense injection of drain region first kind three, and wherein first kind buffering area in drain region is used for the withstand voltage and operating current of compromise device.Source region structure is made up of the dense injection region of source region Second Type, Second Type buffering area, source region and source region Second Type trap, this has formed source region knot termination extension technology the dense injection region of source region Second Type, Second Type buffering area, source region, source region Second Type trap and top silicon layer, wherein Second Type trap in source region is used for improving device withstand voltage, also can be used for regulating the threshold voltage of device, there is double-deck effect.Tie termination extension technology by source region is used in combination together with the knot termination extension technology of drain region, form two-region knot termination extension technology, can further improve device withstand voltage than routine list district knot termination extension technology, thereby reduce device size, the scaled down version area of pictural surface, the integrated level of lifting chip.

2. the Second Type buffering area, drain region of the drain structure of the high-voltage metal oxide semiconductor pipe based on SOI substrate of the present invention can prevent drain region first kind trap and source region first kind trap punch-through breakdown between the two, thereby improves its puncture voltage.

3. the high-voltage metal oxide semiconductor pipe based on SOI substrate of the present invention is the high-voltage metal oxide semiconductor pipe in conjunction with the Fully dielectric isolation technology of deep trench based on SOI substrate slice, adopts SOI substrate and deep trench isolation technology can thoroughly eliminate the parasitic latch-up existing in body silicon circuit in the past.

4. the high-voltage MOS pipe of the thick grid oxygen that prepared by the technological process of the manufacture method of the high-voltage metal oxide semiconductor pipe based on SOI substrate of the present invention employing Dual Gate Oxide, the demand of grid voltage when the oxidated layer thickness of its thick grid oxygen can use according to device (scope can from 100V～600V) is determined, thin grid oxygen high tension apparatus different from the past, its grid voltage is often confined in digital current potential 5V; Thickness is moderate, has both improved the reliability of device, avoids again the blocked up switching speed that affects device.

5. in addition, the source region structure of the high-voltage metal oxide semiconductor pipe based on SOI substrate of the present invention is provided with aluminium field plate in polycrystalline field plate top position, with source shorted, the rational position by ingenious layout aluminium field plate and design optimum size, can improve the withstand voltage of device.

Brief description of the drawings

Fig. 1 is the structural representation of the high-voltage metal oxide semiconductor pipe based on SOI substrate in one embodiment of the invention.

Fig. 2 is the schematic flow sheet of the manufacture method of the high-voltage metal oxide semiconductor pipe based on SOI substrate in one embodiment of the invention.

Embodiment

For making content of the present invention more clear understandable, below in conjunction with Figure of description, content of the present invention is described further.Certainly the present invention is not limited to this specific embodiment, and the known general replacement of those skilled in the art is also encompassed in protection scope of the present invention.

Secondly, the present invention utilizes schematic diagram to carry out detailed statement, and in the time that example of the present invention is described in detail in detail, for convenience of explanation, schematic diagram does not amplify according to general ratio is local, should be using this as limitation of the invention.

Fig. 1 is the structural representation of the high-voltage metal oxide semiconductor pipe based on SOI substrate in one embodiment of the invention, as shown in Figure 1, the invention provides a kind of high-voltage metal oxide semiconductor pipe based on SOI substrate, comprise SOI substrate, deep trench, drain structure, source region structure, an oxygen 17, Dual Gate Oxide structure, interlayer dielectric layer 24 and aluminium field plate 21.

Described deep trench is arranged in described SOI substrate; Wherein said SOI substrate comprises the top silicon layer 3 of substrate slice 1, buried oxidation layer 2 and the Second Type of the first kind from bottom to up successively.In described deep trench, have the filler that comprises silicon dioxide 6 and unadulterated polysilicon 5, described SOI substrate and described deep trench have formed the SOI substrate of Fully dielectric isolation.

Described drain structure is arranged in the top silicon layer 3 of described SOI substrate, described drain structure ecto-entad comprises drain region first kind trap 13, first kind buffering area, drain region 14 and the dense injection region 15 of the drain region first kind that Second Type buffering area 12, drain region and concentration increase progressively successively, and the first kind dense injection region 15 in described drain region is as drain electrode; The concentration of Second Type buffering area, described drain region 12 is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described drain region first kind trap 13 is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of first kind buffering area, described drain region 14 is 3 × 10 ¹⁷cm ^-3～9 × 10 ¹⁷cm ^-3, the concentration of the dense injection region 15 of the first kind, described drain region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3.

Described drain region first kind trap 13, first kind buffering area, drain region 14 and the dense injection region 15 of the drain region first kind have formed drain region knot termination extension technology, three's concentration increases progressively successively, wherein drain region first kind trap 13 concentration are the lightest, first kind buffering area, drain region 14 concentration are taken second place, the concentration of the dense injection region 15 of the drain region first kind is the denseest, at the outer source region Second Type trap 11 that is arranged with of Second Type buffering area, source region 10, can play the bilayer effect for improving device withstand voltage and adjusting threshold voltage simultaneously.

In addition, Second Type buffering area, drain region 12 can prevent from, between drain region first kind trap 13 and source region first kind trap 9, punch-through breakdown occurs, thereby further improves puncture voltage.First kind buffering area, described drain region 14 is used for the withstand voltage and operating current of compromise device.

Described source region structure is arranged in the top silicon layer 3 of described SOI substrate, comprise source region Second Type trap 11, be arranged in the Second Type buffering area, source region 10 of source region Second Type trap 11, the dense injection region 7 of the source region first kind that is positioned at described source region 10Zhong source region, Second Type buffering area first kind trap 9 and adjacent setting is connected with the dense injection region 7 of the described source region first kind with the dense injection region of source region Second Type 8 source region first kind traps 9, the dense injection region 7 of the described source region first kind and the dense injection region 8 of source region Second Type are jointly as source electrode; The concentration of the top silicon layer 3 of described SOI substrate is 3 × 10 ¹⁵cm ^-3～7 × 10 ¹⁵cm ^-3, the concentration of described source region Second Type trap 11 is 8 × 10 ¹⁵cm ^-3～4 × 10 ¹⁶cm ^-3, the concentration of Second Type buffering area, described source region 10 is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described source region first kind trap 9 is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of the dense injection region 7 of the first kind, described source region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, the concentration of the dense injection region 8 of Second Type, described source region is 1 × 10 ²⁰cm ^-3～5 × 10 ²⁰cm ^-3.

Together with top silicon layer 3, source region Second Type trap 11 and Second Type buffering area, source region 10 and the dense injection of source region Second Type, form source region knot termination extension technology, four concentration increases progressively successively, top silicon layer 3 concentration minimums in three, source region Second Type trap 11 concentration are taken second place, after 10 concentration of Second Type buffering area, source region, the concentration maximum of the dense injection of source region Second Type.Combine with described drain region knot termination extension technology, form together two-region knot termination extension technology, the bilayer effect that further improves device withstand voltage and adjusting threshold voltage.

Described oxygen 17 is arranged on the top silicon layer 3 of described drain structure, and is positioned at a side of closing on source region structure; Described Dual Gate Oxide structure comprises thin grid oxygen 25 and the thick grid oxygen 16 of adjacent setting, and described thin grid oxygen 25 is arranged in the dense injection region 7 of the source region first kind and the dense injection 8 of source region Second Type, and described thick grid oxygen 16 is arranged between described oxygen 17 and described thin grid oxygen 25.

The long thin grid oxygen 25 that has routine above the dense injection region 7 of the source region first kind and the dense injection 8 of source region Second Type, close on being positioned at of described drain structure in a side of source region structure and be provided with an oxygen 17, in the middle of oxygen 17 on the scene and thin grid oxygen 25, length has thick grid oxygen 16, the thickness of described oxygen 17 is 600nm～1500nm, the thickness of described thick grid oxygen 16 is 300nm～800nm, the thickness of described thin grid oxygen 25 is 12nm～36nm, the oxidated layer thickness of thick grid oxygen 16 is between field oxygen 17 and thin grid oxygen 25, thinner than an oxygen 17, thicker than thin grid oxygen 25, this device architecture is realized in Dual Gate Oxide technological process, when thick grid oxygen 17 makes circuit design because of its current potential that has improved grid, application is more flexible.

Described grid comprises polysilicon gate 22 and the polycrystalline field plate 23 of adjacent setting, and described polysilicon gate 22 is arranged on described thick grid oxygen 16, and described polycrystalline field plate 23 is arranged on described oxygen 17; Between the dense injection 7 of described polysilicon gate 22 and the source region first kind, be provided with source region first kind trap 9, the raceway groove that can prevent source region structure one side causes component failure because of disconnection.

Described interlayer dielectric layer 24 is arranged on described SOI substrate surface; Described aluminium field plate 21 is arranged on the described interlayer dielectric layer 24 of described polycrystalline field plate 23 tops.The material of described interlayer dielectric layer 24 can be phosphorosilicate glass.Described aluminium field plate 21 is electrical connected with described source electrode.

Described interlayer dielectric layer 24 is covered on described polysilicon gate 22 and an oxygen 17, directly over phosphorosilicate glass 24 and polycrystalline field plate 23, position is provided with aluminium field plate 21 and improves the puncture voltage of device, and aluminium field plate 21 is to be connected with source electrode 18, can improve the voltage endurance capability of device by the position of rational deployment aluminium field plate and the size of setting aluminium field plate.

In addition, also comprise the source terminal 18 of source electrode being drawn through interlayer dielectric layer 24, the drain terminal 20 of drain electrode being drawn through interlayer dielectric layer 24, the grid lead-out wire 19 of grid being drawn through interlayer dielectric layer 24 etc., thereby the structure of the perfect high-voltage metal oxide semiconductor pipe based on SOI substrate.

The described high-voltage metal oxide semiconductor pipe based on SOI substrate can be N-type high-voltage MOS pipe or P type high-voltage MOS pipe, for N-type metal-oxide-semiconductor the described first kind all refer to N-type, described Second Type all refers to P type, for P type metal-oxide-semiconductor the described first kind all refer to P type, described Second Type all refers to N-type.Fig. 1, taking P type high-voltage MOS pipe as example, has represented brief configuration schematic diagram.It is evident that, in structure, the first kind is changed to N-type, and Second Type is changed to after P type, demonstration be the structure of N-type high-voltage MOS pipe, also within thought range of the present invention.

Fig. 2 is the manufacture method of the high-voltage metal oxide semiconductor pipe based on SOI substrate in one embodiment of the invention, specifically comprises the following steps:

Step S01: SOI substrate is provided, and forms deep trench in described SOI substrate;

Step S02: form source region Second Type trap in described SOI substrate;

Step S03: carry out ion implantation technology, form Second Type buffering area, drain region and Second Type buffering area, source region, Second Type buffering area, described source region is arranged in described source region Second Type trap;

Step S04: carry out ion implantation technology, form drain region first kind trap and source region first kind trap, described drain region first kind trap is arranged in Second Type buffering area, described drain region, and described source region first kind trap is arranged in Second Type buffering area, described source region;

Step S05: close on being positioned at of described drain structure and form an oxygen in a side of source region structure;

Step S06: form Dual Gate Oxide structure on the SOI substrate between described drain structure and source region structure, comprise thick grid oxygen and the thin grid oxygen of adjacent setting, described thin grid oxygen is arranged on the dense injection region of the source region first kind and the dense injection region of source region Second Type, and described thick grid oxygen is arranged between described oxygen and described thin grid oxygen;

Step S07: form grid structure on described thick grid oxygen and described oxygen, described grid structure comprises polysilicon gate and the polycrystalline field plate of adjacent setting, and described polysilicon gate is positioned on described thick grid oxygen, described polycrystalline field plate is positioned on described oxygen;

Step S08: carry out ion implantation technology, form first kind buffering area, drain region in the first kind trap of described drain region;

Step S09: carry out ion implantation technology, in first kind buffering area, described drain region, form the dense injection region of the drain region first kind, in Second Type buffering area, described source region, form the dense injection region of the source region first kind and the dense injection region of source region Second Type of adjacent setting;

Step S 10: deposition forms interlayer dielectric layer on described SOI substrate, and forms aluminium field plate on the described interlayer dielectric layer above described polycrystalline field plate.

In conjunction with Fig. 1 and Fig. 2, following taking the P type high-voltage metal oxide semiconductor pipe based on SOI substrate as embodiment, the first kind is P type, and Second Type is N-type.The detailed description manufacture method of the present invention of P type high-voltage MOS pipe in following the present embodiment, but the content providing in embodiment is provided described manufacture method.

In step S01, first SOI substrate is provided, described SOI substrate comprises three layers: ground floor is common P type doped substrate sheet 1, crystal orientation is <100>, resistivity is the substrate slice of 10～20ohmcm, the second layer is to be positioned at the buried oxidation layer (BOX: Buried Oxide) on P type doped substrate sheet 1 described in ground floor, buried oxidation layer 2 can be given birth to formation by thermal oxidation, preferably material is silicon dioxide, thickness range is 1～2um, the 3rd layer of top silicon layer 3 that is the N-type doping that is provided with in buried oxidation layer described in the second layer 2, the effect of described top silicon layer 3 is similar to epitaxial loayer, thickness is 5～20um, concentration is 3 × 10 ¹⁵cm ^-3～7 × 10 ¹⁵cm ^-3.3 three layers of growth successively from the bottom to top of top silicon layer of described P type doped substrate sheet 1, buried oxidation layer 2 and N-type doping.The SOI substrate jointly being formed by the top silicon layer 3 of above-described P type doped substrate sheet 1, buried oxidation layer 2 and N-type doping.

Then, in described SOI substrate, form deep trench; Detailed process is: first at the top silicon layer 3 superficial growth silicon dioxide of described SOI substrate, then apply one deck photoresist at this silica surface, recycling mask aligner carries out the photoetching of groove version, etch away subsequently the silicon dioxide of trench region, remove photoresist again, after completing, carry out ditch groove by anisotropy and the high selectivity technology of dry plasma etch, on top silicon layer 3, carve not only dark but also straight groove, then remove the residual silicon dioxide of clean surface with hydrofluoric acid corrosive liquid.To described top silicon layer 3 carried out deep plough groove etched after, then the deep trench of previously having carved is filled up with backfilling process, the technology of employing is Fully dielectric isolation technology, can thoroughly eliminate the parasitic latch-up existing in body silicon circuit in prior art.The concrete implementing method of backfilling process is to have carried out deep plough groove etched SOI substrate based on above-mentioned, the first thicker silicon dioxide 6 of one deck of simultaneously growing in top silicon layer 3 surfaces and deep trench, use again the unadulterated high resistance polysilicon 5 of low-pressure chemical vapor phase deposition one deck, after complete this layer of high resistance polysilicon 5 of deposit, add the silicon dioxide 6 of having grown in previous groove, thereby two-layer filler can all be filled groove full.Finally, described groove is carried out to plasma dry and return quarter, etch away the unadulterated high resistance polysilicon 5 on described top silicon layer surface, only etch away the unadulterated polysilicon of most surface, the unadulterated polysilicon 5 in groove has been retained.Then on above-mentioned silicon dioxide 6, apply one deck photoresist; recycling mask aligner carries out the photoetching of groove protection version; above groove, covering protection is lived with photoresist, uses subsequently the silicon dioxide outside the clean groove of hydrofluoric acid corrosive liquid wet method rinsing, finally photoresist is removed clean.Silicon dioxide 6 in groove like this, under the protection of photoresist by complete preservation time.Till this walks operation, just complete the Fully dielectric isolation process of the deep trench of SOI substrate.

In step S02, in described SOI substrate, form source region N-type trap 11; The SOI substrate of the Fully dielectric isolation with deep trench completing based on aforementioned preparation, the first silicon oxide layer that is 20nm～50nm in top silicon layer 3 superficial growth a layer thickness, growth temperature is 800 DEG C～900 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes; Then, on the first silicon oxide layer of this 20nm～50nm, apply one deck photoresist, then utilize mask aligner in lithographic mask layer, to open the region of wish formation source region N-type trap 11; Then the region implantation dosage that, forms described source region N-type trap 11 to wish is 1.0E12～6.0E12ions/cm ², and the energy phosphonium ion that is 60KeV～120KeV; Injection finishes the rear method with wet etching, removes the photoresist on the first silicon oxide layer of above-mentioned 20nm～50nm; Then, in diffusion furnace tube, carry out high annealing, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and wherein preferably, annealing temperature is 1100 DEG C～1200 DEG C, annealing atmosphere is nitrogen, and annealing time is 200～300 minutes.Complete after annealing, the concentration range of source region N-type trap 11 is 8 × 10 ¹⁵cm ^-3～4 × 10 ¹⁶cm ^-3, wherein concentration is with 2 × 10 ¹⁶cm ^-3for the best.

In step S03, carry out ion implantation technology, form N-type buffering area, drain region 12 and N-type buffering area, source region 11, N-type buffering area, described source region 10 is arranged in described source region N-type trap 11;

Continue the upper one deck photoresist that applies of the first silicon oxide layer (not indicating in figure) at top silicon layer 3 surperficial 20nm～50nm, utilize photoresist described in mask aligner patterning, to expose first silicon oxide layer in region of N-type buffering area, source region 10 and N-type buffering area, drain region 12, the first oxide layer can be in the process of follow-up doping Implantation, and the top silicon layer 3 of the SOI substrate of protection below is injury-free; Then be, 2.0E12～8.0E12ions/cm at the region implantation dosage of N-type buffering area, source region 10 and N-type buffering area, drain region 12 ²and the phosphonium ion that energy is 60KeV～120KeV; Injection finishes rear method of removing photoresist by wet method, removes the photoresist above the silicon dioxide of above-mentioned 20nm～50nm; In diffusion furnace tube, carry out high annealing, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and wherein preferably, annealing temperature is 1100 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～200 minutes, completes after annealing, and the concentration range of N-type buffering area, source region 10 and N-type buffering area, drain region 12 is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, wherein the concentration of source region N-type buffering area 10 and N-type buffering area, drain region 12 is with 4 × 10 ¹⁶cm ^-3for the best.

In step S04, carry out ion implantation technology, form drain region P type trap 14 and source region P type trap 9, described drain region P type trap 14 is arranged in N-type buffering area, described drain region 10, and described source region P type trap 9 is arranged in N-type buffering area, described source region 12;

Continue to apply one deck photoresist on the first silicon oxide layer of top silicon layer 3 surperficial described 20nm～50nm, utilize photoresist described in mask aligner patterning, to expose first silicon oxide layer in region of source region P type trap 9 and drain region P type trap 14; Region implantation dosage at above-mentioned source region P type trap 9 and drain region P type trap 14 is 5.0E12～3E13ions/cm ²and the boron ion that energy is 40KeV～100KeV; Injection finishes rear method of removing photoresist by wet method, removes the photoresist of surface pattern on the first silicon oxide layer of above-mentioned 20nm～50nm; Then, in diffusion furnace tube, carry out high annealing, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, and annealing atmosphere is nitrogen, and annealing time is 100～300 minutes, wherein preferably, annealing temperature is 1100 DEG C～1200 DEG C, and annealing atmosphere is the nitrogen oxygen atmosphere that nitrogen adds little oxygen, and annealing time is 100～200 minutes, complete after annealing, the concentration range of source region P type trap 9 and drain region P type trap 14 is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, and concentration is with 8 × 10 ¹⁶cm ^-3for the best.

In step S05, close on and in a side of source region structure, form an oxygen 17 being positioned at of described drain structure; First use the first silicon oxide layer of the clean top silicon layer of the diluted hydrofluoric acid rinsing described 20nm～50nm in surface, the a layer thickness that regrows is the second silicon oxide layer of 30nm～60nm, growth temperature is 850 DEG C～1000 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes; The silicon nitride layer that deposit a layer thickness is 100nm～300nm on the silicon dioxide of described 30nm～60nm, adopts low-pressure chemical vapor phase deposition technique, and deposition temperature is 700 DEG C～800 DEG C; Then, on the silicon nitride of this 100nm～300nm, apply one deck photoresist, utilize mask aligner to form the photoresist of patterning, to expose the second silicon oxide layer that has the region outside PMOS pipe source region structure, drain structure and double-gate structure, protect source region structure, drain structure and double-gate structure with glue; Etch away the silicon nitride of the 100nm～300nm outside active area by plasma method at dry quarter; Remove the photoresist of source region structure, drain structure and double-gate structure with the combination ashing method that dry method is removed photoresist and wet method is removed photoresist; In diffusion furnace tube, grow 600nm～1500nm silicon dioxide material field oxygen, growth temperature is 850 DEG C～1000 DEG C, growth atmosphere is wet oxygen, growth time is 280～400 minutes.

In step S06, on the SOI substrate between described drain structure and source region structure, form Dual Gate Oxide structure, comprise thick grid oxygen 16 and the thin grid oxygen 25 of adjacent setting, described thin grid oxygen 25 is arranged on the dense injection region 7 of source region P type and the dense injection region 8 of N-type, and described thick grid oxygen 16 is arranged between described oxygen 17 and described thin grid oxygen 25;

On top silicon layer 3, apply one deck photoresist, utilize mask aligner to form the photoresist of patterning, to expose the silicon nitride layer in region of thick grid oxygen 16; Etch away the silicon nitride in the region of thick grid oxygen 16 by plasma method at dry quarter; Remove photoresist and the combination ashing method that removes photoresist of wet method is removed the photoresist outside the region of thick grid oxygen 16 of high voltage PMOS pipe by dry method; Grow in the grid oxygen boiler tube thick grid oxygen 16 of 300nm～800nm, growth temperature is 900 DEG C～1100 DEG C, and what adopt chloride gaseous state thing mixes the growth of oxychloride technique, and growth time is 50～100 minutes; Then, first do pre-treatment with diluted hydrofluoric acid, slight rinsing 10 seconds; Thereafter, then the remaining silicon nitride on top silicon layer 3 surfaces is all removed clean with the hot phosphoric acid of 120 DEG C～200 DEG C; Then add No. 1 liquid rinsing 120 seconds with diluted hydrofluoric acid, remove the second silicon oxide layer of the beneath 30nm～60nm of original silicon nitride; Grow in the most laggard grid oxygen boiler tube thin grid oxygen 25 of 12nm～36nm, the growth temperature of described thin grid oxygen 25 is 800 DEG C～950 DEG C, and what adopt chloride gaseous state thing mixes the growth of oxychloride technique, and growth time is 20～60 minutes; Thereby form the Dual Gate Oxide structure of high voltage PMOS pipe.

In step S07, on described thick grid oxygen and described oxygen, form grid structure, described grid structure comprises polysilicon gate and the polycrystalline field plate of adjacent setting, and described polysilicon gate is positioned on described thick grid oxygen, and described polycrystalline field plate is positioned on described oxygen;

Utilize the method polysilicon layer that deposit a layer thickness is 250nm～600nm on top silicon layer 3 surfaces of low-pressure chemical vapor phase deposition; Be 5.0E15～1.0E16ions/cm to implantation dosage in the polysilicon layer of this 250nm～600nm ²and the phosphonium ion that energy is 40KeV～100KeV; Then, apply one deck photoresist at above-mentioned polysilicon surface, utilize mask aligner in lithographic mask layer, to protect grid structure region, above-mentioned area of grid comprises the region of polycrystalline grid 22 and polycrystalline field plate 23, and polycrystalline grid 22 and polycrystalline field plate 23 are shorted together, the position just distributing is different, and polycrystalline grid 22 regions are positioned on thick grid oxygen 16, and polycrystalline field plate 23 regions are positioned on the field oxygen 17 being connected with thick grid oxygen 16; Etch away the polysilicon in region outside grid structure region by plasma method at dry quarter; Finally, remove photoresist by dry method and the combination ashing method that removes photoresist of wet method is removed the photoresist of grid structure.

In step S08, carry out ion implantation technology, in described drain region P type trap 13, form P type buffering area, drain region 14; At the 3rd silicon oxide layer of top silicon layer 3 superficial growth one deck 20nm～50nm, growth temperature is 800 DEG C～900 DEG C, and growth atmosphere is wet oxygen, and growth time is 30～60 minutes; Then, on the 3rd silicon oxide layer of this 20nm～50nm, apply one deck photoresist, the photoresist that utilizes mask aligner to form patterning forms the 3rd silicon oxide layer in the region of P type buffering area, drain region 14 with wish in exposure drain structure; Then be, 3.0E13～1.3E14ions/cm at the region implantation dosage of P type buffering area 14 ²and the boron ion that energy is 40KeV～100KeV; Injection finishes rear method of removing photoresist by wet method, removes above-mentioned 20nm～50nm the 3rd remaining photoresist above silicon oxide layer; Then, in diffusion furnace tube, carry out high annealing, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, annealing atmosphere is nitrogen, annealing time is 100～300 minutes, and wherein preferably, annealing temperature is 1000 DEG C～1150 DEG C, annealing atmosphere is nitrogen, and annealing time is 100～200 minutes.Complete after annealing, the concentration range of P type buffering area, described drain region 14 is 3 × 10 ¹⁷cm ^-3～9 × 10 ¹⁷cm ^-3, and concentration is with 6 × 10 ¹⁷cm ^-3for the best.

In step S09, carry out ion implantation technology, in described P type buffering area 14, form the dense injection region 15 of drain region P type, in N-type buffering area, described source region 10, form the dense injection region 7 of source region P type and the NXing Nong injection region, source region 8 of adjacent setting;

At the 4th silicon oxide layer of top silicon layer 3 superficial growth one deck 10nm～30nm, growth temperature is 800 DEG C～900 DEG C, and growth atmosphere is dry oxygen, and growth time is 20～60 minutes; On the 4th silicon oxide layer of described 10nm～30nm, applying one deck photoresist utilizes mask aligner in lithographic mask layer, to open the region of wish formation NXing Nong injection region, source region 8; Be 4.0E15～1.0E16ions/cm at the region implantation dosage of NXing Nong injection region, source region 8 ², and the energy arsenic ion that is 80KeV～120KeV; Then, remove photoresist by dry method and the combination ashing method that removes photoresist of wet method is removed the photoresist on the 4th silicon oxide layer of 10nm～30nm; Then, carry out high annealing in diffusion furnace tube, annealing temperature is 900 DEG C～1000 DEG C, and annealing atmosphere is the nitrogen oxygen atmosphere that nitrogen adds little oxygen, and annealing time is 30～60 minutes, completes after annealing, and the concentration range of NXing Nong injection region, source region 8 is 1 × 10 ²⁰cm ^-3～5 × 10 ²⁰cm ^-3, and concentration is with 3 × 10 ²⁰cm ^-3for the best; On four silicon oxide layer of described 10nm～30nm apply one deck photoresist, utilize mask aligner in lithographic mask layer, to open the 4th silicon oxide layer in the region of the wish formation dense injection region of the first kind, source region thereafter; The region that forms the dense injection region 7 of P type, source region and the dense injection region 15 of P type, drain region in wish, implantation dosage is the boron difluoride ion that 1.0E15～5.0E15ions/cm2 and energy are 80KeV～120KeV; Then remove photoresist by dry method and the combination ashing method that removes photoresist of wet method is removed the photoresist on the 4th silicon oxide layer of 10nm～30nm; Then in diffusion furnace tube, carry out high annealing, annealing temperature is 900 DEG C～1000 DEG C, and annealing atmosphere is nitrogen, and annealing time is 30～60 minutes, completes after annealing, and the concentration range of the dense injection region 7 of P type, source region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, wherein concentration is with 7 × 10 ¹⁹cm ^-3for the best, the concentration range of the dense injection region 15 of P type, described drain region is also 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, wherein concentration is with 7 × 10 ¹⁹cm ^-3for the best.

The technique manufacture process of the high-voltage P-type metal oxide transistor based on SOI substrate after completing steps S01～step S09 completes substantially; again in step S10; on described SOI substrate, deposition forms interlayer dielectric layer; and in dielectric layer, form contact hole, metal interconnecting wires; metallic aluminium field plate on described interlayer dielectric layer; aluminium field plate is positioned at described polycrystalline field plate top; finally form chip surface passivation protection layer, complete the whole preparation technology of the high-voltage P-type metal oxide transistor based on SOI substrate.

It is evident that, when the first kind in structure is changed to N-type, Second Type is changed to after P type, i.e. N-type transposition P type in above-described embodiment description, and P type transposition N-type, what show is the structure of N-type high-voltage MOS pipe, also within thought range of the present invention.

Although the present invention discloses as above with preferred embodiment; so it is not in order to limit the present invention; under any, in technical field, have and conventionally know the knowledgeable; without departing from the spirit and scope of the present invention; when doing a little change and retouching, therefore protection scope of the present invention is when being as the criterion depending on claims person of defining.

Claims

1. the high-voltage metal oxide semiconductor pipe based on SOI substrate, comprises,

SOI substrate;

Deep trench, is arranged in described SOI substrate;

Drain structure, be arranged in described SOI substrate, described drain structure ecto-entad comprises drain region first kind trap, first kind buffering area, drain region and the dense injection region of the drain region first kind that Second Type buffering area, drain region and concentration increase progressively successively, and the dense injection region of the first kind, described drain region is as drain electrode;

Source region structure, be arranged in described SOI substrate, comprise source region Second Type trap, be arranged in source region Second Type trap Second Type buffering area, source region, be arranged in the source region first kind trap of Second Type buffering area, described source region and the dense injection region of the source region first kind of adjacent setting and the dense injection region of source region Second Type, source region first kind trap is connected with the dense injection region of the first kind, described source region, and the dense injection region of the first kind, described source region and the dense injection region of source region Second Type are jointly as source electrode;

Field oxygen, is arranged in described drain structure, is positioned at a side of closing on source region structure;

Grid oxygen, is arranged between described oxygen and the dense injection region of the source region first kind;

Grid, comprises polysilicon gate and the polycrystalline field plate of adjacent setting, and described polysilicon gate is arranged on described grid oxygen, and described polycrystalline field plate is arranged on described oxygen;

Interlayer dielectric layer, is arranged on described SOI substrate surface.

2. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, the concentration of Second Type buffering area, described drain region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described drain region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of first kind buffering area, described drain region is 3 × 10 ¹⁷cm ^-3～9 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described drain region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3.

3. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, the concentration of described source region Second Type trap is 8 × 10 ¹⁵cm ^-3～4 × 10 ¹⁶cm ^-3, the concentration of Second Type buffering area, described source region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described source region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described source region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, the concentration of the dense injection region of Second Type, described source region is 1 × 10 ²⁰cm ^-3～5 × 10 ²⁰cm ^-3.

4. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, the thickness of described oxygen is 600nm～1500nm.

5. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, it is characterized in that, described grid oxygen adopts Dual Gate Oxide structure, comprise thin grid oxygen and the thick grid oxygen of adjacent setting, described thin grid oxygen is arranged on the dense injection region of the source region first kind and the dense injection region of source region Second Type, and described thick grid oxygen is arranged between described oxygen and described thin grid oxygen.

6. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 5, is characterized in that, the thickness of described thick grid oxygen is 300nm～800nm, and the thickness of described thin grid oxygen is 12nm～36nm.

7. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, described SOI substrate comprises the top silicon layer of substrate slice, buried oxidation layer and the Second Type of the first kind from bottom to up successively.

8. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, the degree of depth of described deep trench is 5um～20um.

9. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, has the filler that comprises silicon dioxide and unadulterated polysilicon in described deep trench.

10. the high-voltage metal oxide semiconductor pipe based on SOI substrate as claimed in claim 1, is characterized in that, on the described interlayer dielectric layer of described polycrystalline field plate top, is provided with aluminium field plate, and described aluminium field plate and described source electrode are electrical connected.

11. high-voltage metal oxide semiconductor pipes based on SOI substrate as described in any one in claim 1 to 10, is characterized in that, the described first kind is P type, and described Second Type is N-type; Or the described first kind is N-type, described Second Type is P type.

The manufacture method of 12. 1 kinds of high-voltage metal oxide semiconductor pipes based on SOI substrate, comprises,

SOI substrate is provided, and forms deep trench in described SOI substrate;

In described SOI substrate, form source region Second Type trap;

Between described oxygen and the dense injection region of the source region first kind, form grid oxygen;

Carry out ion implantation technology, in first kind buffering area, described drain region, form the dense injection region of the drain region first kind, the dense injection region of the source region first kind and the dense injection region of source region Second Type that in Second Type buffering area, described source region, form adjacent setting, the dense injection region of the first kind, described source region and the dense injection region of source region Second Type are jointly as source electrode;

On described SOI substrate, deposition forms interlayer dielectric layer.

The manufacture method of the 13. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, the concentration of Second Type buffering area, described drain region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described drain region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of first kind buffering area, described drain region is 3 × 10 ¹⁷cm ^-3～9 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described drain region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3.

The manufacture method of the 14. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, the concentration of described source region Second Type trap is 8 × 10 ¹⁵cm ^-3～4 × 10 ¹⁶cm ^-3, the concentration of Second Type buffering area, described source region is 2 × 10 ¹⁶cm ^-3～6 × 10 ¹⁶cm ^-3, the concentration of described source region first kind trap is 6 × 10 ¹⁶cm ^-3～1 × 10 ¹⁷cm ^-3, the concentration of the dense injection region of the first kind, described source region is 4 × 10 ¹⁹cm ^-3～1 × 10 ²⁰cm ^-3, the concentration of the dense injection region of Second Type, described source region is 1 × 10 ²⁰cm ^-3～5 × 10 ²⁰cm ^-3.

The manufacture method of the 15. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, the thickness of described oxygen is 600nm～1500nm.

The manufacture method of the 16. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, the degree of depth of described deep trench is 5um～20um.

The manufacture method of the 17. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, has the filler that comprises silicon dioxide and unadulterated polysilicon in described deep trench.

The manufacture method of the 18. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, is characterized in that, on the described interlayer dielectric layer of described polycrystalline field plate top, is provided with aluminium field plate, and described aluminium field plate and described source electrode are electrical connected.

The manufacture method of the 19. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, it is characterized in that, form the step of source region Second Type trap in described SOI substrate before, comprising: at described SOI Grown the first silicon oxide layer; Described the first silicon oxide layer, after forming the step of described drain region first kind trap and source region first kind trap, and is removed before forming the step of described oxygen.

The manufacture method of the 20. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 19, is characterized in that, the step that forms source region Second Type trap in described SOI substrate comprises:

On described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation source region Second Type trap;

The region dopant implant ion that forms source region Second Type trap to wish, described doping ion is phosphonium ion, implantation dosage is 1.0E12～6.0E12ions/cm ², Implantation Energy is 60KeV～120KeV;

Remove the photoresist of patterning;

Carry out high-temperature annealing process.

The manufacture method of the 21. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 19, is characterized in that, the step that forms Second Type buffering area, drain region and Second Type buffering area, source region comprises:

On described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation Second Type buffering area, drain region and Second Type buffering area, source region;

The region dopant implant ion that forms Second Type buffering area, drain region and Second Type buffering area, source region to wish, described doping ion is phosphonium ion, implantation dosage is 2.0E12～8.0E12ions/cm ², Implantation Energy is 60KeV～120KeV;

Remove the photoresist of patterning;

Carry out high-temperature annealing process.

The manufacture method of the 22. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 19, is characterized in that, the step that forms drain region first kind trap and source region first kind trap comprises:

On described the first silicon oxide layer, form the photoresist of patterning, expose first silicon oxide layer in the region of wish formation drain region first kind trap and source region first kind trap;

The region dopant implant ion that forms drain region first kind trap and source region first kind trap to wish, described doping ion is boron ion, implantation concentration is 5.0E12～3E13ions/cm ², Implantation Energy is 40KeV～100KeV;

Remove the photoresist of patterning;

Carry out high-temperature annealing process.

The manufacture method of 23. high-voltage metal oxide semiconductor pipes based on SOI substrate as described in any one in claim 20 to 22, it is characterized in that, the annealing temperature of described high-temperature annealing process is 1000 DEG C～1200 DEG C, and annealing atmosphere is nitrogen, and annealing time is 100～300 minutes.

The manufacture method of the 24. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 12, it is characterized in that, between the step of formation drain region first kind trap, source region first kind trap and a formation oxygen, comprise: on described SOI substrate, form successively the second silicon oxide layer and silicon nitride layer.

The manufacture method of the 25. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 24, is characterized in that, the step that forms an oxygen comprises:

On described silicon nitride layer, form the photoresist of patterning, expose the silicon nitride layer in a wish formation oxygen region;

Silicon nitride layer described in etching, exposure wish forms second silicon oxide layer in the region of an oxygen;

Remove the photoresist of patterning;

On the second silicon oxide layer exposing, form described oxygen.

The manufacture method of the 26. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 24, it is characterized in that, described grid oxygen adopts Dual Gate Oxide structure, comprise thin grid oxygen and the thick grid oxygen of adjacent setting, described thin grid oxygen is arranged on the dense injection region of the source region first kind and the dense injection region of source region Second Type, and described thick grid oxygen is arranged between described oxygen and described thin grid oxygen; The step of wherein said thick grid oxygen comprises:

On described silicon nitride layer, form the photoresist of patterning, exposure wish forms the silicon nitride layer in thick grid oxygen region;

Silicon nitride layer described in etching, exposure wish forms second silicon oxide layer in thick grid oxygen region;

Remove the photoresist of patterning;

Remove the second silicon oxide layer by hydrofluoric acid wet method, exposure wish forms the SOI substrate in thick grid oxygen region;

On the SOI substrate exposing, form described thick grid oxygen; The step of described thin grid oxygen comprises:

Wet method is removed the silicon nitride layer on described SOI substrate;

Wet method is removed described the second silicon oxide layer, and exposure wish forms the SOI substrate in thin grid oxygen region;

On the SOI substrate exposing, form described thin grid oxygen.

The manufacture method of the 27. high-voltage metal oxide semiconductor pipes based on SOI substrate as claimed in claim 26, it is characterized in that, the thickness of described thick grid oxygen is 300nm～800nm, in employing boiler tube, mixing oxychloride method forms, growth temperature is 900 DEG C～1100 DEG C, adopt the oxychloride technique of mixing of chloride gaseous state thing to grow, growth time is 50～100 minutes; The thickness of described thin grid oxygen is 12nm～36nm, adopts in boiler tube and mixes the formation of oxychloride method, and growth temperature is 800 DEG C～950 DEG C, adopts the oxychloride technique of mixing of chloride gaseous state thing to grow, and growth time is 20～60 minutes.

The manufacture method of 28. high-voltage metal oxide semiconductor pipes based on SOI substrate as described in any one in claim 12 to 22 or 24 to 27, is characterized in that, the described first kind is P type, and described Second Type is N-type; Or the described first kind is N-type, described Second Type is P type.