CN104241282A - Bi-directional gallium nitride switch and forming method thereof - Google Patents

Bi-directional gallium nitride switch and forming method thereof Download PDF

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Publication number
CN104241282A
CN104241282A CN201410273212.7A CN201410273212A CN104241282A CN 104241282 A CN104241282 A CN 104241282A CN 201410273212 A CN201410273212 A CN 201410273212A CN 104241282 A CN104241282 A CN 104241282A
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clamp portion
source
layer
substrate
grid
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桑迪普·R·巴尔
马修·塞内斯凯
纳韦恩·蒂皮尔内尼
戴维·I·安德森
萨米尔·彭德哈卡
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Texas Instruments Inc
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Texas Instruments Inc
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Abstract

The application relates to a bi-directional gallium nitride switch and a forming method thereof. A semiconductor device (400) includes a bidirectional GaN FET (406) formed on a non-insulating substrate (402). The semiconductor device further includes a first electrical clamp (420) connected between the substrate and a first source/drain node (416) of the bidirectional GaN FET, and a second electrical clamp connected between the substrate and a second source/drain node (418) of the bidirectional GaN FET. The first clamp and the second clamp are configured to bias the substrate at a lower voltage level of an applied bias to the first source/drain node and an applied bias to the second source/drain node, within an offset voltage of the relevant clamp.

Description

Two-way gallium nitride switch and forming method thereof
Technical field
The present invention relates to the field of semiconductor device.More particularly, the present invention relates to the gallium nitride field effect transistor in semiconductor device.
Background technology
The institute that gallium nitride field effect transistor (GaN FET) has for electric power switch application wants quality.GaN FET is integrated in the bidirectional switch in common substrate and can causes non-wanted trade-off of performance.
Summary of the invention
Below present simplification summary, to provide the basic comprehension to one or more aspect of the present invention.This summary is extensive overview ot of the present invention not, and has both been not intended to identify key or decisive element of the present invention, is also not intended to describe its scope.On the contrary, the main purpose of described summary presents concepts more of the present invention in simplified form, using as foreword in greater detail presented after a while.
Semiconductor device comprises the two-way GaN FET be formed on nonisulated substrate.Semiconductor device comprise further be connected to substrate and two-way GaN FET the first source/drain node between the first electric clamp portion and be connected to substrate and two-way GaN FET the second source/drain node between the second electric clamp portion.First clamp portion and the second clamp portion be configured in the offset voltage in relevant clamp portion by Substrate bias in the first source/drain node apply biased and lower voltage level in applying to the institute of the second source/drain node to be biased under.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of the Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.
Fig. 2 is the schematic diagram of another Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.
Fig. 3 is the schematic diagram of the another Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.
Fig. 4 A to Fig. 4 F is the cross section containing the Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.
Fig. 5 A to Fig. 5 E is the cross section containing another Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.
Fig. 6 is the cross section of the alternative form of the semiconductor device of Fig. 5 E.
Fig. 7 A to Fig. 7 D is the cross section containing the another Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.
Fig. 8 A and Fig. 8 B is the cross section containing two-way GaN FET, clamp portion and at least one pullup/pulldown Exemplary semiconductor devices along separate routes described in the continuous production phase.
Fig. 9 is the cross section containing two-way GaN FET, clamp portion and at least one pullup/pulldown another Exemplary semiconductor devices along separate routes.
Figure 10 is the cross section of the Exemplary semiconductor devices containing two-way GaN FET and two the clamp portion with multipair grid.
Embodiment
With reference to accompanying drawing, the present invention is described.Described figure not drawn on scale and provide it to be only in order to graphic extension the present invention.For graphic extension hereinafter with reference exemplary application describes several aspect of the present invention.Should be understood that statement various detail, relation and method are to provide the understanding of the present invention.But those skilled in the relevant art will readily recognize that, the present invention can be put into practice when not using one or more detail or use when other method.In other example, the well-known structure of non-detail display or operation are to avoid making the present invention fuzzy.The present invention is not limited to the illustrated order of action or event, because some actions can occur and/or occur with other action or event by different order simultaneously.In addition, all illustrated actions or event is not needed to implement according to method of the present invention.
Semiconductor device comprises the two-way GaN FET be formed on nonisulated substrate.Semiconductor device comprise further be connected to substrate and two-way GaN FET the first source/drain node between the first electric clamp portion and be connected to substrate and two-way GaN FET the second source/drain node between the second electric clamp portion.First clamp portion and the second clamp portion be configured in the offset voltage in relevant clamp portion by Substrate bias in the first source/drain node apply biased and lower voltage level in applying to the institute of the second source/drain node to be biased under.
For the object of this description, term " III-N " is interpreted as and refers to following semi-conducting material: wherein III element (that is, aluminium, gallium and indium and possibly boron) provides a part for the atom in described semi-conducting material and nitrogen-atoms provides the remainder of the atom in described semi-conducting material.The example of III-N semi-conducting material is gallium nitride, boron nitride gallium, aluminium gallium nitride alloy, indium nitride and indium nitride gallium aluminium.The term describing the element formula of material does not imply the specified chemical metering of element.III-N material can be write to represent a series of possibility stoichiometry by variable subscript.For example, aluminium gallium nitride alloy can be written as Al xga 1-xn and indium nitride gallium aluminium can be written as In xal yga 1-x-yn.For the object of this description, term GaN FET is interpreted as the field-effect transistor referring to and comprise III-N semi-conducting material.
Fig. 1 is the schematic diagram of the Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.Semiconductor device 100 comprises the two-way GaN FET102 be formed on nonisulated substrate 122.Two-way GaN FET102 has the first source/drain node 104 of the first source/drain terminal 106 being connected to semiconductor device 100 and is connected to second source/drain node 108 of the second source/drain terminal 110 of semiconductor device 100.Two-way GaN FET102 has the first grid 112 of the first grid terminal 114 being connected to semiconductor device 100 and is connected to the second grid 116 of second grid terminal 118 of semiconductor device 100.Semiconductor device 100 comprises the first clamp portion 120 be connected between the substrate node 122 of two-way GaN FET102 and the first source/drain node 104; In this example, the first clamp portion 120 is the first diode 120, and wherein the anode of the first diode 120 is connected to substrate node 122 and the negative electrode of the first diode 120 is connected to the first source/drain node 104.Semiconductor device 100 also comprises the second clamp portion 124 be connected between substrate node 122 and the second source/drain node 108; In this example, the second clamp portion 124 is the second diode 124, and its Anodic is connected to substrate node 122 and negative electrode is connected to the second source/drain node 108.
Semiconductor device 100 optionally comprises the first pullup/pulldown that leap first clamp portion 120 is connected in parallel along separate routes 126 and/or the second pullup/pulldown of being connected in parallel of the second clamp portion 124 of leap along separate routes 128; In this example, the first pullup/pulldown shunt 126 and the second pullup/pulldown shunt 128 are resistor 126 and 128.
In the first operator scheme of semiconductor device 100, the first source/drain terminal 106 can be biased to the current potential higher than the second source/drain terminal 110.The bias potential that second clamp portion 124 makes the current potential of substrate node 122 remain in the second source/drain terminal 110 adds the offset voltage in the second clamp portion 124.In this example, the offset voltage in the second clamp portion 124 is the forward bias turn-on voltage of the second diode 124.First clamp portion 120 is reverse biased in a first mode of operation, makes the current potential of substrate node 122 to being applied to the biased insensitive of the first source/drain terminal 106.
In the second operator scheme of semiconductor device 100, the second source/drain terminal 110 can be biased to the current potential higher than the first source/drain terminal 106.The bias potential that first clamp portion 120 makes the current potential of substrate node 122 remain in the first source/drain terminal 106 adds the offset voltage (that is, the forward bias turn-on voltage of the first diode 120) in the first clamp portion 120.Second clamp portion 124 is reverse biased in this second mode of operation, makes the current potential of substrate node 122 to being applied to the biased insensitive of the second source/drain terminal 110.
During the operation of semiconductor device 100, can occur: the current potential of substrate node 122 is pulled to both current potentials of current potential lower than the first source/drain terminal 106 and the second source/drain terminal 110.In this example, through the first pullup/pulldown along separate routes 126 and/or second pullup/pulldown along separate routes 128 electric current advantageously can accelerate the current potential of substrate node 122 to the transformation that will be worth, described will value is junior in the current potential of the first source/drain terminal 106 and the current potential of the second source/drain terminal 110.The resistance value of the first pullup/pulldown shunt 126 and the second pullup/pulldown shunt 128 can through selecting to make the electric current through shunt 126 and 128 maintain lower than wanted level.
Fig. 2 is the schematic diagram of another Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.Semiconductor device 200 comprises the two-way GaN FET202 be formed on nonisulated substrate 222.Two-way GaN FET202 has the first source/drain node 204 of the first source/drain terminal 206 being connected to semiconductor device 200 and is connected to second source/drain node 208 of the second source/drain terminal 210 of semiconductor device 200.Two-way GaN FET202 has the first grid 212 of the first grid terminal 214 being connected to semiconductor device 200 and is connected to the second grid 216 of second grid terminal 218 of semiconductor device 200.Semiconductor device 200 comprises the first clamp portion 220 be connected between the substrate node 222 of two-way GaN FET202 and the first source/drain node 204; In this example, first clamp portion 220 is with first enhancement-mode field-effect transistors (FET) 220 of diode mode configuration, and wherein the source electrode of a FET220 and grid are connected to substrate node 222 and the drain electrode of a FET220 is connected to first source/drain node 204 of two-way GaN FET102.Semiconductor device 200 also comprises the second clamp portion 224 be connected between substrate node 222 and the second source/drain node 208; In this example, the second clamp portion 224 is with the second enhancement mode FET224 of diode mode configuration, wherein the 2nd FET224 source electrode and grid is connected to substrate node 222 and the drain electrode of the 2nd FET224 is connected to the second source/drain node 208.
In the first operator scheme of semiconductor device 200, the first source/drain terminal 206 can be biased to the current potential higher than the second source/drain terminal 210.Second clamp portion 224 is in on-state and the bias potential making the current potential of substrate node 222 remain in the second source/drain terminal 210 adds the offset voltage in the second clamp portion 224.In this example, the offset voltage in the second clamp portion 224 is the threshold voltage of the 2nd FET224.First clamp portion 220 is in off state in a first mode of operation, makes the current potential of substrate node 222 to being applied to the biased insensitive of the first source/drain terminal 206.
In the second operator scheme of semiconductor device 200, the second source/drain terminal 210 can be biased to the current potential higher than the first source/drain terminal 206.The bias potential that first clamp portion 220 makes the current potential of substrate node 222 remain in the first source/drain terminal 206 adds the threshold voltage of a FET220, and the 2nd FET224 is in off state simultaneously.
Fig. 3 is the schematic diagram of the another Exemplary semiconductor devices containing the two-way GaN FET between source/drain node and substrate with clamp portion.Semiconductor device 300 comprises the two-way GaN FET302 be formed on nonisulated substrate 322.Two-way GaN FET302 has the first source/drain node 304 of the first source/drain terminal 306 being connected to semiconductor device 300 and is connected to second source/drain node 308 of the second source/drain terminal 310 of semiconductor device 300.Two-way GaN FET302 has the first grid 312 of the first grid terminal 314 being connected to semiconductor device 300 and is connected to the second grid 316 of second grid terminal 318 of semiconductor device 300.Semiconductor device 300 comprises the first clamp portion 320 be connected between the substrate node 322 of two-way GaN FET302 and the first source/drain node 304; In this example, the first clamp portion 320 is the first diode 320, and wherein the anode of the first diode 320 is connected to substrate node 322 and the negative electrode of the first diode 320 is connected to the first source/drain node 304.Semiconductor device 300 also comprises the second clamp portion 324 be connected between substrate node 322 and the second source/drain node 308; In this example, the second clamp portion 324 is the second diode 324, and its Anodic is connected to substrate node 322 and negative electrode is connected to the second source/drain node 308.
Semiconductor device 300 comprises the pullup/pulldown FET328 be along separate routes connected between substrate node 322 and the second source/drain node 308 further, for example, has the GaN FET328 of the threshold value identical with two-way GaN FET302.The gate node of pullup/pulldown shunt FET328 can be biased to the junior the current potential being applied to first grid terminal 314 and the current potential being applied to second grid terminal 318 from outside.Enhancement mode GaN FET328 can integrate with two-way GaN FET302.Pullup/pulldown along separate routes FET328 advantageously can accelerate the current potential of substrate node 322 to the transformation that will be worth, as described with reference to fig. 1.
Fig. 4 A to Fig. 4 E is the cross section containing the Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.With reference to figure 4A, at nonisulated substrate 402 (such as silicon substrate) upper formation semiconductor device 400.For example, substrate 402 can be monolithic high resistivity silicon wafer or as depicted in fig. 4a there is at top surface place high-resistivity wafer through heavily doped layer or other nonisulated configuration.Substrate 402 is formed III-N layer stacking 404 and thinks that two-way GaN FET406 provides applicable surface.For example, III-N layer stacking 404 can comprise be formed on substrate 402 be 100 nanometers to 300 nano aluminum nitrides mismatch separator, be 1 micron of Al to 7 micron thickness xga 1-xthe stacking resilient coating of N hierarchical layer (its at mismatch separator place be rich in aluminium and be rich in gallium at the top surface place of resilient coating) and be formed at described resilient coating may be the electricity isolated layers of 300 nanometers to the semi-insulating gallium nitride of 2000 nanometer.
III-N layer stacking 404 forms low defect layer 408.For example, low defect layer 408 can be the gallium nitride of 25 nanometers to 1000 nanometers.Low defect layer 408 can through being formed in case minimize may have adverse effect to electron mobility, low defect layer 408 may be caused to be doped carbon, iron or other dopant species (for example, have and are less than 10 17cm -3doping density) crystal defect.
Low defect layer 408 forms barrier layer 410.For example, barrier layer 410 can be the Al of 2 nanometers to 30 nanometers xga 1-xn or In xal yga 1-x-yn.For example, the composition of barrier layer 410 can be the aluminium nitride of 24% to 28% and the gallium nitride of 72% to 76%.Low defect layer 408 is formed barrier layer 410 and in low defect layer 408, lucky generation below barrier layer 410 can have (for example) 1 × 10 12cm -2to 2 × 10 13cm -2the two dimensional electron gas of electron density.Optional cap layer 412 can be formed on barrier layer 410.For example, cap layer 412 can be the gallium nitride of 2 nanometers to 5 nanometers.
Formed and patterning first passivation layer 414 in cap layer 412 (if existence) is upper above barrier layer 410.For example, the first passivation layer 414 can be the silicon dioxide that the use tetraethyl orthosilicate (TEOS) of 30 nanometers to 300 nanometers is formed by plasma enhanced chemical vapor deposition (PECVD) technique or the silicon nitride using dichlorosilane and ammonia to be formed by low-pressure chemical vapor deposition (LPCVD).For example, by shelter and use etch patterning first passivation layer 414 of reactive ion etching (RIE) technique with the region in the first source/drain node 416 for two-way GaN FET406 and for the region of its second source/drain node 418 in and in the region in the first Schottky diode clamp portion 420 for semiconductor device 400 and the region for its second Schottky diode clamp portion 422, remove the first passivation layer 414.
The place exposed by the first passivation layer 414 on cap layer 412 (if existence) above barrier layer 410 forms gate dielectric layer 424.For example, gate dielectric layer 424 can be the silicon nitride that by ald (ALD), LPCVD or pecvd process formed of 10 nanometers to 30 nanometers.In other version of this example, gate dielectric layer 424 can comprise one or more layer of silicon nitride, silicon dioxide, silicon oxynitride and/or aluminium oxide.
Formed above gate dielectric layer 424 and patterning grid/field plate layer to form the first grid 426 of two-way GaN FET406 and second grid 428 and to form field plate 430 around the region for the first Schottky diode clamp portion and the second Schottky diode clamp portion.For example, described grid/field plate layer can be 100 nanometers to the tungsten of 300 nanometers or titanium tungsten and by using etch process or stripping technology to carry out patterning.First grid 426 and second grid 428 can be overlapping with the first passivation layer 414, as depicted in fig. 4a.Similarly, field plate 430 can be overlapping with the first passivation layer 414.
The second passivation layer 432 is formed above first grid 426, second grid 428 and field plate 430.For example, the second passivation layer 432 can be 50 nanometers to the silicon dioxide formed by pecvd process of 500 nanometers or silicon nitride.Contact/diode etching mask 434 is formed to expose for the region of first source/drain node 416 of two-way GaN FET406 and the region for its second source/drain node 418 and the region in the first Schottky diode clamp portion 420 for semiconductor device 400 and the region for its second Schottky diode clamp portion 422 above the second passivation layer 432.For example, contact/diode etching mask 434 can comprise the photoresist formed by photoetching process.The contact holes that contact holes etch process has close to the bottom of low defect layer 408 barrier layer 410 from the second passivation layer 432, gate dielectric layer 424, cap layer 412 (if existence) and barrier layer 410 removing materials with formation.Contact/diode etching mask 434 is removed after completing contact holes etch process.
With reference to figure 4B, above the second passivation layer 432, form contact metal layer 436, it extends to for the region of first source/drain node 416 of two-way GaN FET406 and in the contact holes in the region of its second source/drain node 418 and contact berrier layer 410.For example, contact metal layer 436 can comprise the titanium and titanium nitride sublayer that are formed by sputter, ALD and/or chemical vapour deposition (CVD) (CVD).Source/drain contact etching mask 438 is formed to cover the region for the first source/drain node 416 and the region for the second source/drain node 418 and to expose for the region in the first Schottky diode clamp portion 420 of semiconductor device 400 and the region for its second Schottky diode clamp portion 422 above contact metal layer 436.
With reference to figure 4C, contact metal etch process removes the contact metal layer 436 in the region (comprising the contact holes in the region for the first Schottky diode clamp portion 420 and the region for the second Schottky diode clamp portion 422) exposed by source/drain contact etching mask 438, to form the first source/drain contact 440 in the contact holes in the region for the first source/drain node 416 and to form the second source/drain contact 442 in contact holes in the region for the second source/drain node 418.First source/drain contact 440 and the second source/drain contact 442 contact with barrier layer 410.Source/drain contact etching mask 438 is removed after completing contact metal etch process.After removing source/drain contact etching mask 438, perform annealing process, it heats the first source/drain contact 440 and the second source/drain contact 442 and barrier layer 410 and makes the first source/drain contact 440 and the second source/drain contact 442 be provided to the ohm contact of the two dimensional electron gas in low defect layer 408.Annealing process is performed during the contact holes in the region for the first Schottky diode clamp portion 420 and the region for the second Schottky diode clamp portion 422 is contactless metal.
With reference to figure 4D, above the second passivation layer 432, form field plate conducting body etching mask 441, to expose the region being used for field plate conducting body 443.Field plate conducting body etch process is from the second passivation layer 432 removing materials to expose field plate 430.Field plate conducting body etching mask 441 is removed after completing field plate conducting body etch process.
With reference to figure 4E, clamp portion conducting body etching mask 444 is formed, to expose the region being used for clamp portion conducting body inside the contact holes in the region for the first Schottky diode clamp portion 420 and the region for the second Schottky diode clamp portion 422 above the second passivation layer 432.For example, clamp portion conducting body etching mask 444 can be comprised the photoresist that formed by photoetching process and optionally comprise hard mask layer (displaying).Clamp portion conducting body etch process from stacking 404 removing materials of barrier layer 410, low defect layer 408 and III-N layer to be formed in the region for the first Schottky diode clamp portion 420 the first clamp portion via 446 of exposing substrate 402 and to be formed in the region for the second Schottky diode clamp portion 422 the second clamp portion via 448 exposing substrate 402.Clamp portion conducting body etching mask 444 is removed after completing clamp portion conducting body etch process.
With reference to figure 4F, formed and patterned interconnect metal above the second passivation layer 432, thus be implemented to the electrical connection of the first source/drain contact 440 to form the first source/drain cross tie part 450 and to be implemented to the electrical connection of the second source/drain contact 442 to form the second source/drain cross tie part 452.Patterned interconnecting metal also comprises the first clamp portion cross tie part 456, and its electrical connection being implemented to barrier layer 410 to form the first Schottky diode 454 and to extend in the first clamp portion via 446 to form the first clamp portion conducting body 457 being implemented to the electrical connection of substrate 402 in the region for the first Schottky diode clamp portion 420.Patterned interconnecting metal comprises the second clamp portion cross tie part 460 further, and its electrical connection being implemented to barrier layer 410 to form the second Schottky diode 458 and to extend in the second clamp portion via 448 to form the second clamp portion conducting body 461 being implemented to the electrical connection of substrate 402 in the region for the second Schottky diode clamp portion 422.First Schottky diode 454 and the first clamp portion cross tie part 456 provide the first Schottky diode clamp portion 420 of semiconductor device 400.Similarly, the second Schottky diode 458 and the second clamp portion cross tie part 460 provide the second Schottky diode clamp portion 422 of semiconductor device 400.
Fig. 5 A to Fig. 5 E is the cross section containing another Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.With reference to figure 5A, at nonisulated substrate 502 (such as silicon substrate) upper formation semiconductor device 500.Form III-N layer stacking 504 on the substrate 502 and think that two-way GaN FET506 provides applicable surface.III-N layer stacking 504 forms low defect layer 508.Low defect layer 508 forms barrier layer 510.Low defect layer 508 is formed barrier layer 510 and in low defect layer 508, just can produce two dimensional electron gas below barrier layer 510.Optional cap layer 512 can be formed on barrier layer 510.For example, the III-N layer that III-N layer is stacking 504, low defect layer 508, barrier layer 510 and cap layer 512 can be similar to Fig. 4 A is respectively stacking 404, low defect layer 408, barrier layer 410 and cap layer 412.
Isolation etch process removes cap layer 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504 at the areas outside for two-way GaN FET506, thus may expose substrate 502.For example, described isolation etch process can use the etching mask of photoresist, follow-up then wet etch process.Cap layer 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504 is removed in the part in the region in the FET clamp portion 520 for semiconductor device 500 and in the part in the region for its 2nd FET clamp portion 522.
With reference to figure 5B, above cap layer 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504, form the first passivation layer 514, its to overlap onto on substrate 502 in case covering cap cap rock 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504 once by side that the isolation etch process of Fig. 5 A exposes.First passivation layer 514 can be formed as conformal layer, makes to be at least 50% of the thickness of the first passivation layer 514 on the substrate 502 and on cap layer 512 at the thickness of first passivation layer 514 in exposed side of cap layer 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504.
Patterning first passivation layer 514 so as the region of the first source/drain node 516 for two-way GaN FET506 and for the region of its second source/drain node 518 in and above barrier layer 510 for the part in the region in a FET clamp portion 520 in and above barrier layer 510 for the part in the region in the 2nd FET clamp portion 522 in remove the first passivation layer 514.The first passivation layer 514 is removed through exposed side not from cap layer 512, barrier layer 510, low defect layer 508 and III-N layer stacking 504.
The place exposed by the first passivation layer 514 on cap layer 512 (if existence) above the first passivation layer 514 and above barrier layer 510 forms gate dielectric layer 524.For example, gate dielectric layer 524 can be formed as described with reference to figure 4.
Recess 563 is formed and it extends to in the barrier layer 510 in the region of the grid in a FET clamp portion 520 and the 2nd FET clamp portion 522 through gate dielectric layer 524 and cap layer 512.Formed above gate dielectric layer 524 and patterning grid/field plate layer to form the first grid 526 of two-way GaN FET506 and second grid 528 and to be formed for the enhancement mode first clamp portion grid 564 in the region in a FET clamp portion 520 and for the enhancement mode second clamp portion grid 566 in the region in the 2nd FET clamp portion 522.Enhancement mode first clamp portion grid 564 and enhancement mode second clamp portion grid 566 to extend in recess 563 and overlapping with the first passivation layer 514 being adjacent to recess 563.
With reference to figure 5C, above first grid 526, second grid 528, first clamp portion grid 564 and the second clamp portion grid 566, form the second passivation layer 532 and overlapping with substrate 502 in its region in the region for a FET clamp portion 520 and for the 2nd FET clamp portion 522.For example, the second passivation layer 532 can be formed as described with reference to figure 4.
Perform contact etch technique, its part removing the second passivation layer 532, gate dielectric layer 524, cap layer 512 and barrier layer 510 to form two dimensional electron gas (2DEG) contact holes 562 in the region for the first source/drain node 516 and the region for the second source/drain node 518 and in the region for a FET clamp portion 520 and the region for the 2nd FET clamp portion 522.Described contact etch technique also forms the substrate conducting body 568 through the second passivation layer 532, gate dielectric layer 524 and the first passivation layer 514 to expose substrate 502 in the region in the region for a FET clamp portion 520 and for the 2nd FET clamp portion 522.Described contact etch technique can form first grid contact conducting body 570 through the second passivation layer 532 further to expose the first clamp portion grid 564 and to be formed through the second grid contact conducting body 572 of the second passivation layer 532 to expose the second clamp portion grid 566.Or, first grid contact conducting body 570 and second grid contact conducting body 572 can be individually formed in another etch process.For example, contact etch technique is performed by the etching mask of formation photoresist, follow-up then Wet-type etching.
With reference to figure 5D, above the second passivation layer 532, form the contact metal layer extended in 2DEG contact holes 562 and substrate conducting body 568 and be patterned subsequently to form the first source/drain contact 540 in the 2DEG contact holes 562 in the region of the first source/drain node 516, for the second source/drain contact 542 in the 2DEG contact holes 562 in the region of the second source/drain node 518, for the contact, FET clamp portion 574 in the 2DEG contact holes 562 in the region in a FET clamp portion 520 and for the 2nd contact, FET clamp portion 576 in the 2DEG contact holes 562 in the region in the 2nd FET clamp portion 522 and optionally for the first contact, substrate clamp portion 578 in the substrate conducting body 568 in the region in a FET clamp portion 520 and for the second contact, substrate clamp portion 580 in the substrate conducting body 568 in the region in the 2nd FET clamp portion 522.Subsequently, perform annealing process, it heats the first source/drain contact 540, second source/drain contact 542, contact, FET clamp portion the 574, the 2nd contact, FET clamp portion 576 and a barrier layer 510, makes the first source/drain contact 540, second source/drain contact 542, ohm contact that a contact, FET clamp portion 576, contact, FET clamp portion the 574, the 2nd is provided to the two dimensional electron gas in low defect layer 508.
With reference to figure 5E, formed and patterned interconnect metal above the second passivation layer 532, thus be implemented to the electrical connection of the first source/drain contact 540 to form the first source/drain cross tie part 550 and to be implemented to the electrical connection of the second source/drain contact 542 to form the second source/drain cross tie part 552.Patterned interconnecting metal also comprises the first clamp portion cross tie part 556, and it realizes by first grid contact conducting body 570 to the first clamp portion grid 564, to a contact, FET clamp portion 574 and by the electrical connection of the first contact, substrate clamp portion 578 (if existence) to substrate 502.Patterned interconnecting metal comprises the second clamp portion cross tie part 560 further, and it realizes by second grid contact conducting body 572 to the second clamp portion grid 566, to the 2nd contact, FET clamp portion 576 and by the electrical connection of the second contact, substrate clamp portion 580 (if existence) to substrate 502.First contact, substrate clamp portion, clamp portion grid the 564, the one contact, FET clamp portion 574, first 578 and the first clamp portion cross tie part 556 provide the first clamp portion 520 of semiconductor device 500.Similarly, the second contact, substrate clamp portion, clamp portion grid the 566, the 2nd contact, FET clamp portion 576, second 580 and the second clamp portion cross tie part 560 provide the second clamp portion 522.
Fig. 6 is the cross section of the alternative form of the semiconductor device 500 of Fig. 5 E.Enhancement mode first clamp portion grid 564 and enhancement mode second clamp portion grid 566 are formed by p-type III-N material (such as p-type gallium nitride) and are formed on cap layer 512.Gate dielectric layer 524 is formed and coverage enhancement pattern first clamp portion grid 564 and enhancement mode second clamp portion grid 566 after formation enhancement mode first clamp portion grid 564 and enhancement mode second clamp portion grid 566.
Fig. 7 A to Fig. 7 D is the cross section containing the another Exemplary semiconductor devices in two-way GaN FET and clamp portion described in the continuous production phase.With reference to figure 7A, at Semiconductor substrate 702 (such as p-type silicon substrate) upper formation semiconductor device 700.Substrate 702 has the first clamp portion diode 782 of the form in diffusion n-type district 782 in the region in the first diode clamp portion 720 for semiconductor device 700 and has the second clamp portion diode 784 of form in diffusion n-type district 784 in the region in the second diode clamp portion 722 for semiconductor device 700.The anode of the first clamp portion diode 782 and the anode of the second clamp portion diode 784 are directly electrically connected to a part for substrate 702 below GaN FET706.Form extra N-shaped diffusion region 785 close to the first clamp portion diode 782 and the second clamp portion diode 784 so as by biased be greatly applied to semiconductor device 700 time in substrate 702, provide depletion region.
Form III-N layer stacking 704 over the substrate 702 and think that two-way GaN FET706 provides applicable surface.III-N layer stacking 704 forms low defect layer 708.Low defect layer 708 forms barrier layer 710.Low defect layer 708 is formed barrier layer 710 and in low defect layer 708, just can produce two dimensional electron gas below barrier layer 710.Optional cap layer 712 can be formed on barrier layer 710.For example, the III-N layer that III-N layer is stacking 704, low defect layer 708, barrier layer 710 and cap layer 712 can be similar to Fig. 4 A is respectively stacking 404, low defect layer 408, barrier layer 410 and cap layer 412.
With reference to figure 7B, in barrier layer 710 and above form two-way GaN FET706, for example, as with reference to figure 4A to Fig. 4 E or with reference to described by figure 5A to Fig. 5 E.Two-way GaN FET706 comprises first grid 726 and second grid 728 and the first source/drain contact 740 and the second source/drain contact 742.Two-way GaN FET706 comprises the first source/drain cross tie part 750 of the electrical connection being implemented to the first source/drain contact 740 further and is implemented to the second source/drain cross tie part 752 of electrical connection of the second source/drain contact 742.First source/drain cross tie part 750 comprises for the first clamp portion joint sheet 786 in the region in the first diode clamp portion 720; Second source/drain cross tie part 752 comprises for the second joint sheet 788 in the region in the second diode clamp portion 722.
With reference to figure 7C, isolation etch process removes cap layer 712, barrier layer 710, low defect layer 708 and III-N layer stacking 704 at the areas outside for two-way GaN FET706, thus exposes substrate 702 at the first clamp portion diode 782 and the second diode 784 place of clamp portion.For example, can as performed isolation etch process described by with reference to figure 5A.
With reference to figure 7D, formed the first electrical connection 790 (for example, as in Fig. 7 D the line described engage 790) the first clamp portion joint sheet 786 of the first source/drain cross tie part 750 to be connected to the negative electrode of the first clamp portion diode 782.Form the second electrical connection 792 the second clamp portion joint sheet 788 of the second source/drain cross tie part 752 to be connected to the negative electrode of the second clamp portion diode 784.First clamp portion joint sheet 786, first electrical connection 790 and the first clamp portion diode 782 provide the first clamp portion 720 of semiconductor device 700.Second clamp portion joint sheet 788, second electrical connection 792 and the second clamp portion diode 784 provide the second clamp portion 722.
Fig. 8 A and Fig. 8 B is the cross section containing two-way GaN FET, clamp portion and at least one pullup/pulldown Exemplary semiconductor devices along separate routes described in the continuous production phase.With reference to figure 8A, at nonisulated substrate 802 (such as silicon substrate) upper formation semiconductor device 800.Substrate 802 is formed III-N layer stacking 804 and thinks that two-way GaN FET806 provides applicable surface.III-N layer stacking 804 forms low defect layer 808.Low defect layer 808 forms barrier layer 810.Low defect layer 808 is formed barrier layer 810 and in low defect layer 808, just can produce two dimensional electron gas below barrier layer 810.Optional cap layer 812 can be formed on barrier layer 810.For example, the III-N layer that III-N layer is stacking 804, low defect layer 808, barrier layer 810 and cap layer 812 can be similar to Fig. 4 A is respectively stacking 404, low defect layer 408, barrier layer 410 and cap layer 412.
In barrier layer 810 and above form two-way GaN FET806, for example, as with reference to figure 4A to Fig. 4 E or with reference to described by figure 5A to Fig. 5 E.Two-way GaN FET806 comprises first grid 826 and second grid 828 and the first source/drain contact 840 and the second source/drain contact 842.
Semiconductor device 800 comprises pullup/pulldown shunt 894 further, and in this example, it is the resistor 894 of the resistor body had in the two dimensional electron gas in low defect layer 808.First source/drain contact 840 is provided to the source side resistor device contact of resistor body.Pullup/pulldown shunt 894 comprises the substrate side resistor contact 896 of the form in the ohm contact 896 to resistor body; Substrate side resistor contact 896 can be formed with the first source/drain contact 840 and the second source/drain contact 842 simultaneously.
With reference to figure 8B, form along separate routes conducting body 898 by conducting body etch process, described technique is from stacking 804 removing materials of barrier layer 810, low defect layer 808 and III-N layer and expose substrate 802.The mode that can be similar to the first clamp portion via 446 forms conducting body 898 along separate routes, described by with reference to figure 4D.Form the first source/drain cross tie part 850 being implemented to the electrical connection of the first source/drain contact 840, and form the second source/drain cross tie part 852 being implemented to the electrical connection of the second source/drain contact 842.Cross tie part 899 along separate routes is side by side formed with the first source/drain cross tie part 850 and the second source/drain cross tie part 852; Cross tie part 899 is implemented to the electrical connection of substrate side resistor contact 896 and extends in shunt conducting body 898 to be implemented to the electrical connection of substrate 802 along separate routes.The the first clamp portion (displaying) crossing over semiconductor device 800 is connected in parallel pullup/pulldown shunt 894.Semiconductor device 800 can comprise another pullup/pulldown shunt that leap second clamp portion is connected in parallel.Pullup/pulldown along separate routes 894 is formed as having resistor body in the two dimensional electron gas in low defect layer 808, side by side forms substrate side resistor contact 896 with the first source/drain contact 840 and the second source/drain contact 842 and side by side form with the first source/drain cross tie part 850 and the second source/drain cross tie part 852 cost of manufacture and the complexity that shunt cross tie part 899 advantageously can reduce semiconductor device 800.
Fig. 9 is the cross section containing two-way GaN FET, clamp portion and at least one pullup/pulldown another Exemplary semiconductor devices along separate routes.At nonisulated substrate 902 (such as silicon substrate) upper formation semiconductor device 900.Substrate 902 is included in for the shunt separator 903 in the region of shunt 994.For example, separator 903 can be the field oxide 903 formed from (STI) technique by shallow trench isolation along separate routes.
Substrate 902 is formed III-N layer stacking 904 and thinks that two-way GaN FET906 provides applicable surface.III-N layer stacking 904 forms low defect layer 908.Low defect layer 908 forms barrier layer 910.Low defect layer 908 is formed barrier layer 910 and in low defect layer 908, just can produce two dimensional electron gas below barrier layer 910.Optional cap layer 912 can be formed on barrier layer 910.For example, the III-N layer that III-N layer is stacking 904, low defect layer 908, barrier layer 910 and cap layer 912 can be similar to Fig. 4 A is respectively stacking 404, low defect layer 408, barrier layer 410 and cap layer 412.
In barrier layer 910 and above form two-way GaN FET906, for example, as with reference to figure 4A to Fig. 4 E or with reference to described by figure 5A to Fig. 5 E.Two-way GaN FET906 comprises first grid 926 and second grid 928 and the first source/drain contact 940 and the second source/drain contact 942.First source/drain cross tie part 950 comprises for the joint sheet 986 along separate routes of first in the region of shunt 994.Isolation etch process removes cap layer 912, barrier layer 910, low defect layer 908 and III-N layer stacking 904 at the areas outside for two-way GaN FET906, thus exposes the shunt separator 903 in substrate 902.For example, can as performed isolation etch process described by with reference to figure 5A.
By-passed resistor 995 is formed above shunt separator 903.For example, by-passed resistor 995 can comprise polysilicon (being commonly referred to polysilicon (polysilicon)) resistor body.Formed the first electrical connection 990 (for example, line as depicted in fig. 9 engages 990) with by first of the first source/drain cross tie part 950 along separate routes joint sheet 986 be connected to the first end of by-passed resistor 995.Form the second electrical connection 991 (for example, another line engages 991) the second end of by-passed resistor 995 is connected to substrate 902, can by the joint sheet 993 on substrate 902.The the first clamp portion (displaying) crossing over semiconductor device 900 is connected in parallel pullup/pulldown shunt 994.Semiconductor device 900 can comprise another pullup/pulldown shunt that leap second clamp portion is connected in parallel.Substrate 902 is formed by-passed resistor 995 can advantageously promote pullup/pulldown 994 to be integrated in the version of semiconductor device 900 along separate routes, wherein by isolation etch exposed substrate 902.
Figure 10 is the cross section of the Exemplary semiconductor devices containing two-way GaN FET and two the clamp portion with multipair grid.At nonisulated substrate 1002 (such as silicon substrate) upper formation semiconductor device 1000.Substrate 1002 is formed III-N layer stacking 1004 and thinks that two-way GaN FET1006 provides applicable surface.III-N layer stacking 1004 forms low defect layer 1008.Low defect layer 1008 forms barrier layer 1010.Low defect layer 1008 is formed barrier layer 1010 and in low defect layer 1008, just can produce two dimensional electron gas below barrier layer 1010.Optional cap layer 1012 can be formed on barrier layer 1010.Gate dielectric layer 1024 can be formed in cap layer 1012 (if existence) is upper above barrier layer 1010.For example, the III-N layer that III-N layer is stacking 1004, low defect layer 1008, barrier layer 1010, cap layer 1012 and gate dielectric layer 1024 can be similar to Fig. 4 A is respectively stacking 404, low defect layer 408, barrier layer 410, cap layer 412 and gate dielectric layer 424.
In this example, GaN FET1006 comprises the Multi-instance of first grid and second grid and the corresponding instance of the first source/drain contact and the second source/drain contact.First example 1042 of the first example 1026 of the first example 1040 that GaN FET1006 comprises the first source/drain contact and the first grid that formed close to the first example 1040 of the first source/drain contact, the first example 1028 of second grid be separated with the first example 1026 of first grid by the first example 1035 of the drift region of GaN FET1006 and the second source/drain contact close to the first example 1028 of second grid.
GaN FET1006 comprises the second example 1041 of the second example 1027 of the second grid that the first example 1042 close to the second source/drain contact is formed, the second example 1029 of first grid be separated with the second example 1027 of second grid by the second example 1037 of drift region and the first source/drain contact close to the second example 1029 of first grid.
GaN FET1006 comprises the second example 1043 of the 3rd example 1031 of the first grid that the second example 1041 close to the first source/drain contact is formed, the 3rd example 1033 of second grid be separated with the 3rd example 1031 of first grid by the 3rd example 1039 of drift region and the second source/drain contact close to the 3rd example 1033 of second grid further.
Semiconductor device 1000 comprise can (for example) according in example described herein any one formed the first clamp portion 1020 and the second clamp portion 1022.First clamp portion 1020 and the second clamp portion 1022 are depicted as the Schottky diode having and arrive the substrate conducting body of substrate through III-N layer stacking 1004 by Figure 10, described by with reference to figure 4A to Fig. 4 E.
First example 1040 of the first clamp portion 1020, first source/drain contact and the second example 1041 of the first source/drain contact are electrically coupled to the first source/drain terminal 1001 of semiconductor device 1000, for example, by the cross tie part of semiconductor device 1000.First example 1042 of the second clamp portion 1022, second source/drain contact and the second example 1043 of the second source/drain contact are electrically coupled to the second source/drain terminal 1003 of semiconductor device 1000 similarly.3rd example 1031 of the first example 1026 of first grid, the second example 1029 of first grid and first grid is electrically coupled to the first grid terminal 1014 of semiconductor device 1000.3rd example 1033 of the first example 1028 of second grid, the second example 1027 of second grid and second grid is electrically coupled to the second grid terminal 1018 of semiconductor device 1000.Form the semiconductor device 1000 with the Multi-instance of first grid and second grid and the corresponding instance of the first source/drain contact and the second source/drain contact and two clamp portions and advantageously can be wanted current density by GaN FET1006 provides, the institute being simultaneously provided for semiconductor device 1000 wants region.
Although described various embodiment of the present invention above, only should be understood that described embodiment by way of example and non-limited way presents.Can make many changes according to disclosure herein to disclosed embodiment, this does not deviate from the spirit or scope of the present invention.Therefore, range of the present invention and scope should not limit by any one in above-described embodiment.But scope of the present invention should define according to appended claims and equivalent thereof.

Claims (20)

1. a semiconductor device, it comprises:
Two-way gallium nitride field effect transistor GaN FET, it is formed in the III-N layer of types of flexure, and described substrate is uninsulated, and described two-way GaN FET has the first source/drain node and the second source/drain node;
First clamp portion, it is connected between described first source/drain node and described substrate; And
Second clamp portion, it is connected between described second source/drain node and described substrate.
2. semiconductor device according to claim 1, wherein:
Described first clamp portion comprises the first Schottky diode and is connected to the first clamp portion cross tie part of interconnecting metal of described first source/drain node, and described first clamp portion cross tie part contacts the barrier layer of described III-N layer to form described first Schottky diode; And
Described second clamp portion comprises the second Schottky diode and is connected to the second clamp portion cross tie part of described interconnecting metal of described second source/drain node, and described second clamp portion cross tie part contacts described barrier layer to form described second Schottky diode.
3. semiconductor device according to claim 1, wherein:
Described first clamp portion comprises the first enhancement mode GaN FET and is connected to the first clamp portion cross tie part of interconnecting metal of the first clamp portion grid of described first enhancement mode GaN FET, and described first clamp portion cross tie part is electrically coupled to described substrate; And
Described second clamp portion comprises the second enhancement mode GaN FET and is connected to the second clamp portion cross tie part of interconnecting metal of the second clamp portion grid of described second enhancement mode GaN FET, and described second clamp portion cross tie part is electrically coupled to described substrate.
4. semiconductor device according to claim 1, wherein:
Described substrate comprises semi-conducting material;
Described first clamp portion comprises the first diode be placed in the described semi-conducting material of described substrate, makes the anode of described first diode be electrically coupled to described substrate and the cathodic electricity of described first diode is coupled to described first source/drain node; And
Described second clamp portion comprises the second diode be placed in the described semi-conducting material of described substrate, makes the anode of described second diode be electrically coupled to described substrate and the cathodic electricity of described second diode is coupled to described second source/drain node.
5. semiconductor device according to claim 1, wherein:
Described first clamp portion comprises the first clamp portion conducting body extending to described substrate through described III-N layer; And
Described second clamp portion comprises the second clamp portion conducting body extending to described substrate through described III-N layer.
6. semiconductor device according to claim 1, wherein:
The first clamp portion cross tie part of described substrate is extended to above the edge that described first clamp portion is included in described III-N layer; And
The second clamp portion cross tie part of described substrate is extended to above the described edge that described second clamp portion is included in described III-N layer.
7. semiconductor device according to claim 1, it comprises the pullup/pulldown shunt of crossing over described first clamp portion and being connected in parallel further.
8. semiconductor device according to claim 7, wherein said pullup/pulldown comprises resistor, in the two dimensional electron gas of described resistor in the barrier layer of described III-N layer between substrate side resistor contact and described first source/drain node along separate routes.
9. semiconductor device according to claim 7, wherein said pullup/pulldown comprises enhancement mode GaNFET along separate routes.
10. semiconductor device according to claim 1, wherein:
Described first source/drain node of described two-way GaN FET and described second source/drain node comprise a series of alternative embodiment of described first source/drain node and described second source/drain node; And
Described two-way GaN FET comprises first grid between every a pair alternative embodiment of described first source/drain node and described second source/drain node and second grid, wherein said first grid close to the described example of described first source/drain node and described second grid close to the described example of described second source/drain node.
11. 1 kinds of methods forming semiconductor device, it comprises the following steps:
There is provided substrate, described substrate is uninsulated;
Square one-tenth III-N layer over the substrate;
The first grid of two-way GaN FET is formed above described III-N layer;
The second grid of described two-way GaN FET is formed above described III-N layer;
Form first source/drain contact of described two-way GaN FET close to described first grid in described III-N layer;
Form second source/drain contact of described two-way GaN FET close to described second grid in described III-N layer;
Form the first clamp portion be connected between described first source/drain contact and described substrate; And
Form the second clamp portion be connected between described second source/drain contact and described substrate.
12. methods according to claim 11, wherein:
The step in the described first clamp portion of described formation comprises: form the first clamp portion cross tie part being connected to the interconnecting metal of described first source/drain contact, make described first clamp portion cross tie part contact the barrier layer of described III-N layer to form first Schottky diode in described first clamp portion; And
The step in the described second clamp portion of described formation comprises: form the second clamp portion cross tie part being connected to the interconnecting metal of described second source/drain contact, make described second clamp portion cross tie part contact described barrier layer to form second Schottky diode in described second clamp portion.
13. methods according to claim 11, wherein:
The step in the described first clamp portion of described formation comprises: form the first clamp portion grid of the first enhancement mode GaN FET and the first clamp portion cross tie part of formation interconnecting metal, make the first clamp portion cross tie part be connected to described first clamp portion grid and be coupled to described substrate; And
The step in the described second clamp portion of described formation comprises: form the second clamp portion grid of the second enhancement mode GaN FET and form the second clamp portion cross tie part of described interconnecting metal, making the second clamp portion cross tie part be connected to described second clamp portion grid and be coupled to described substrate.
14. methods according to claim 11, wherein:
Described substrate comprises semi-conducting material;
The step in the described first clamp portion of described formation comprises: in the described semi-conducting material of described substrate, form the first diode be electrically coupled to described substrate to make the anode of described first diode, and is electrically connected with being formed between described first source/drain contact at the negative electrode of described first diode; And
The step in the described second clamp portion of described formation comprises: in the described semi-conducting material of described substrate, form the second diode be electrically coupled to described substrate to make the anode of described second diode, and is electrically connected with being formed between described second source/drain contact at the negative electrode of described second diode.
15. methods according to claim 11, wherein:
The step in the described first clamp portion of described formation comprises: remove III-N material to form the first clamp portion via exposing described substrate from described III-N layer, and in described first clamp portion via, form the first clamp portion conducting body extending to described substrate through described III-N layer; And
The step in the described second clamp portion of described formation comprises: remove III-N material to form the second clamp portion via exposing described substrate from described III-N layer, and in described second clamp portion via, form the second clamp portion conducting body extending to described substrate through described III-N layer.
16. methods according to claim 11, wherein:
The step in the described first clamp portion of described formation comprises: remove III-N material to expose described substrate from described III-N layer, above the edge of described III-N layer, form dielectric material layer, and extend to the first clamp portion cross tie part of described substrate above the described edge being formed in described III-N layer above described dielectric material layer; And
The step in the described second clamp portion of described formation comprises: the second clamp portion cross tie part extending to described substrate above the described edge being formed in described III-N layer above described dielectric material layer.
17. methods according to claim 11, it comprises formation pullup/pulldown along separate routes further, be electrically connected with being formed between described first source/drain contact along separate routes in described pullup/pulldown, and be electrically connected with being formed between described substrate in described pullup/pulldown shunt.
18. methods according to claim 17, the described pullup/pulldown of wherein said formation step along separate routes comprises: the substrate side resistor contact being formed into the two dimensional electron gas in the barrier layer of described III-N layer, to form resistor in described two dimensional electron gas between described substrate side resistor contact and described first source/drain contact.
19. methods according to claim 17, the described pullup/pulldown of wherein said formation step along separate routes comprises: the enhancement mode grid forming GaN FET above the barrier layer of described III-N layer.
20. methods according to claim 12, wherein:
Described first source/drain contact of described formation and the step forming described second source/drain contact comprise: a series of alternative embodiment forming described first source/drain contact and described second source/drain contact; And
Described method comprises the step of first grid and the second grid formed between every a pair alternative embodiment of described first source/drain contact and described second source/drain contact further, described first grid is formed close to the described example of described first source/drain contact, and described second grid is formed close to the described example of described second source/drain contact.
CN201410273212.7A 2013-06-20 2014-06-18 Bi-directional gallium nitride switch and forming method thereof Pending CN104241282A (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Families Citing this family (13)

* Cited by examiner, † Cited by third party
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US9379620B2 (en) 2014-10-02 2016-06-28 Navitas Semiconductor Inc. Zero voltage soft switching scheme for power converters
US9985626B2 (en) * 2015-01-30 2018-05-29 Navitas Semiconductor, Inc. Bidirectional GaN switch with built-in bias supply and integrated gate drivers
US9818854B2 (en) * 2015-04-30 2017-11-14 Semiconductor Components Industries, Llc Electronic device including a bidirectional HEMT
US9548731B2 (en) 2015-06-16 2017-01-17 Tagore Technology, Inc. High performance radio frequency switch
US10270239B2 (en) 2016-06-15 2019-04-23 Texas Instruments Incorporated Overvoltage protection and short-circuit withstanding for gallium nitride devices
FR3053832B1 (en) * 2016-07-05 2018-11-30 Renault S.A.S METHOD FOR MANUFACTURING FIELD EFFECT HETEROJUNCTION TRANSISTOR AND CORRESPONDING TRANSISTOR
JP6815509B2 (en) * 2016-11-24 2021-01-20 ヴィジック テクノロジーズ リミテッド Power supply device for high voltage and high current switching
US10224924B1 (en) 2017-08-22 2019-03-05 Infineon Technologies Austria Ag Bidirectional switch with passive electrical network for substrate potential stabilization
US11862630B2 (en) * 2018-04-23 2024-01-02 Infineon Technologies Austria Ag Semiconductor device having a bidirectional switch and discharge circuit
US10840798B1 (en) 2018-09-28 2020-11-17 Dialog Semiconductor (Uk) Limited Bidirectional signaling method for high-voltage floating circuits
US11594626B2 (en) 2021-02-05 2023-02-28 Globalfoundries U.S. Inc. Bidirectional switches with active substrate biasing
KR20240027679A (en) 2021-06-28 2024-03-04 엔페이즈 에너지, 인코포레이티드 Gallium nitride bidirectional high electron mobility transistor substrate voltage management circuit
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Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7250804B2 (en) * 2002-12-17 2007-07-31 M/A -Com, Inc. Series/shunt switch and method of control
US7465997B2 (en) * 2004-02-12 2008-12-16 International Rectifier Corporation III-nitride bidirectional switch
JP2006310769A (en) * 2005-02-02 2006-11-09 Internatl Rectifier Corp Group iii nitride integrated schottky electrode and power elements
EP2084750A4 (en) * 2006-11-20 2010-12-22 Panasonic Corp Semiconductor device and its drive method
US7508267B1 (en) * 2007-09-28 2009-03-24 Rockwell Collins, Inc. GaN based digital controlled broadband MMIC power amplifier
US8339163B2 (en) * 2009-06-01 2012-12-25 Sensor Electronic Technology, Inc. Field effect transistor with integrated gate control and radio frequency switch
CN102612753A (en) * 2009-11-30 2012-07-25 松下电器产业株式会社 Bidirectional switch

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US10411008B2 (en) 2015-10-15 2019-09-10 Infineon Technologies Austria Ag System and method for depletion mode and enhancement mode transistors
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