JP6815509B2 - Power supply device for high voltage and high current switching - Google Patents

Description

Various products and systems such as televisions, electric vehicles, radar systems, electric motor controllers, and / or non-disruptive power supply systems can require a relatively large supply of power, which is a high voltage. It can be transmitted from the power source. Various types of semiconductor field effect transistors (FETs) can be used as power switches to perform the switching functions that these products and / or systems may require.

The subject matter considered to be an invention is specifically pointed out and explicitly asserted at the conclusion of this specification. Due to the simplicity and clarity of the figures, the elements shown in the figures are not necessarily drawn to the exact scale. For example, some dimensions of these elements may be enlarged compared to other elements to clarify what is presented. In addition, reference numerals may be used repeatedly between figures to indicate matching or similar elements. On the other hand, the present specification should be best understood by reading and referring to the following detailed description in conjunction with the accompanying drawings with respect to both mechanisms and methods of operation and their objectives, features and advantages. Let's do it.

FIG. 6 is a schematic block diagram representation of a high voltage power switching circuit configuration according to some exemplary embodiments. It is a schematic representation of a power switching circuit configuration according to some exemplary embodiments. It is a schematic representation of a power switching circuit configuration with a common power supply, according to some exemplary embodiments. It is a schematic representation of a power switching circuit configuration with a single isolated power supply, according to some exemplary embodiments. It is a schematic representation of a top view of a high power switching device according to some exemplary embodiments. It is a schematic representation of a bottom view of a high power switching device according to some exemplary embodiments. It is a schematic representation of the physical structure of a GaN transistor according to some exemplary embodiments. FIG. 6 is a schematic representation of a graph of turn-on and turn-off energy losses for multiple high power devices, according to some exemplary embodiments. It is a schematic representation of a graph of switching loss energy of a plurality of high power switching devices according to some exemplary embodiments. FIG. 6 is a schematic representation of a waveform diagram of voltage and current switching time waveforms of a high power switching device according to some exemplary embodiments. It is a schematic representation of a block diagram of a system including a high voltage, high current switching device, according to some exemplary embodiments.

In the detailed description below, a number of specific details are given to provide a thorough understanding of some embodiments. However, as a matter of course to those skilled in the art, some embodiments can be practiced without these specific details. In another example, well-known methods, procedures, components, units, and / or circuits are not described in detail as they do not obscure the description.

For example, the description in this specification using terms such as "process", "calculate", "calculate", "determine", "set", "analyze", and "confirm" , Computer registers and / or data expressed as physical (eg, electronic) quantities in memory, as well as computer registers and / or memory, or for performing operations and / or processing. A computer, computing platform, computing system, or other electronic device that manipulates and / or transforms into other data, represented as a physical quantity, in other information storage medium capable of storing instructions. It may refer to the operation (s) and / or processing (s) of a computing device.

As used herein, the terms "plurality" and "plurality" include, for example, "majority" or "two or more". For example, "plurality of items" includes two or more items.

References to "one embodiment", "some embodiment", "exemplary embodiment", "exemplary embodiment", "various embodiments", etc. are referred to in the described embodiments (groups). Indicates that a particular feature, structure, or property may be included, but not necessarily all embodiments include that particular feature, structure, or property. Moreover, the repeated use of the phrase "in one embodiment" may be the same but does not necessarily refer to the same embodiment.

In use herein, unless otherwise specified, the use of ordinal adjectives "first," "second," "third," etc. to describe a common object is the same as referred to. It only shows different individual examples of objects, that the objects mentioned must be in the order stated, temporally, spatially, in rank, or in any other way. Not intended to mean.

According to some exemplary embodiments, the semiconductor field effect transistor (FET) may rely on silicon material and / or other materials. For example, the FET can include a source terminal and a drain terminal, which can be used to connect a power source to the load. Further terminals can be arranged between the source terminal and the drain terminal in the FET, and this terminal can be referred to as a gate terminal. The gate terminal can control the resistance of the current transmission channel.

During operation, for example, a voltage that can be a voltage to a common ground can be applied to the gate terminals, which can generate an electric field in the FET, which is the resistance of the FET, for example. Can serve to control the transistor, and can also serve to switch the transistor on and / or off. For example, when the FET is turned on, the voltage applied to the gate terminal is, for example, a resistance in the current transmission channel so that a relatively large current can flow between the source terminal and the drain terminal. It is possible to reduce. The total resistance between the source terminal and the drain terminal when the FET is turned on can be referred to as the on resistance of the transistor. This on-resistance is determined by the resistance of the current transmission channel, the resistance to current flow in the FET region below and inside the source terminal, and / or the resistance of the FET region below and / or inside the drain terminal. obtain. Each region inside and around the source and drain terminals can be referred to as an access region of the FET.

Conventional power FETs based on silicon (Si) can, if desired, provide switching functionality for power switching applications. For example, electric motors and / or vehicles, fast charging devices, uninterruptible power supplies, and / or photovoltaic inverters.

According to some exemplary embodiments, nitride-based semiconductors, such as gallium nitride (GaN) and aluminum nitride (AlN), can be characterized by having a relatively large bandgap. For example, the bandgap can be approximately 3.4 eV for GaN and / or approximately 6.2 eV for AlN. For example, a FET that can include a nitride semiconductor layer structure can also include a small bandgap layer adjacent to a large bandgap layer. These FETs can have a relatively high concentration of high mobility electrons, which can be characterized by having a high saturation flow velocity. High-mobility electrons can accumulate in the narrow triangular potential wells of the interface between layers to form a relatively thin sheet-like electron concentration, which is called two-dimensional electron gas (2DEG). be able to. For example, due to the geometry and / or position of this 2DEG, the electrons in the 2DEG can generally exhibit very low donor impurity scattering, resulting in, for example, 1800 cm ² / V * s and, respectively. It is possible to have relatively high electron mobility and / or velocity on the order of 1.5 × 10 ⁷ cm / s. The concentration of electrons in 2DEG can be as high as 1 × 10 ¹³ / cm ² . As a result of the above, for example, FET transistors can have very low intrinsic Rds (on).

According to some exemplary embodiments, FET transistors that operate by generating and / or controlling high mobility electrons in 2DE can be referred to as high electron mobility transistors. A semiconductor layer structure that can contain multiple layers of different components can be referred to as having a heterostructure, and the interface between two adjacent layers of different components can be referred to as a heterojunction.

In some embodiments, the technique comprises a circuit configuration of multiple series and / or parallel connections of discrete and / or monolithic GaN horizontal field effect transistors on a Si substrate due to the extended blocking voltage range. The source of the GaN transistor may have an electrical connection to the back side of a p-type Si substrate, for example, via a high value and / or high voltage insulation resistance element. This high voltage isolation transistor may have a value of several megaohms. For example, longitudinal leak current can flow from the source through the buffer layer to the conductive Si substrate and further from the conductive Si substrate through the buffer layer to the drain. The longitudinal leak current can be considered as a non-linear resistance element and / or bus voltage dependent current. In addition, the longitudinal blocking voltage (eg, source-board-drain) can be lower than the transverse blocking voltage, and the longitudinal substrate-drain leak current can be higher than the horizontal source-drain leak. GaN transistors on Si can have a current capacity of at least 1 amp and / or a blocking voltage of at least 600V.

According to some embodiments, for example, this circuit configuration is a voltage-dependent resistor element of an epitaxial buffer layer grown on a Si substrate and / or connection of a source terminal to the substrate via a high voltage resistor element. May include. This circuit configuration operates in a high voltage range from discrete and / or monolithic Si GaN transistors up to an upper limit of 650V and, if desired, up to 1200V, 1700V, 3500V or higher. It can be applied to devices and systems that are used.

With reference to FIG. 1, this figure schematically illustrates a power switching circuit configuration 100 according to some exemplary embodiments. For example, the power switching circuit configuration 110 may include a "normal off" high output high voltage switching circuit. The switching circuit configuration 100 can include a circuit 110, a circuit 120, and n circuits 130. Circuits 110, 120, and 130 may include the same components, if desired.

For example, the circuit 110 may include a GaN transistor (Q1) 111, a resistance element (Rv1) 112, a resistance element (R1) 113, and a capacitor (Coss1) 114. The transistor 111 may include a P-type Si substrate terminal 115, a drain terminal 116, a gate terminal 117, and a source terminal 118. The circuit 120 may include a GaN transistor (Q2) 121, a resistance element (Rv2) 122, a resistance element (R2) 123, and a capacitor (Coss2) 124. The transistor 121 may include a P-type Si substrate terminal 125, a drain terminal 126, a gate terminal 127, and a source terminal 128. The circuit 130 may have substantially the same components and substantially the same circuit design as the circuits 110 and 120.

According to some embodiments of the present invention, for example, circuits 110, 120, 130 can be used as construction blocks to achieve higher voltage ranges. For example, these circuits may be repeatedly connected in series and / or in parallel to achieve various desired voltage levels. For example, a single circuit (eg, circuit 110) can supply 650v, two circuits connected in series (eg, circuits 110, 120) can achieve 1200v, and three circuits connected in series (eg, circuits 110). , Circuits 110, 120, and 130) can achieve 1700v, six circuits connected in series can achieve 3500v, and so on.

According to some exemplary embodiments, for example, transistors 111 and 121, such as GaN transistors, and resistor elements 112 can be grown on a silicon (Si) substrate. In some embodiments, for example, the diameter of the Si substrate may be in the range of 6-12 inches (about 15-30 centimeters), if desired. A buffer layer (not shown) can be added between the Si substrate and a GaN transistor such as transistor 111. The thickness of this buffer layer may be in the range of 1-8 microns. This buffer layer provides insulation from the substrate and / or high voltage support.

According to some exemplary embodiments, the transistors 111, 121, eg, Q1 and Q2, can be, for example, "normalion" power GaN transistors connected in series. The resistor elements 112 (eg, Rv1) and 122 (eg, Rv2) are, respectively, internal voltage-gated resistors of the drain-board-source of the semiconductor structure. Capacitors 114 (eg, Coss1) and 124 (eg, Coss2) include transistors with internal voltage-gated output capacitance.

According to some exemplary embodiments, the high power switching circuit configuration 100 can have three modes of operation. For example, the first mode can be in the "off" state. In some embodiments, the "off" state may be referred to as static mode. If desired, in the "off" state mode, both transistors 111 and 121 may be in "off" condition. In the second mode, for example the transient mode, the transistors 111 and 121 may be in the transient state. Transient conditions can occur when transistors, such as transistors 111 and 121, can switch from an "off" state to an "on" state, and vice versa. In some embodiments, the third mode can be a conductive state mode. For example, in the conduction state mode, the transistors 111 and 121 may be in the "on" state. In all of the above conditions, the voltage across the transistors 111 and / or the transistors 121 can be split approximately equally between the transistors 111 and 121 due to the self-balancing characteristics incorporated during the circuit design of this example. However, of course, it is also possible to use other circuit designs according to other embodiments of this technique. Further, the high power switching circuit configuration 100 can optionally enable switching at a minimum frequency of 2 kHz with a blocking voltage of at least 600 V.

According to some embodiments, for example, the resistance element (Rv1) 112 and the capacitor (Coss1) 114 can be part of the physical structure of the transistor (Q1) 111. The resistance element (Rv2) 122 and the capacitor (Coss2) 124 can also be part of the physical structure of the transistor (Q2) 121. For example, the resistor elements 112 and 122 may be in the range of 1 k ohm to 100 M ohm, and the capacitors 114 and 124 may be in the range of 10 pF to 1 nF. The resistance element (R1) 113 and the resistance element (R2) 123 may be in the range of 0 ohms to 100 ohms.

In one exemplary embodiment, the values of the resistor elements 113 and 123 may be 10 M ohms. In the case of voltage gradients and / or voltage drops at the drain of transistors 111 and 121, such as non-initial voltage spikes, the resistor elements 112 and 122, along with the capacitors 114, 124, and the resistors 113, 123, are transistors. It may be involved in equilibrating the voltage drops at 111 and 121 almost evenly.

Now, with reference to FIG. 2, this figure schematically illustrates a power switching circuit configuration 200 according to some exemplary embodiments. The operation of the circuit configuration 200 is similar to the operation of the circuit configuration 100, but two functions are added. The first function is a Vcc absence protection circuit including enable units 216 and 226. The second function is the PWM controller 240, which controls the operation of all units 210, 220, and 230n. For example, the power switching circuit configuration 200 can include a high voltage, high output switching circuit configuration. The switching circuit configuration 200 may include a circuit 210, a circuit 220, n circuits 230, and a pulse width modulation (PWM) controller 240. The circuits 210, 220, and 230 may have substantially the same circuit design and may include the same components. In some embodiments, the circuits common to circuits 220 and / or 230 may, if desired, not include separate drivers and / or separate Si MOSFET transistors.

For example, the circuit 210 includes a P-channel metal oxide semiconductor field effect transistor (MOSFET: Metal-Oxide Semiconductor Field-Effective Transistor) (Q3) 212, a resistance element (Rv1) 213, a resistance element (R1) 214, and a capacitor (Coss1). A GaN transistor (Q1) 211 connected in series with the 215, the enable circuit 216, and the driver circuit 217 can be included. The transistor 211 can include a P-type Si substrate terminal 217. The circuit 220 includes a GaN transistor (Q2) 221, a P-channel MOSFET transistor (Q4) 222, a resistance element (Rv2) 223, a resistance element (R2) 224, a capacitor (Coss2) 225, an enable circuit 226, and a driver circuit 227. be able to. The transistor 211 can include a P-type Si substrate terminal 227.

According to an exemplary embodiment, the circuit 230 may have about the same circuit design and components as the circuits 210 and 220. According to another exemplary embodiment, the circuit 220 may not include the driver 227 and the transistor Q4 222. In this embodiment, the driver 217 may be connected to the gate of transistor Q2 221 shown by the dotted line, if desired. Of course, other designs of the circuit 220 according to embodiments of the present invention are also possible.

According to some embodiments of the invention, for example, circuits 210, 220, 230 can be used as building blocks to achieve higher voltage ranges. For example, a single circuit (eg, circuit 210) can supply 650v, two circuits connected in series (eg, circuits 210, 220) can achieve 1200v, and three circuits connected in series (eg, circuits 210). Circuits 210, 220, and 230) can achieve 1700v, six circuits connected in series can achieve 3500V, and so on.

According to some exemplary embodiments, for example, transistors Q1 211, and Q2 221 can include "normalion" power GaN transistors connected in series. Transistors Q3 212 and Q4 222 may include high current SiMOSFET N and / or P channel transistors. Transistors Q3 212 and Q4 222 can be provided with a common current cutoff in the process of power rise, power fall and Vcc undervoltage, and / or in case of abnormal operation. During continuous normal operation, the transistors Q3 212 and Q4 222 may be continuously energized by the enable circuit 226, which may be "transparent" to the power on / power off normal switching mode. ..

Enable circuits 216 and 226 can provide control over the voltage levels of the gates of transistors 212 and 222 to allow PWM signals to flow through the gates of GaN transistors, such as the gates of transistors 211 and 221. , Drivers 217 and 227 can be activated and / or stopped. The enable circuits 216, 226 can also provide a predetermined sequence of switching activations, and as previously described, the transistors 211, 212, 221 and 222 are turned on / off for system power supply operation. It can be protected from the transient state in the process of).

According to some exemplary embodiments, for example, the driver, eg the driver 227, may not include an undervoltage lockout function. According to this example, when Vcc is lower than a predetermined threshold, the enable circuits 216 and 226 can block the transistors Q3 212 and Q4 222, and can block the gate control of the transistors Q1 211 and Q2 221. Yes, and thus the device 200 can go into "off" mode. The term cutoff can be used to indicate that a transistor behaves like an open circuit, where, for example, no current flows from the drain to the source and / or a signal is sent to the gate. Absent.

According to some exemplary embodiments, the PWM controller 240 may be coupled to drivers 217 and 227. For example, if desired, the PWM controller 240 can drive the transistors 211 and 221 at about the same time.

According to some exemplary embodiments, the resistor element (Rv1) 213 and the capacitor (Coss1) 215 are incorporated into the physical structure of the transistor (Q1) 211. The resistor element (Rv2) 223 and the capacitor (Coss2) 225 are also incorporated into the physical structure of the transistor (Q2) 221. For example, the resistor elements 213 and 223 may be in the range of 1 k ohm (kilo ohm) to 100 M ohm (mega ohm), and the capacitors 215 and 225 are in the range of 10 pF (picofarad) to 1 nF (nanofarad). You can. The resistance element (R1) 214 and the resistance element (R2) 224 may be in the range of 0 ohms to 100 ohms. In the case of voltage gradients and / or voltage drops at the drain of transistors 211 and 221, such as non-initial voltage spikes, the resistor elements 213 and 223 are capacitors 215, 225, resistor elements 214, 224, and transistors 212 and 224. At the same time, it can operate so as to equilibrate the voltage drops in the transistors 111 and 121 almost evenly.

According to some exemplary embodiments, for example, a series connection of multiple discrete and / or monolithic GaN horizontal field effect transistors on a Si substrate has a total output capacitance of Coss = Cos1 / N. ) Is the output capacitance of the discrete and / or monolithic GaN horizontal field effect transistor on the Si substrate, where N is the discrete and / or monolithic on the Si substrate connected in series. The number of GaN horizontal field effect transistors.

With reference to FIG. 3, this figure schematically illustrates a power switching circuit configuration 300 with a single power supply (PS) 310 according to some exemplary embodiments. According to some embodiments, this power switching circuit configuration can include a high voltage power switching circuit configuration. The power switching circuit configuration 300 includes, for example, a Zener diode (D2) 315, a capacitor (C), a diode (D1) 330, an enable circuit 335, a driver 340, a GaN transistor (Q1) 345, a GaN transistor (Q2) 350, and a MOSFET transistor. 355, drain terminal 360, and source terminal 370 may be included.

According to an embodiment of this example, during operation, the PS310 brings the VCS1 to the driver 340, the enable circuit 335, the RTN1 to the source of the GaN transistor Q2 350, and the drain of the transistor Q2 355 (eg, the GaN transistor Q2 350). Can be supplied to the source of transistor Q3 355). The voltage range of VCS1 may be, for example, −8V to −15V.

According to some embodiments, if transistor Q2 350 can turn off-condition, its drain voltage can rise with the source voltage of transistor Q1 345. After reaching a positive voltage, which can be higher than the gate threshold voltage of transistor Q1 345, transistor Q1 345 can turn off-condition. For example, the gate threshold voltage of transistor Q1 345 may be in the range of −6V to −15V. When the transistor Q2 350 (for example, a GaN transistor) can shift to the off-condition, the transition period of the transistor Q1 345 can be delayed because the gate of the transistor Q1 345 may be connected to the ground potential via the capacitor C320. For example, this leg period can be 0.5 ns to 10 ns.

According to some embodiments, for example, the voltage rise of the transistor Q2 350 (eg, a GaN transistor) can be limited to 400V by the Zener diode D2 315. The rating of the Zener diode D2 315 may be selected according to the breakdown voltage of the transistor Q1 345. For example, the breakdown voltage of transistor Q1 345 can be 650V.

According to some exemplary embodiments, applying a drain-source voltage to the transistors Q1 345 and Q3 355 in the absence of VCS1 can cause the GaN transistor Q2 350 to be off-condition. DC equilibration is achievable when the gate-source voltage of "normalion" transistors, such as Q1 345 and Q2 350, can be equalized by the diodes D2 315 and D1 330 to the threshold voltages of those transistors. For example, this threshold voltage may be −6V to −15V.

According to some embodiments, when VCS1 is applied, it can turn on the enable circuit 335. For example, the enable circuit 335 can turn the transistor 355 on and off by the VCS1 voltage that can be supplied by the power supply 310, but, of course, this example is not limited to the circuit configuration of FIG.

With reference to FIG. 4, this figure schematically illustrates a power switching circuit configuration 400 with a single power supply (PS) 405, according to some exemplary embodiments. According to some embodiments, the power switching circuit configuration 400 can include a high voltage power switching circuit. The power switching circuit configuration 400 (200) includes, for example, a Zener diode (D2) 410, a capacitor (C) 420, an enable circuit 425, a driver 430, a diode (D1) 435, a GaN transistor Q1 445, Q4 450, Q6 455, and GaN. It may include transistors Q2 460, Q5 465, Q7 470, MOSFET transistors 475, drain terminals 440, and source terminals 480.

According to the embodiment of this example, during operation, the PS405 attaches the VCS1 to the driver 430 and the RTN1 to the GaN transistors Q2 460, Q5 465. .. .. It can be supplied to the common source of Q7 470 and the drain of transistor Q3 475 (for example, the common source of GaN transistors Q2 460, Q5 465 ... Q7 470 is connected to the drain of transistor Q3 475). .. For example, the voltage range of VCS1 may be −8V to −15V.

According to some embodiments, GaN transistors Q2 460, Q5 465. .. .. When Q7 470 can turn off-condition, their drain voltage is GaN transistors Q1 445, Q4 450. .. .. It can rise with the source voltage of Q6 455. This voltage can rise until it reaches a positive voltage, eg 400V. GaN transistors Q1 445, Q4 450. .. .. After reaching a positive voltage that can be above the gate threshold voltage of Q6 455, GaN transistors Q1 445, Q4 450. .. .. Q6 455 can turn to off-condition. For example, GaN transistors Q1 445, Q4 450. .. .. The gate threshold voltage of Q6 455 may be in the range of -6V to -15V. GaN transistors Q1 445, Q4 450. .. .. When Q6 455 can shift to the off condition, GaN transistors Q1 445 and Q4 450. .. .. Q6 455 is a GaN transistor Q1 445, Q4 450. .. .. Since the gate of Q6 455 may be connected to the ground potential via the capacitor C420, the transition period may be delayed. For example, this delay period may be 0.5 ns to 10 ns.

According to some embodiments, for example, GaN transistors Q2 460, Q5 465. .. .. The voltage rise of Q7 470 can be limited to 400V by the Zener diode D2 410. The Zener diode D2 410 includes GaN transistors Q1 445 and Q4 450. .. .. The rating may be selected according to the breakdown voltage of Q6 455. For example, GaN transistors Q1 445, Q4450. .. .. The breakdown voltage of Q6 455 can be 650V.

According to some exemplary embodiments, the GaN transistors Q1 445, Q4 450. In the absence of VCS1. .. .. Q6 455 and GaN transistors Q2 460, Q5 465. .. .. When a drain source voltage is applied to Q7 470, the MOSFET transistor Q3 475 may be in an off condition. Normalion GaN transistors, such as Q1 445, Q4 450. .. .. Q6 455 and GaN transistors Q2 460, Q5 465. .. .. DC equilibration is achievable when the gate-source voltage of Q7 470 can be equal to the threshold voltage of those transistors by the diodes D2 410 and D1 435. For example, this threshold voltage may be −6V to −15V.

According to some embodiments, when VCS1 is applied, it can turn on enable circuit 425. For example, the enable circuit 425 can turn the MOSFET transistor 475 on and / or off by the VCS1 voltage that can be supplied by the PS405, but of course this example is limited to the circuit configuration of FIG. Not done.

According to some exemplary embodiments, advantageously combined GaN transistors Q1 445, Q4 (2) 450. By arranging the GaN transistors in parallel as shown in FIG. .. .. Q6 455 and GaN transistors Q2 460, Q5 465. .. .. A higher drain 440-source 480 current and lower on-state resistance of Q7 470 can be achieved. The configuration of this example can make it possible to achieve both higher voltage and / or higher current at about the same time while reducing conductive loss.

With reference to FIG. 5a here, this figure schematically illustrates a top view of the high power switching device 500 according to some exemplary embodiments. For example, the high power switching device 500 may include a low current lead terminal 510, a high current lead terminal 520, a molding compound 530, and / or an exposed thermal interface pad 540. For example, if desired, a heat sink for cooling the power transistors of the high power switching device 500 can be attached to the exposed thermal interface pad 540.

With reference to FIG. 5b, the figure schematically illustrates a bottom view of the high power switching device 500 according to some exemplary embodiments. For example, the high-power switching device 500 includes a low-current lead terminal 510, a high-current lead terminal 520, a three-dimensional (3D: 3 wire) power die stack 530, a ceramic interposer 535, a built-in ceramic insert 540, a GaN FET 550 on Si, and a Si MOSFET 560. It may include an enable circuit 570, a high voltage (HV) resistor element 580, and / or a small diameter bond wire 590.

According to some exemplary embodiments, for example, the circuit configurations of FIGS. 1, 2, 3 or 4 can be implemented on the high power device 500. The low current lead terminal 510 can be used to provide input signals and / or voltages to drivers 217 and 227. The high current lead terminal 520 can be used, if desired, to provide a high voltage to the drain of the transistor 211 and a ground potential to the source of the transistor 222.

Further, for example, the 3D power die stack 530 provides insulation and further provides heat transfer from the GaN FET 550 on Si through the ceramic interposer 535, Si MOSFET 560 to the top thermal pad 540 and heat sink (not shown). A ceramic interposer 535 may be included. The ceramic insert 540 can have high thermal conductivity. The enable circuit 570 may include, for example, an HV resistance element 580 that can be used to reduce leakage of GaN FETs.

According to some exemplary embodiments, the high power switching device 500 can be incorporated into a high voltage package that may include, for example, a printed circuit board (PCB) 505 that includes a built-in ceramic insert. The PCB 505 can include a plurality of conductors capable of continuously extending from the PCB 505 over the ceramic insert 540. Multiple high current 520 and / or low current 510 metal lead terminals can be mounted on PCB505 using a conductive medium with a melting point above the melting point of lead-free solder and below 350 degrees Celsius (C). It is possible. For example, this high voltage package may be coated with molding compound 430.

According to some exemplary embodiments, the 3D power die stack 530 is a ceramic interposer with a GaN power FET die 550 on Si, a Si power MOSFET die 560, and / or, for example, multiple conductors and conductive vias. 535 may be included. The ceramic interposer 535 can include multiple wire bond pads for inner and / or outer wire interconnects. The GaN die 550 on Si, the Si MOSFET die 560, and / or the ceramic interposer 535 (435) are mounted, for example, using some conductive medium having a melting point above the solder melting point and / or below 550 ° C. Is possible. The high voltage package can also include multiple small diameter wire bonds on the GaN FET die 550 and Si MOSFET die 560 on Si due to low stray inductance and / or high temperature cycle reliability.

With reference to FIG. 6, this figure is a schematic representation of the physical structure of the GaN transistor 600 according to some exemplary embodiments. According to some exemplary embodiments, the GaN transistor 600 has a source terminal 610, a gate terminal 620, a drain terminal 630, a barrier layer 640, 2DEG650, a buffer layer 660, a P-channel Si substrate 670, and / or a leak current. 680 may be included.

According to this exemplary embodiment, the longitudinal leak current 680 passes from the drain terminal 630 through the barrier layer 640, 2DEG650, and the buffer layer 660 to the conductive Si substrate 670 and / or to the conductive Si substrate 670. Can flow from the buffer layer 660, 2DEG650, and the barrier layer 640 to the source terminal 610. The longitudinal leak current 480 can behave as a non-linear resistance element and / or bus voltage dependent current.

In addition, the longitudinal blocking voltage on the source terminal 610, P-channel board 670, and drain terminal can be lower than the transverse blocking voltage, and / or the longitudinal substrate-drain leak current is the lateral source-. It can be higher than the drain leak. GaN transistors on Si can optionally have a current capacity of at least 1 amp and a blocking voltage of at least 600V.

With reference to FIG. 7, this figure schematically illustrates a graph of turn-on and / or turn-off energy loss of multiple high power devices according to some exemplary embodiments. An example of the turn-on energy and / or turn-off energy performance of certain embodiments of the high power switching device 300 is shown by the low line. Advantageously, for a current from 10 amps (A) to 40 A, for example, the turn-on energy range can be 25 μJ to 100 μJ and the turn-off energy range can be 75 μJ to 100 μJ. is there. Compared to other prior art switching devices, this embodiment can operate with lower turn-on, turn-off energy loss.

With reference to FIG. 8, this figure schematically illustrates a graph of switching loss energies of a plurality of high power switching devices according to some exemplary embodiments. The total switching loss of certain embodiments of the high power switching device 300 is shown by the low line drawn as 45 m ohms. Advantageously, for a current from 10A to 40A, for example, the range of switching energies is 25μJ to 200μJ. Compared to other prior art switching devices, this embodiment can provide low switching energy loss.

With reference to FIG. 9, this figure schematically illustrates the voltage and current switching time waveforms of a high power switching device according to some exemplary embodiments. For example, the first waveform is the voltage waveform 710 and the second waveform is the current waveform 720. The voltage waveform 710 shows 1 kV voltage switching with a rise time of 18.3 ns and a fall time of 14.3 ns, which can be better than the current technology. The current waveform 620 shows switching of 11.6 A with a rise and fall time similar to the voltage waveform 610. The current and voltage, 610 and 620 waveforms show continuous straight lines during the switching time, demonstrating voltage balancing and / or synchronized operation between GaN FET transistors on Si connected in series. doing.

With reference to FIG. 10, this figure represents a block diagram of a system 1000 including a high voltage high current switching device 1010 according to some exemplary embodiments. For example, the system 1000 can include switching power supplies such as AC / DC power supplies, three-phase motor drives, solar inverters, uninterruptible power supplies, battery chargers, several kV high voltage converters and inverters.

According to some exemplary embodiments, the high voltage and / or high current switching device 1010 can include the circuit configurations and devices described above in FIGS. 1, 2, 3, 4, 5a, and 5b. However, as a matter of course, FIGS. 1, 2, 3, 4, 5a, and 5b are non-limiting exemplary embodiments, and other embodiments can be used if desired.

Although the particular features of the present invention have been illustrated and described here, many modifications, alternatives, modifications, and equivalents will come to mind to those skilled in the art. Therefore, of course, the appended claims are intended to cover all such modifications and modifications that are within the true spirit of the invention.

Examples The following examples relate to further embodiments.

Example 1 includes a device comprising a circuit configuration, the circuit configuration comprising a first gallium nitride (GaN) horizontal field effect transistor on a silicon (Si) substrate and a first GaN horizontal field effect on the Si substrate. The source terminals of the effect transistor are the P-type Si substrate terminal via the first resistance element, the drain terminal of the first GaN horizontal field effect transistor, and the second resistance element operably connected to the P-type Si substrate terminal. When the voltage on the first GaN horizontal field effect transistor, including the electrical connection to, drops, the first leak current from the drain terminal to the source terminal via the buffer layer increases on the first GaN horizontal field effect transistor on the Si substrate. The voltage on the second GaN horizontal field effect transistor on the Si substrate connected in series will be balanced, and this buffer layer will be epitaxially grown on the conductive substrate on the Si substrate.

Example 2 includes the subject of Example 1, optionally including a first discrete GaN horizontal field effect transistor on the Si substrate, the first discrete GaN horizontal field effect transistor on the Si substrate, and a second on the Si substrate. The GaN horizontal field effect transistor includes a second discrete GaN horizontal field effect transistor on the Si substrate.

Example 3 includes the subjects of Examples 1 and 2, and optionally, the first GaN horizontal field effect transistor on the Si substrate and the second GaN horizontal field effect transistor on the Si substrate monolithically include the Si substrate. Combined inside.

Example 4 includes the subjects of Examples 1 to 3, and optionally includes a third resistance element in which the circuit configuration is operably connected to the drain terminal and the P-type Si substrate terminal of the second GaN horizontal field effect transistor. The leakage current from the drain terminal to the source terminal via the buffer layer of the second GaN horizontal field effect transistor includes the voltage drop on the second GaN horizontal field effect transistor, and the first GaN horizontal field effect connected in series. It will be balanced with the voltage on the transistor, and this buffer layer will be epitaxially grown on the conductive substrate on the Si substrate.

Example 5 includes the subjects of Examples 1 to 4, and the circuit configuration uses a first driver for supplying a switch signal to a first GaN horizontal field effect transistor and a switch signal to a second GaN horizontal field effect transistor. A second driver for supply, a first Si metal oxide semiconductor field effect transistor (MOSFET) connected in series with the first GaN horizontal field effect transistor, and a second GaN horizontal field effect transistor connected in series. The first and second Si MOSFETs, including the second Si MOSFET, will perform a common current cutoff when one of the first driver and the second driver is not activated.

Example 6 includes the subject of Examples 1 to 5, and optionally includes a first driver operably coupled to the gate of the first Si MOSFET and the gate of the first GaN horizontal field effect transistor. A second enable circuit operably coupled to, and a second driver operably coupled to the gate of the second SiMOSFET and the gate of the second GaN horizontal field effect transistor. The first and second enable circuits, including the enable circuit, will open the first and second Si MOSFETs to carry current.

Example 7 includes the subject of Examples 1 to 6, and optionally, the circuit configuration operates with the first driver and the second driver in order to drive the first and second GaN horizontal field effect transistors at approximately the same time. Includes a freely coupled pulse width modulation (PWM) controller.

Example 8 includes the subject of Examples 1 to 7, and optionally, the first and second enable circuits provide turn-on and turn-off timing sequences for the device, allowing delivery of PWM signals from the PWM controller. It will be.

Example 9 includes the subject matter of Examples 1-8, and optionally, the device includes high voltage and high current switching devices.

Example 10 includes the subject of Examples 1-9, in which the apparatus optionally switches the first and second GaN transverse field effect transistors at a minimum frequency of 1 kHz and a blocking voltage of at least 600 volts. Become.

Example 11 includes the subject matter of Examples 1 to 10, and optionally, the series connection of a plurality of GaN horizontal field effect transistors results in a total output capacitance (Coss) of Cos total = Cos1 / N. , The output capacitance of the first GaN horizontal field effect transistor on the Si substrate, where N is the number of GaN horizontal field effect transistors on the Si substrate connected in series.

Example 12 includes the subjects of Examples 1 to 11, and optionally, the first and second GaN horizontal field effect transistors are normal off type transistors.

Example 13 includes a system that includes a device for high voltage and high current switching, the device including a first gallium nitride (GaN) horizontal field effect transistor on a silicon (Si) substrate and a first GaN on a Si substrate. The source terminal of the horizontal field-effect transistor is operably connected to the P-type Si substrate terminal via the first resistance element, the drain terminal of the first GaN horizontal field-effect transistor, and the P-type Si substrate terminal. When the voltage on the first GaN horizontal field effect transistor drops, the first leak current from the drain terminal to the source terminal via the buffer layer becomes the first GaN horizontal field effect on the Si substrate. The voltage on the transistor and the voltage on the second GaN horizontal field effect transistor on the Si substrate connected in series will be balanced, and this buffer layer is epitaxially grown on the conductive substrate on the Si substrate. Be done.

Example 14 includes the subject of Example 13, optionally, the first GaN horizontal field effect transistor on the Si substrate comprises a first discrete GaN horizontal field effect transistor on the Si substrate and a second on the Si substrate. The GaN horizontal field effect transistor includes a second discrete GaN horizontal field effect transistor on the Si substrate.

Example 15 includes the subjects of Examples 13 and 14, and optionally, the first GaN horizontal field effect transistor on the Si substrate and the second GaN horizontal field effect transistor on the Si substrate monolithically include the Si substrate. Is united in.

Example 16 includes the subjects of Examples 13 to 15, and optionally, the apparatus is operably connected to the drain terminal of the second GaN horizontal field effect transistor on the Si substrate and the back side of the P-type substrate terminal. When the voltage on the first GaN horizontal field-effect transistor including the three resistance elements drops, the leak current from the drain terminal to the source terminal of the second GaN horizontal field-effect transistor via the buffer layer increases to the second on the Si substrate. The voltage on the GaN horizontal field effect transistor and the voltage on the first GaN horizontal field effect transistor on the Si substrate connected in series will be balanced, and this buffer layer is a Si substrate and a conductive substrate. It is epitaxially grown on top.

Example 17 includes the subjects of Examples 13 to 16, and optionally, the apparatus provides a first driver for supplying the switch signal to the first GaN horizontal field effect transistor on the Si substrate and a second switch signal. A second driver for supplying to a GaN horizontal field effect transistor and a first Si metal oxide semiconductor field effect transistor (MOSFET) (MOSFET) Field-Effective transistor connected in series with the first GaN horizontal field effect transistor (Metal-Oxide Semiconductor Field-Effective Transistor). (MOSFET) transistor) and a second Si MOSFET connected in series with a second GaN horizontal field effect transistor, the first and second Si MOSFETs do not operate one driver, the first driver and the second driver. In some cases, a common current cutoff will be performed.

Example 18 includes the subject matter of Examples 13 to 17, and optionally includes a first driver operably coupled to the gate terminal of the first Si MOSFET and the gate terminal of the first GaN horizontal field effect transistor. Operatively coupled to a first enable circuit operably coupled to, and a second driver operably coupled to the gate of the second SiMOSFET and the gate terminal of the second GaN horizontal field effect transistor. The first and second enable circuits, including the second enable circuit, will operate the first and second Si MOSFETs to carry current.

Example 19 includes the subject matter of Examples 13 to 18, and optionally, the apparatus can operate the first driver and the second driver because the first and second GaN horizontal field effect transistors are driven almost simultaneously. Includes a coupled pulse width modulation (PWM) controller.

Example 20 includes the subject of Examples 13-19, optionally with first and second enable circuits providing turn-on and turn-off timing sequences for the device, allowing delivery of PWM signals from the PWM controller. It will be.

Example 21 includes the subject of Examples 13-20, and optionally the device includes a high voltage and high current switching power supply.

Example 22 includes the subject of Examples 13-21, optionally such that the apparatus switches the first and second GaN lateral field effect transistors at a minimum frequency of 1 kHz and a blocking voltage of at least 600 volts. It is composed.

Example 23 includes the subject of Examples 13 to 22, and optionally, the series connection of a plurality of GaN horizontal field effect transistors results in a total output capacitance (Coss) of Cos total = Cos1 / N, where Cos1 is , The output capacitance of the first GaN horizontal field effect transistor, where N is the number of GaN horizontal field effect transistors connected in series.

Example 24 includes the subjects of Examples 13 to 23, in which the first and second GaN horizontal field effect transistors are normal off type transistors.

Example 24 includes a device that includes a high voltage package with a printed circuit board (PCB), the PCB including an internal ceramic insert, a 3D power die stack, which is on a Si power FET die. GaN transistors, Si MOSFETs, and ceramic interposers on this Si power FET die include a ceramic interposer with a GaN transistor, a power SiMOSFET die, multiple conductors and conductive vias, and the ceramic interposer is a conductive medium having a melting point above the solder melting point Installed by.

Example 25 includes the subject of Example 24, optionally with a ceramic interposer of multiple wire bond pads for inner and outer wire connections, multiple conductors extending continuously from the PCB, and lead-free solder. Includes multiple high and low current metal lead terminals mounted on the PCB by a conductive medium having a melting point above and below 350 degrees Celsius.

Example 26 includes the subjects of Examples 24 and 25, optionally a high voltage package with a PCB coated with a molding compound.

Example 27 includes the subject of Examples 24 to 26, and optionally, the device includes a thermal interface electrical insulation pad on the top or bottom surface of the device, and an exposed thermoelectric insulation pad.

Example 28 includes the subject matter of Examples 24 to 27, wherein the apparatus includes a plurality of small diameter wire bonds on a SiFET die and a plurality of small diameter wire bonds on the SiFET die. It has low stray inductance and high temperature cycle reliability.

Claims (7)

A series connection of at least two GaN switching units (110, 120) on a Si substrate designed to extend the operating voltage range beyond the breakdown voltage of each switching unit.
The source of the first transistor of one of the at least two switching units including the first transistor (111, 121) is connected to the drain of the first transistor of the next switching unit.
The source of each first transistor is connected to the Si substrate via an external resistance element (113, 123) having a high resistance.
To form the adapted circuit configured to equilibrate substantially equally each on the voltage drops of the first transistor of the series connection, the drain of the first transistor, wherein the external resistor element (113 , 123) and connected to the internal voltage control resistors (112, 122) formed in the epitaxial structure of the GaN internal buffer layer on the Si substrate of the first transistor.
Series connection. It formed in the epitaxial structure of the Si GaN of the internal buffer layer on the substrate of the first transistor, which is connected between the drain and the source of the first transistor, the first transistor of the series connection is adapted to equilibrate substantially uniformly the voltage drops on each internal voltage controlled capacitance (114, 124),
The serial connection according to claim 1, further comprising. It said first transistor of each of the gates (117 and 127) is coupled to the driver, the series connection of claim 1. Each pre Kido driver is controlled by the same PWM signal, the series connection of claim 3. Each of the switching units
A protection transistor connected in series between the source of each of the first transistors and the drain of the first transistor of the next-stage switching unit.
To prevent over current through the first transistor of said respective, an enable circuit for controlling the operation of the driver of each of the first transistor, and the operation of the protection transistor,
The serial connection according to claim 1, further comprising. Resistance of the internal resistor element is in the range of 1k Omega～100emuomega, series connection of claim 1. The series connection according to claim 5, wherein each of the first transistors is a type of D-mode or E-mode transistor.

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