CN112349764A - RESURF LDMOS device with field limiting ring structure - Google Patents
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- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
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Abstract
本发明公开了一种具有场限环结构的RESURF LDMOS器件，包括P型半导体衬底，在P型半导体衬底上设置深N阱和深P阱，在深P阱中设置P阱，源端N+区和源端P+区设置在P阱中且位于器件的表面；深N阱的上端面设置场氧化层，场氧化层的一端与漏端N+区相连，场氧化层的另一端设置栅氧化层和多晶硅栅；多晶硅栅设置在栅氧化层之上，两者共同延伸至器件表面的源端N+区；在深N阱中设置N阱和P TOP区，漏端N+区设置在N阱中且位于器件的表面；P TOP区由P型条和P型场限环组成。该器件可以降低结表面曲率效应引起的大电场，提高器件的击穿电压。
The invention discloses a RESURF LDMOS device with a field limiting ring structure. The N+ region and the source P+ region are arranged in the P well and are located on the surface of the device; a field oxide layer is arranged on the upper end face of the deep N well, one end of the field oxide layer is connected to the drain N+ region, and the other end of the field oxide layer is arranged with gate oxide layer and polysilicon gate; the polysilicon gate is arranged on the gate oxide layer, and the two together extend to the source N+ region of the device surface; the N well and P TOP region are arranged in the deep N well, and the drain N+ region is arranged in the N well And it is located on the surface of the device; the P TOP region consists of P-type strips and P-type field limiting rings. The device can reduce the large electric field caused by the curvature effect of the junction surface and improve the breakdown voltage of the device.
Description
Technical Field
The invention belongs to the technical field of power semiconductor devices, and particularly relates to a RESURF LDMOS device with a field limiting ring structure.
Background
An ldmos (laterally Diffused Metal Oxide semiconductor) is a lateral double-Diffused structure power device, the source, drain and gate of which are on the surface of a chip, and is easy to integrate with other circuits, and the withstand voltage can be higher, so that the ldmos (laterally Diffused Metal Oxide semiconductor) is more commonly used in high-voltage power integrated circuits. The high-voltage LDMOS has the advantages of high working voltage, relatively simple process and the like due to the compatibility of CMOS and BCD processes, and is widely applied to high-voltage circuits of automobile electronics, power supply management, industrial control, motor drive, household appliances and the like. However, the specific on-resistance of the high-voltage LDMOS increases at a rate of 2.5 times with the increase of the breakdown voltage, so that its application in the field of ultra-high voltage is greatly limited. At present, two optimization targets are provided for the high-voltage-resistant power LDMOS: improve breakdown voltage and reduce on-resistance.
In silicon devices, especially in lateral high voltage semiconductor devices LDMOS, field limiting ring technology is often used to help reduce the large electric field due to junction surface curvature effects and increase the breakdown voltage of the device. The Field Limiting Ring technology is usually to form an impurity region in a Ring shape distribution on the periphery of a main junction of a planar junction by means of ion implantation or diffusion, and the property of the impurity region is the same as that of the main junction. According to the technology, one or more rings are doped near the PN junction, and the added rings can increase the effective curvature radius of a depletion region, so that electric field concentration caused by the curvature effect of the edge of a main junction is inhibited, the peak electric field intensity of the edge of a gate field plate is reduced, the effect of a voltage divider is realized to a certain extent, and the purpose of improving the breakdown voltage of a device is achieved. The main advantages of the field limiting ring technology are: the structure is simple, when the main junction is formed by diffusion, the same doped ring is made around the main junction, and the purpose of optimization and improvement can be realized without adding another process. Theoretically, as the number of rings increases, the breakdown voltage will increase continuously, but when the number of rings increases to a certain number, the breakdown voltage will increase slowly, which will cause a serious waste of chip area and increase the cost.
Disclosure of Invention
The invention aims to solve the problem that the breakdown voltage and the on-resistance are difficult to balance in the prior art, and provides a RESURF LDMOS device with a field limiting ring structure, which can reduce a large electric field caused by the junction surface curvature effect and further improve the breakdown voltage of the device.
The invention is realized by the following technical scheme:
a RESURF LDMOS device with a field limiting ring structure comprises a P-type semiconductor substrate, wherein a deep N well and a deep P well are arranged on the P-type semiconductor substrate, the P well is arranged in the deep P well, and a source end N + region and a source end P + region are arranged in the P well and positioned on the surface of the device; a field oxide layer is arranged on the upper end surface of the deep N well, one end of the field oxide layer is connected with the drain end N + region, and a gate oxide layer and a polysilicon gate are arranged on the other end of the field oxide layer; the polysilicon gate is arranged on the gate oxide layer, and the polysilicon gate and the gate oxide layer jointly extend to a source end N + region on the surface of the device; an N well and a P TOP region are arranged in the deep N well, and a drain terminal N + region is arranged in the N well and is positioned on the surface of the device; the P TOP region consists of P-type strips and P-type field limiting rings.
In the technical scheme, an N TOP area is arranged above the P TOP area, and the N TOP area consists of an N-type strip and an N-type field limiting ring.
In the technical scheme, the surface of the device is isolated by adopting the silicon dioxide layer.
In the technical scheme, the number of the P-type field limiting rings is 1-5.
In the above technical solution, an N-type strip or an N-type field limiting ring is disposed on a P-type strip, and an N-type strip or an N-type field limiting ring is disposed on a P-type field limiting ring.
In the technical scheme, the number of the N-type field limiting rings is 1-5.
In the technical scheme, boron ions are injected into the P TOP region, the junction depth is 1-5 mu m, and the doping concentration is 2.6 multiplied by 1012cm-2-3×1012cm-2。
In the technical scheme, phosphorus ions are injected into the N TOP region, the junction depth is 1-5 mu m, and the doping concentration is 7.5 multiplied by 1011cm-2-2×1012cm-2。
In the technical scheme, the cross section of the P-type field limiting rings is square, the side length is 1 mu m, the horizontal distance from the P-type field limiting rings to the P-type strips is 1-3 mu m, and the horizontal distance between adjacent P-type field limiting rings is 1-4 mu m.
In the technical scheme, the section of the N-type field limiting rings is square, the side length is 1 mu m, the horizontal distance from the N-type field limiting rings to the N-type strips is 1-3 mu m, and the horizontal distance between adjacent N-type field limiting rings is 1-4 mu m.
The invention has the beneficial effects that:
the invention provides a RESURF LDMOS device with a field limiting ring structure. The field limiting ring technology is aimed at relieving the contradictory relation between the on-resistance and the breakdown voltage of a lateral power device, such as a high-voltage LDMOS device, so that breakdown does not occur on the surface of the device but occurs inside the device. The RESURF LDMOS device with the field limiting ring structure introduces a P TOP region (comprising a P-type strip and a P-type field limiting ring) at the TOP of a drift region, so that a PN junction formed by the P TOP region and an N-type drift region is added in the longitudinal direction to assist in depletion, and a breakdown point of the device is transferred from the surface of the device to the interior of the device. The field limiting ring is not in direct contact with a main junction (PN junction of a device) and other electrodes, when the voltage applied to the main junction is continuously increased, a depletion region of the main junction is also continuously expanded outwards until the depletion region is contacted with the field limiting ring, electrons in the ring flow into the main junction under the action of an electric field, and at the moment, the ring is changed from electric neutrality to positive charge. In the region from the main junction to the ring, the electric field generated on the surface of the device by positive charges is opposite to the original electric field, so that the electric field intensity of the region is weakened, and another small peak electric field is introduced into the region outside the right end of the field limiting ring. In order to further optimize the performance of the device, a metal layer (a field plate) is laid above the PN junction, and when a certain voltage is applied to the field plate, interface charges capable of weakening a peak electric field of the PN junction are induced on the upper surface of the silicon, so that the purpose of optimizing the breakdown voltage is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a RESURF LDMOS device having a field limiting ring structure according to the present invention.
In the figure: 1 is a P-type semiconductor substrate; 2 is deep N-well (DNW); 3 is a deep P-well (DPW); 4 is an N-well (NW); 5 is a P-type bar; 6 is a P-type field limiting ring; 7 is a field oxide layer; 8 is a P Well (PW); 9 is source end N +; 10 is source end P +; 11 is the drain terminal N +; 12 is a gate oxide layer; and 13 is a polysilicon gate.
Fig. 2 is a cross-sectional doping concentration profile of the RESURF LDMOS device having the field limiting ring structure in example 1.
Fig. 3 is a graph of simulation results of the drain current of the RESURF LDMOS device having the field limiting ring structure in example 1 as a function of the drain voltage.
Fig. 4 is a cross-sectional doping concentration profile of the RESURF LDMOS device having the field limiting ring structure in example 2.
Fig. 5 is a graph of simulation results of the drain current variation with the drain voltage of the RESURF LDMOS device having the field limiting ring structure in embodiment 2.
Fig. 6 is a schematic structural diagram of a RESURF LDMOS device of the RESURF LDMOS device having a field limiting ring structure in embodiment 3.
In the figure: 1 is a P-type semiconductor substrate; 2 is deep N-well (DNW); 3 is a deep P-well (DPW); 4 is an N-well (NW); 5 is N TOP; 6 is P TOP; 7 is a field oxide layer; 8 is a P Well (PW); 9 is source end N +; 10 is source end P +; 11 is the drain terminal N +; 12 is a gate oxide layer; and 13 is a polysilicon gate.
Fig. 7 is a graph of simulation results of the drain current variation with the drain voltage of the RESURF LDMOS device having the field limiting ring structure in example 3.
Fig. 8 is a graph of simulation results of the drain current variation with the drain voltage of the RESURF LDMOS device having the field limiting ring structure in example 4.
Fig. 9 is a schematic structural diagram of a RESURF LDMOS device having a field limiting ring structure in embodiment 5.
In the figure: 1 is a P-type semiconductor substrate; 2 is deep N-well (DNW); 3 is a deep P-well (DPW); 4 is an N-well (NW); 5 is N TOP; 6 is P TOP; 7 is a field oxide layer; 8 is a P Well (PW); 9 is source end N +; 10 is source end P +; 11 is the drain terminal N +; 12 is a gate oxide layer; and 13 is a polysilicon gate.
Fig. 10 is a schematic structural diagram of a RESURF LDMOS device having a field limiting ring structure in example 6.
Fig. 11 is a schematic structural diagram of a RESURF LDMOS device having a field limiting ring structure in example 7.
Detailed Description
Example 1
As shown in fig. 1, a RESURF LDMOS device having a field limiting ring structure includes a P-type semiconductor substrate 1, which is implemented by implanting boron ions as an impurity into single crystal silicon; a deep N well 2 and a deep P well 3, namely an N-type drift region main body, are arranged on a P-type semiconductor substrate 1 and are realized by injecting phosphorus ions by adopting an ion injection technology; an N well 4, a P-type strip 5, a P-type field limiting ring 6 and a field oxide layer 7 are arranged on the deep N well 2, wherein the P-type strip is rectangular and is equivalent to a cuboid as a whole from a device structure schematic diagram, namely a cross-sectional diagram; the P-type field limiting ring is a square ring, and the whole structure is equivalent to a cylindrical structure with a square section; different traps are realized by adopting an ion implantation technology and implanting different concentrations and energies; a P well 8 is arranged on the deep P well 3, the injection of the P well 8 is to reduce parasitic resistance, so that the on-resistance is reduced, and the P well 8 also comprises a source end N +9 and a source end P +10 which form ohmic contact; the N well 4 comprises a drain terminal N + 11; the upper end surface of the deep N well 2 is a gate oxide layer 12 and a polysilicon gate 13 from bottom to top.
The specific process implementation flow of the invention is as follows:
(1) and implanting boron ions into the monocrystalline silicon to obtain the P-type semiconductor substrate.
(2) The preparation of the deep N well is carried out by implanting phosphorus into the lightly doped P-type semiconductor substrate by means of ion implantation.
(3) The deep P well is formed by injecting boron into the source end and then performing high-temperature junction pushing for a long time in the later period. The deep P-well here can be used as a P-type isolation well. Similarly, the ion implanter is the main device required for forming the N-well, except that the energy required for implanting impurities into the P-well is significantly lower than that of the N-well.
(4) The formation of the field oxygen of the active area is realized by depositing silicon nitride, etching a silicon nitride window on the surface of the device by using a mask, wherein the window is the active area, and then growing a thick field oxide layer.
(5) The implantation of the N-well and the P-well requires three ion implantation techniques to implement the N-well region and the P-well region, respectively.
(6) The formation of the P TOP region is also achieved by implanting boron ions by ion implantation technique, with a dose of 2.7 × 1012cm-2. Implantation of the P TOP region to form a RESURF LDMOSA PN junction consisting of a P TOP area and an N-type drift area is added in the direction to assist in depletion, and the performance of the device is well improved.
(7) The formation of gate oxide and polysilicon is performed below, wherein the gate oxide is formed by combining two processes of dry oxygen and wet oxygen, so that the rapid growth of high-quality gate oxide is ensured. Polysilicon is then deposited on the surface of the device and the unwanted portions are etched away.
(8) And then, the source end N + and the source end P + are injected to form ohmic contact, and the source end N + and the source end P + are required to have heavy doping concentration so as to have small resistance. The formation of the source end N + and the source end P + is realized by two times of ion implantation respectively, the implantation energy and the implantation dosage are different, and the purpose is to reduce the concentration gradient between a source/drain and a trap and reduce the generation of leakage current.
(9) And finally, preparing a contact hole, metalizing and passivating.
Fig. 2 is a cross-sectional doping concentration distribution diagram of the device of the present example, and fig. 3 is a simulation result diagram of the drain current of the device of the present example changing with the drain voltage, at this time, the breakdown voltage value of the device is 575V, and the on-resistance value is 9.3 Ω · mm2。
Example 2
The present embodiment is different from embodiment 1 in that: the implantation dosage of the P TOP region in the step (6) is changed into 2.8 multiplied by 1012cm-2. Fig. 4 corresponds to a profile doping concentration profile of the device of this example, and fig. 5 corresponds to a graph of simulation results of drain current versus drain voltage of the device of this example. The simulation result showed that the breakdown voltage was 530V, and the on-resistance was 9.3. omega. mm2. Compared with embodiment 1, it can be found that under this condition, the on-resistance of the device is not changed, and the breakdown voltage is reduced to 530V instead.
Example 3
This embodiment is different from embodiment 1 in that a N TOP region 5 is provided above a P TOP region 6, as shown in fig. 6. The implantation dose of the P TOP region is 2.6X 1012cm-2. The implantation dose of the N TOP region is 1.0X 1012cm-2. FIG. 7 is a graph showing the result of simulation of the variation of drain current with drain voltage of the device of this example, under which the device has a breakdown voltage of 621V and an on-resistance of 8.22. omega. mm2。
Example 4
The present embodiment is different from embodiment 3 in that: the implantation dose of the N TOP region is changed to 1.5X 1012cm-2. FIG. 8 is a graph showing the simulation result of the variation of drain current with drain voltage of the device of this example, after increasing the implantation of phosphorus ions into the N TOP region, the breakdown voltage of the device is 518V, and the on-resistance of the device is 8.45 Ω · mm2。
Example 5
The present embodiment is different from embodiment 3 in that: the number of the N-type field limiting rings and the number of the P-type field limiting rings are two, the sections of the N-type field limiting rings and the P-type field limiting rings are square, the side length is 1 mu m, the horizontal distance from the N-type field limiting rings and the P-type field limiting rings to the N-type strips and the P-type strips is 2 mu m, and the horizontal distance between the adjacent field limiting rings is 3 mu m, as shown in FIG. 9. Under the condition, the breakdown voltage value of the device is 583V, and the on-resistance value is 7.8 omega mm2。
Example 6
This embodiment is different from embodiment 5 in that: the horizontal distance from the N-type field limiting rings and the P-type field limiting rings to the N-type strips and the P-type strips is 3 μm, and the horizontal distance between adjacent field limiting rings is 4 μm, as shown in fig. 10. The breakdown voltage value of the adjusted device is 579V, and the on resistance value of the device is 8.1 omega mm2。
Example 7
This embodiment is different from embodiment 5 in that: the horizontal distance from the N-type field limiting rings and the P-type field limiting rings to the N-type strips and the P-type strips is 1 μm, and the horizontal distance between adjacent field limiting rings is 1 μm, as shown in fig. 11. The breakdown voltage of the device after adjustment is 581V, and the on-resistance of the device is 8.3 omega mm2。
The invention has been described in an illustrative manner, and it is to be understood that any simple variations, modifications or other equivalent changes which can be made by one skilled in the art without departing from the spirit of the invention fall within the scope of the invention.
Claims (10)
1. A RESURF LDMOS device with a field limiting ring structure comprises a P-type semiconductor substrate, wherein a deep N well and a deep P well are arranged on the P-type semiconductor substrate, the P well is arranged in the deep P well, and a source end N + region and a source end P + region are arranged in the P well and positioned on the surface of the device; a field oxide layer is arranged on the upper end surface of the deep N well, one end of the field oxide layer is connected with the drain end N + region, and a gate oxide layer and a polysilicon gate are arranged on the other end of the field oxide layer; the polysilicon gate is arranged on the gate oxide layer, and the polysilicon gate and the gate oxide layer jointly extend to a source end N + region on the surface of the device; an N well and a P TOP region are arranged in the deep N well, and a drain terminal N + region is arranged in the N well and is positioned on the surface of the device; the P TOP region consists of P-type strips and P-type field limiting rings.
2. The RESURF LDMOS device of claim 1, wherein an NTOP region is formed above the P TOP region, the NTOP region comprising N-type strips and N-type field limiting rings.
3. The RESURF LDMOS device with the field limiting ring structure as claimed in claim 1 or 2, wherein the surface of the device is isolated by a silicon dioxide layer.
4. The RESURF LDMOS device having the field limiting ring structure as claimed in claim 1 or 2, wherein the number of the P-type field limiting rings is 1 to 5.
5. The RESURF LDMOS device having the field limiting ring structure of claim 2, wherein an N-type strap or an N-type field limiting ring is disposed over a P-type strap, and an N-type strap or an N-type field limiting ring is disposed over a P-type field limiting ring.
6. The RESURF LDMOS device with the field limiting ring structure as claimed in claim 2 or 5, wherein the number of the N-type field limiting rings is 1-5.
7. According to the claimsClaim 1 or 2 of the RESURF LDMOS device with the field limiting ring structure is characterized in that a P TOP region is implanted with boron ions, the junction depth is 1-5 mu m, and the doping concentration is 2.6 multiplied by 1012cm-2-3×1012cm-2。
8. The RESURF LDMOS device as claimed in claim 2, wherein the N TOP region is implanted with P ions with a junction depth of 1-5 μm and a doping concentration of 7.5 x 1011cm-2-2×1012cm-2。
9. The RESURF LDMOS device with the field limiting ring structure as claimed in claim 1 or 2, wherein the P-type field limiting rings have a square cross section, the side length is 1 μm, the horizontal distance from the P-type field limiting ring to the P-type bar is 1-3 μm, and the horizontal distance between adjacent P-type field limiting rings is 1-4 μm.
10. The RESURF LDMOS device having the field limiting ring structure as claimed in claim 2, wherein the N-type field limiting rings have a square cross section, a side length of 1 μm, a horizontal distance from the N-type field limiting ring to the N-type bar of 1-3 μm, and a horizontal distance between adjacent N-type field limiting rings of 1-4 μm.
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| CN117038704A (en) * | 2023-08-03 | 2023-11-10 | 南京邮电大学 | Composite field limiting ring circular layout transverse power device and preparation method thereof |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN103123935A (en) * | 2011-11-18 | 2013-05-29 | 上海华虹Nec电子有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103474466A (en) * | 2013-09-13 | 2013-12-25 | 电子科技大学 | High-voltage device and manufacturing method thereof |
| CN104617149A (en) * | 2015-01-30 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| CN106409883A (en) * | 2016-10-31 | 2017-02-15 | 上海晶丰明源半导体有限公司 | High voltage LDMOS device and the manufacturing method thereof |
| CN109378340A (en) * | 2018-09-22 | 2019-02-22 | 天津大学 | A double-well p-type LDMOS using multi-buried layer technology |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
-
2019
- 2019-08-08 CN CN201910746926.8A patent/CN112349764A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102005480A (en) * | 2010-10-28 | 2011-04-06 | 电子科技大学 | High-voltage low-on-resistance LDMOS device and manufacturing method thereof |
| CN103123935A (en) * | 2011-11-18 | 2013-05-29 | 上海华虹Nec电子有限公司 | NLDMOS (N-type laterally diffused metal oxide semiconductor) device and manufacturing method thereof |
| CN103474466A (en) * | 2013-09-13 | 2013-12-25 | 电子科技大学 | High-voltage device and manufacturing method thereof |
| CN104617149A (en) * | 2015-01-30 | 2015-05-13 | 上海华虹宏力半导体制造有限公司 | Isolation N-type laterally diffused metal oxide semiconductor (NLDMOS) device and manufacturing method thereof |
| CN106409883A (en) * | 2016-10-31 | 2017-02-15 | 上海晶丰明源半导体有限公司 | High voltage LDMOS device and the manufacturing method thereof |
| CN109378340A (en) * | 2018-09-22 | 2019-02-22 | 天津大学 | A double-well p-type LDMOS using multi-buried layer technology |
| CN109411527A (en) * | 2018-09-22 | 2019-03-01 | 天津大学 | A kind of N-type LDMOS using reduction surface field technology |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117038704A (en) * | 2023-08-03 | 2023-11-10 | 南京邮电大学 | Composite field limiting ring circular layout transverse power device and preparation method thereof |
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