CN117038704A - Composite field limiting ring circular layout transverse power device and preparation method thereof - Google Patents

Composite field limiting ring circular layout transverse power device and preparation method thereof Download PDF

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Publication number
CN117038704A
CN117038704A CN202310969940.0A CN202310969940A CN117038704A CN 117038704 A CN117038704 A CN 117038704A CN 202310969940 A CN202310969940 A CN 202310969940A CN 117038704 A CN117038704 A CN 117038704A
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region
limiting ring
semiconductor
field limiting
composite field
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姚佳飞
林琰琰
李昂
任嵩茗
刘安琪
刘宇遨
郭宇锋
李曼
张珺
陈静
杨可萌
张茂林
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Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
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Nanjing University Of Posts And Telecommunications Nantong Institute Co ltd
Nanjing University of Posts and Telecommunications
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Priority to CN202310969940.0A priority Critical patent/CN117038704A/en
Publication of CN117038704A publication Critical patent/CN117038704A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes

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Abstract

The invention discloses a composite field limiting ring circular layout transverse power device and a preparation method thereof, wherein the transverse power device comprises a substrate, an oxygen burying layer, an active layer, a composite field limiting ring, source electrode metal, grid electrode metal and drain electrode metal; the cross section of the transverse power device is circular or elliptical, and the active layer comprises a semiconductor drain region, a drift region and a semiconductor well region which are coaxially arranged in sequence from inside to outside; the composite field limiting rings are at least two, and are embedded in the top surface of the drift region at equal intervals by taking the center of the semiconductor drain region as the center of a circle; each composite field limiting ring comprises a P-type region and a medium region; the P-type region surrounds both sides and the bottom surface of the dielectric region. The high-K dielectric material of the composite field limiting ring can effectively modulate a surface electric field to avoid the influence of surface charges on the field limiting ring, thereby improving breakdown voltage; meanwhile, the doping concentration of the drift region is improved, and the on-resistance of the device is reduced. In addition, the gate dielectric, the field dielectric and the dielectric in the composite field limiting ring are made of the same dielectric material, so that the process difficulty is reduced.

Description

Composite field limiting ring circular layout transverse power device and preparation method thereof
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a transverse power device with a composite field limiting ring circular layout and a preparation method thereof.
Background
The transverse power device is used as an important component of a power integrated circuit, and is widely applied to the fields of communication electronics, automobile electronics, intelligent furniture and the like due to the advantages of small volume, easy integration, large breakdown voltage, low on-resistance, excellent conversion performance, good process compatibility and the like. How to reduce the on-resistance and other electrical characteristics of the lateral power device is one of the goals of device design. The field limiting ring terminal technology has the advantages that the field limiting ring of the terminal structure is deformed, the problem of specific on resistance is reduced, and the basic principle is that under the action of reverse bias voltage of a main junction, before the voltage does not reach breakdown voltage of the main junction, a depletion region of the main junction meets and overlaps with a depletion region of the field limiting ring, at the moment, the field limiting ring and the depletion region are in a punching state, so that the point position of the field limiting ring is improved, and at the moment, under the condition that the voltage is increased by the main junction, the field limiting ring plays a role of voltage division, so that the purpose of improving the breakdown voltage is achieved.
However, the conventional field limiting ring structure needs to gradually decrease the width of the field limiting ring from the main junction to the outside and gradually increase the distance between the main junction and the field limiting ring structure is very sensitive to the surface charge effect, especially the field limiting ring structure of the shallow plane junction, which can cause the breakdown voltage of the device to decrease or even the device to fail due to the influence of the surface electric field.
In addition, in order to make the field limiting ring have a certain distance from the surface of the drift region, the buried field limiting ring structure needs to control the implantation depth of impurities through ion implantation, which not only causes damage to the region between the field limiting ring and the surface of the drift region, but also has a certain challenge in controlling the impurity distribution.
Disclosure of Invention
The invention aims to solve the technical problems of the prior art, and provides a composite field limiting ring circular layout transverse power device and a preparation method thereof, wherein the composite field limiting ring circular layout transverse power device and the preparation method can improve the doping concentration of a drift region, reduce the on-resistance of the device and improve the breakdown voltage; meanwhile, the influence of the surface charge effect on the field limiting ring is overcome through the high-k medium, and the influence of the electric field concentration effect of the main junction on the breakdown voltage is solved through the composite field limiting ring.
In order to solve the technical problems, the invention adopts the following technical scheme:
a composite field limiting ring circular layout transverse power device comprises a substrate, an oxygen burying layer, an active layer, a composite field limiting ring, source metal, gate metal and drain metal.
The cross section of the transverse power device is circular or elliptical, and the substrate, the oxygen-buried layer and the active layer are sequentially arranged from bottom to top.
The active layer comprises a semiconductor drain region, a drift region and a semiconductor well region which are coaxially arranged in sequence from inside to outside.
The semiconductor drain region is arranged at the top center of the active layer and is cylindrical, and the drain metal is arranged at the top center of the semiconductor drain region.
And the source metal is distributed on the outer edge of the top of the semiconductor well region.
The gate metal is arranged on the top surface of the active layer adjacent to the source metal through the gate dielectric layer.
The composite field limiting rings are M and are embedded in the top surface of the drift region at equal intervals by taking the center of the semiconductor drain region as the center of a circle.
Each composite field limiting ring comprises a P-type region and a medium region; the P-type region surrounds both sides and the bottom surface of the dielectric region.
The depth of the P-type region in the composite field limiting ring is 0.1-1 micrometers; when the thickness of the active layer is less than 2 microns, the depth of the P-type region is half the thickness of the active layer.
The semiconductor well region comprises a semiconductor contact region and a semiconductor source region; the semiconductor contact area is positioned right below the source metal and is annular, and the annular width of the semiconductor contact area is smaller than that of the source metal; the semiconductor source region is in contact with the inner side wall of the semiconductor contact region and is annular.
The number M of the composite field limiting rings is selected according to the width of the drift region, and M is more than or equal to 2; when the width of the drift region is increased by 4-5 micrometers, 1 composite field limiting ring is required to be added.
The annular width of the P-type region and the annular width of the medium region in each composite field limiting ring synchronously change.
The annular width of the dielectric region in each composite field-limiting ring is equal or the annular width of the dielectric region in each composite field-limiting ring gradually increases from the source metal to the drain metal.
A field dielectric layer is distributed on the top surface of the active region between the source metal and the drain metal, wherein the field dielectric layer positioned right below the gate metal is formed into a gate dielectric layer; the field dielectric layer, the gate dielectric layer and the dielectric region in each composite field limiting ring are all the same high-K dielectric.
A preparation method of a composite field limiting ring circular layout transverse power device comprises the following steps.
Step 1, manufacturing an active layer: an oxygen buried layer and an active layer are sequentially arranged on a substrate; the buried oxide layer is used for electrical isolation between the active layer and the substrate;
step 2, etching the annular groove: etching M concentric annular grooves with equal spacing on the top surface of the active layer;
step 3, manufacturing a P-type region: and (3) taking the photoresist as a mask, and adopting an ion implantation process to implant boron ions into each annular groove to form a P-type region with a concave longitudinal section.
Step 4, manufacturing a semiconductor well region: and (3) adopting an ion implantation process, taking photoresist as a mask, and implanting low-concentration P-type semiconductor impurities into the top surface of the active layer outside the P-type region at the outermost layer to form a semiconductor well region communicated with the buried oxide layer.
Step 5, manufacturing a semiconductor contact region: and taking the photoresist as a mask, and adopting an ion implantation process to implant highly doped P-type semiconductor impurities on the top surface of the outer edge of the semiconductor well region to form a semiconductor contact region.
Step 6, manufacturing a semiconductor source region and a semiconductor drain region: and taking the photoresist as a mask, and adopting an ion implantation process to implant highly doped phosphorus ions into the middle annular region of the top surface of the semiconductor well region and the center of the top surface of the active layer, thereby forming a semiconductor source region and a semiconductor drain region.
Step 7, annealing, and pushing diffusion to form given impurity distribution;
step 8, depositing a dielectric material: depositing a dielectric material in each P-type region manufactured in the step 3 and on the top surface of the active layer, wherein the dielectric material deposited in each P-type region is formed into a dielectric region; the medium region and the corresponding P-type region together form a composite field limiting ring; and a dielectric material deposited on the top surface of the active layer to form a field dielectric layer.
Step 9, etching source-drain contact holes: the source-drain contact hole comprises a source contact hole and a drain metal hole; the source contact hole is etched at the outer edge of the field dielectric layer, and the drain metal hole is etched in the field dielectric layer right above the semiconductor drain region.
Step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact hole, depositing drain metal in the drain metal hole, and depositing gate metal on the top surface of the field dielectric layer right above the semiconductor well region between the semiconductor source region and the drift region; wherein the field medium under the gate metal is formed as a gate medium layer.
And (2) etching the annular groove by adopting a dry etching process.
The number of annular grooves in the step 2 is selected according to the width of the drift region, and is not less than 2; every 4-5 microns increase in drift region width, 1 annular groove is added.
The invention has the following beneficial effects:
1. the invention can improve the doping concentration of the drift region, reduce the on-resistance of the device and improve the breakdown voltage.
2. The P-type region of the composite field limiting ring can be mutually depleted with the N-type drift region to improve the concentration of the drift region, the high-k medium can further assist in depleting the drift region, and the surface electric field is modulated to solve the adverse effect of the surface charge effect on the field limiting ring, so that the on-resistance of the device is reduced, and the breakdown voltage of the device is improved.
3. When the composite field limiting rings are equal in distance and width, the difficulty of process design can be greatly reduced, and the composite field limiting rings can be realized only through conventional processes such as grooving, ion implantation, medium deposition and the like.
4. In the invention, the gate dielectric, the field dielectric and the dielectric in the composite field limiting ring are made of the same dielectric material, so that the process difficulty is reduced.
Drawings
Fig. 1 shows a schematic structure of a composite field limiting ring circular layout transverse power device of the invention.
Fig. 2 shows a schematic structure of the active layer manufactured in step 1 of the present invention.
Fig. 3 shows a schematic structural diagram of the annular groove after etching in step 2 in the present invention.
Fig. 4 is a schematic structural diagram of the P-type region fabricated in step 3 of the present invention.
Fig. 5 shows a schematic structure of the semiconductor well region fabricated in step 4 of the present invention.
Fig. 6 is a schematic structural diagram of a semiconductor contact region fabricated in step 5 of the present invention.
Fig. 7 shows a schematic structural diagram of a semiconductor source region and a semiconductor drain region fabricated in step 6 of the present invention.
FIG. 8 shows a schematic A-A' cross-section of the step 7 deposited dielectric material in accordance with the present invention.
FIG. 9 shows a schematic A-A' cross-section of a completed composite field limiting ring circular layout lateral power device in accordance with the present invention.
Fig. 10 shows a graph comparing breakdown voltage and specific on-resistance as a function of drift region doping concentration for a lateral power device provided by the present invention and conventional.
Fig. 11 shows a simulated potential line pattern of the present invention.
The method comprises the following steps: 1. a substrate, 2, an oxygen-buried layer, 3, an active layer, 4, annular grooves, 5, a semiconductor contact region, 6, a semiconductor source region, 7, a semiconductor well region, 8, a semiconductor drain region, 9 and a P-type region,
101-104 a high-k dielectric,
11. gate dielectric layer 12, source metal 13, drain metal 14, gate metal.
Detailed Description
The invention will be described in further detail with reference to the accompanying drawings and specific preferred embodiments.
In the description of the present invention, it should be understood that the terms "left", "right", "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element being referred to must have a specific orientation, be configured and operated in a specific orientation, and "first", "second", etc. do not indicate the importance of the components, and thus are not to be construed as limiting the present invention. The specific dimensions adopted in the present embodiment are only for illustrating the technical solution, and do not limit the protection scope of the present invention.
As shown in fig. 1 and 9, a composite field limiting ring circular layout transverse power device comprises a substrate 1, an oxygen buried layer 2, an active layer 3, a composite field limiting ring, a source metal 12, a gate metal 14 and a drain metal 13.
The cross section of the transverse power device is circular or elliptic, and the substrate, the oxygen-buried layer and the active layer are sequentially arranged from bottom to top.
The active layer includes a semiconductor drain region 8, a drift region, and a semiconductor well region 7 coaxially arranged in this order from the inside to the outside.
The semiconductor drain region is arranged at the top center of the active layer and is cylindrical, drain metal is arranged at the top center of the semiconductor drain region, and the radius of the semiconductor drain region is preferably larger than that of the drain metal.
Source metal is distributed on the outer edge of the top of the semiconductor well region; the gate metal is disposed on the top surface of the active layer adjacent to the source metal through the gate dielectric layer 11.
The semiconductor well region comprises a semiconductor contact region 5 and a semiconductor source region 6.
The semiconductor contact area is positioned right below the source metal and is annular, and the annular width of the semiconductor contact area is smaller than that of the source metal; the semiconductor source region is in contact with the inner side wall of the semiconductor contact region and is annular, and the semiconductor source region is partially positioned below the source metal.
The semiconductor contact region is used for eliminating parasitic transistor effect, and the semiconductor source region is used for collecting electrons flowing from a channel formed below the gate dielectric; and a gate dielectric layer is arranged below the gate metal and covers the semiconductor well region formed by double diffusion. When the gate voltage is greater than the threshold voltage, a channel is formed on the surface of the semiconductor well region, and the device is turned on. And a high-doped N-type semiconductor region, which is also called a semiconductor drain region, is arranged below the drain metal electrode, and an N-type drift region is arranged between the semiconductor drain region and the semiconductor well region.
The composite field limiting rings are M and are embedded in the top surface of the drift region at equal intervals by taking the center of the semiconductor drain region as the center of a circle. The number M of the composite field limiting rings is selected according to the width of the drift region, and M is more than or equal to 2; when the width of the drift region is increased by 4-5 micrometers, 1 composite field limiting ring is required to be added.
Each composite field limiting ring comprises a P-type region 9 and medium regions 101-104; the P-type region surrounds both sides and the bottom surface of the dielectric region, and is bilaterally symmetrical with respect to the dielectric region.
The depth of the P-type region in the composite field limiting ring is preferably 0.1-1 micron; the depth of the P-type region is too shallow, so that the ion implantation is not easy to control; the depth of the P-type region is too deep, and the grooving and filling processes are difficult to implement. Thus, when the active layer thickness is less than 2 microns, the P-type region depth is preferably half the active layer thickness.
The annular width of the P-type region and the annular width of the dielectric region in each composite field limiting ring can be synchronously changed.
When the annular widths of the medium regions in each composite field limiting ring are equal, the annular widths of the P-type regions in each composite field limiting ring are equal.
As the annular width of the dielectric region in each composite field-limiting ring increases gradually from the source metal to the drain metal, the annular width of the P-type region in each composite field-limiting ring will also vary synchronously with the annular width of the corresponding P-type region.
Further, a field dielectric layer is distributed on the top surface of the active region between the source metal and the drain metal, wherein the field dielectric layer right below the gate metal is formed into a gate dielectric layer; the field dielectric layer, the gate dielectric layer and the dielectric region in each composite field limiting ring are all the same high-K dielectric. The high-K dielectric herein refers to a dielectric material having a dielectric constant higher than that of silicon dioxide, and preferably has a dielectric constant of more than 20.
A preparation method of a composite field limiting ring circular layout transverse power device comprises the following steps.
Step 1, manufacturing an active layer: as shown in fig. 2, an oxygen buried layer and an active layer are sequentially arranged on a substrate; wherein the buried oxide layer is used for electrical isolation between the active layer and the substrate.
The active layer is a substrate with low concentration boron ions, and the substrate material may be silicon, silicon carbide, gallium nitride or gallium oxide semiconductor material with wide forbidden band.
Step 2, etching the annular groove: preferably, a dry etching process is used to etch M concentric and equally spaced annular grooves in the top surface of the active layer. The etching depth of each annular groove is preferably half the thickness of the active layer, the interval between each medium groove is controlled to be the same, and the structure after the annular grooves are formed is shown in fig. 3. The dry etching process is adopted because of high processing precision, compared with wet etching, the etching depth is convenient to control, and the etching anisotropy is good.
Further, the number of the annular grooves is selected according to the width of the drift region, and is not less than 2; every 4-5 microns increase in drift region width, 1 annular groove is added.
Step 3, manufacturing a P-type region: with photoresist as a mask, an ion implantation process is adopted to implant boron ions into each annular groove to form a P-type region 9 with a concave longitudinal section, as shown in fig. 4. Wherein the concentration of the P-type region is 1×10 15 cm -3 Up to 5X 10 17 cm -3 。
Step 4, manufacturing a semiconductor well region: and an ion implantation process is adopted, photoresist is used as a mask, and P-type semiconductor impurities with low concentration are implanted into the top surface of the active layer outside the P-type region at the outermost layer to form a semiconductor well region communicated with the buried oxide layer, as shown in fig. 5.
Step 5, manufacturing a semiconductor contact region: taking photoresist as a mask, adopting an ion implantation process, and implanting highly doped P-type semiconductor impurities into the top surface of the outer edge of the semiconductor well region to form a semiconductor contact region, wherein the semiconductor contact region is shown as 6; wherein the concentration of the P-type semiconductor impurity is not less than 1×10 19 cm -3 。
Step 6, manufacturing a semiconductor source region and a semiconductor drain region: taking photoresist as a mask, adopting an ion implantation process, and implanting highly doped phosphorus ions into the middle annular region of the top surface of the semiconductor well region and the center of the top surface of the active layer, thereby forming a semiconductor source region and a semiconductor drain region; wherein the concentration of the phosphorus ion is not less than 1X 10 20 cm -3 。
And 7, annealing, wherein the ion implantation damage is repaired by using an annealing process, and ion diffusion is promoted by using only one annealing process to form the given impurity distribution, and the structure is shown in figure 7.
Step 8, depositing a dielectric material: the dielectric material is preferably deposited in each P-type region and the top surface of the active layer manufactured in the step 2 by adopting a radio frequency magnetron sputtering deposition process, wherein the dielectric material deposited in the groove of each P-type region is formed into a dielectric region; the medium region and the corresponding P-type region together form a composite field limiting ring; the dielectric material deposited on the top surface of the active layer is formed into a gate dielectric layer, as shown in fig. 8.
The high-K dielectric material can be silicon dioxide, but is not limited to the silicon dioxide, and can modulate a surface electric field to solve the adverse effect of a surface charge effect on a composite field limiting ring, so that the breakdown voltage is improved, and the on-resistance of the device is reduced.
The gate dielectric material of conventional devices employs silicon dioxide because it can form a very desirable silicon interface with a silicon substrate. In the embodiment, a part of high-k medium reserved after the magnetic jet deposition is selected as a medium layer, so that a silicon dioxide gate medium layer is not required to be generated, and the process steps are saved.
Step 9, etching source-drain contact holes: the source-drain contact hole comprises a source contact hole and a drain metal hole; the source contact hole is etched at the outer edge of the field dielectric layer, and the drain metal hole is etched in the field dielectric layer right above the semiconductor drain region.
Step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact hole, depositing drain metal in the drain metal hole, and depositing gate metal on the top surface of the field dielectric layer right above the semiconductor well region between the semiconductor source region and the drift region, as shown in fig. 9; wherein the field medium under the gate metal is formed as a gate medium layer.
FIG. 10 is a graph showing the breakdown voltage of a composite field-limiting ring circular layout lateral power device (composite field-limiting ring device) and a conventional lateral power device without field-limiting ring (conventional device) and a lateral power device with P-type field-limiting ring (conventional field-limiting ring device) according to the variation of doping concentration of a drift region, wherein the composite field-limiting ring device and the conventional field-limiting ring deviceThe concentration of the P-type region of the ring device is 8 multiplied by 10 16 cm -3 The dielectric constant of the medium in the composite field limiting ring is 200, and other structural parameters are consistent. As can be seen from fig. 10, the maximum Breakdown Voltage (BV) of the composite field limiting ring device can be increased by 26% compared with the other two devices. And the drift region concentration corresponding to the maximum breakdown voltage is also the maximum, so that the transistor has smaller on-resistance (R on,sp ). When the device reaches the maximum breakdown voltage, the figure of merit (FOM) of the composite field limiting ring device provided by the invention can be improved by more than one time.
FIG. 11 is a simulated potential line diagram of the composite field limiting ring circular layout transverse power device provided by the invention. From the graph, the electric field intensity of the device is strongest near the drain region and the semiconductor well region, and the electric field intensity of the device is weakest at the position of the composite field limiting ring. The device is proved to have the advantages that the structure can well deplete the electric field of the drift region, optimize the surface electric field and prevent the device from being broken down in advance, so that the voltage resistance of the device is optimized, and the breakdown voltage of the device is improved. In fig. 11, the abscissa represents the lateral distance, and the ordinate represents the longitudinal distance.
The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to the specific details of the above embodiments, and various equivalent changes can be made to the technical solution of the present invention within the scope of the technical concept of the present invention, and all the equivalent changes belong to the protection scope of the present invention.

Claims (10)

1. A composite field limiting ring circular layout transverse power device is characterized in that: the device comprises a substrate, an oxygen burying layer, an active layer, a composite field limiting ring, source electrode metal, grid electrode metal and drain electrode metal;
the cross section of the transverse power device is circular or elliptical, and the substrate, the oxygen-buried layer and the active layer are sequentially arranged from bottom to top;
the active layer comprises a semiconductor drain region, a drift region and a semiconductor well region which are coaxially arranged in sequence from inside to outside;
the semiconductor drain region is arranged at the top center of the active layer and is cylindrical, and the drain metal is arranged at the top center of the semiconductor drain region;
the source metal is distributed on the outer edge of the top of the semiconductor well region;
the grid metal is arranged on the top surface of the active layer adjacent to the source metal through the grid dielectric layer;
the M composite field limiting rings are embedded in the top surface of the drift region at equal intervals by taking the center of the semiconductor drain region as the center of a circle;
each composite field limiting ring comprises a P-type region and a medium region; the P-type region surrounds both sides and the bottom surface of the dielectric region.
2. The composite field limiting ring circular layout transverse power device of claim 1, wherein: the depth of the P-type region in the composite field limiting ring is 0.1-1 micrometers; when the thickness of the active layer is less than 2 microns, the depth of the P-type region is half the thickness of the active layer.
3. The composite field limiting ring circular layout transverse power device of claim 1, wherein: the semiconductor well region comprises a semiconductor contact region and a semiconductor source region; the semiconductor contact area is positioned right below the source metal and is annular, and the annular width of the semiconductor contact area is smaller than that of the source metal; the semiconductor source region is in contact with the inner side wall of the semiconductor contact region and is annular.
4. The composite field limiting ring circular layout transverse power device of claim 1, wherein: the number M of the composite field limiting rings is selected according to the width of the drift region, and M is more than or equal to 2; when the width of the drift region is increased by 4-5 micrometers, 1 composite field limiting ring is required to be added.
5. The composite field limiting ring circular layout transverse power device of claim 1, wherein: the annular width of the P-type region and the annular width of the medium region in each composite field limiting ring synchronously change.
6. The composite field limiting ring circular layout transverse power device of claim 1, wherein: the annular width of the dielectric region in each composite field-limiting ring is equal or the annular width of the dielectric region in each composite field-limiting ring gradually increases from the source metal to the drain metal.
7. The composite field limiting ring circular layout transverse power device of claim 1, wherein: a field dielectric layer is distributed on the top surface of the active region between the source metal and the drain metal, wherein the field dielectric layer positioned right below the gate metal is formed into a gate dielectric layer; the field dielectric layer, the gate dielectric layer and the dielectric region in each composite field limiting ring are all the same high-K dielectric.
8. A preparation method of a composite field limiting ring circular layout transverse power device is characterized by comprising the following steps: the method comprises the following steps:
step 1, manufacturing an active layer: an oxygen buried layer and an active layer are sequentially arranged on a substrate; the buried oxide layer is used for electrical isolation between the active layer and the substrate;
step 2, etching the annular groove: etching M concentric annular grooves with equal spacing on the top surface of the active layer;
step 3, manufacturing a P-type region: taking photoresist as a mask, and adopting an ion implantation process to implant boron ions into each annular groove to form a P-type region with a concave longitudinal section;
step 4, manufacturing a semiconductor well region: an ion implantation process is adopted, photoresist is used as a mask, and P-type semiconductor impurities with low concentration are implanted into the top surface of the active layer outside the P-type region at the outermost layer to form a semiconductor well region communicated with the buried oxide layer;
step 5, manufacturing a semiconductor contact region: taking photoresist as a mask, adopting an ion implantation process, and implanting highly doped P-type semiconductor impurities into the top surface of the outer edge of the semiconductor well region to form a semiconductor contact region;
step 6, manufacturing a semiconductor source region and a semiconductor drain region: taking photoresist as a mask, adopting an ion implantation process, and implanting highly doped phosphorus ions into the middle annular region of the top surface of the semiconductor well region and the center of the top surface of the active layer, thereby forming a semiconductor source region and a semiconductor drain region;
step 7, annealing, and pushing diffusion to form given impurity distribution;
step 8, depositing a dielectric material: depositing a dielectric material in each P-type region manufactured in the step 3 and on the top surface of the active layer, wherein the dielectric material deposited in each P-type region is formed into a dielectric region; the medium region and the corresponding P-type region together form a composite field limiting ring; a dielectric material deposited on the top surface of the active layer to form a field dielectric layer;
step 9, etching source-drain contact holes: the source-drain contact hole comprises a source contact hole and a drain metal hole; the source contact hole is etched at the outer edge of the field dielectric layer, and the drain metal hole is etched in the field dielectric layer right above the semiconductor drain region;
step 10, depositing source metal, drain metal and gate metal: depositing source metal in the source contact hole, depositing drain metal in the drain metal hole, and depositing gate metal on the top surface of the field dielectric layer right above the semiconductor well region between the semiconductor source region and the drift region; wherein the field medium under the gate metal is formed as a gate medium layer.
9. The method for manufacturing the composite field limiting ring circular layout transverse power device according to claim 8, wherein the method comprises the following steps: and (2) etching the annular groove by adopting a dry etching process.
10. The method for manufacturing the composite field limiting ring circular layout transverse power device according to claim 8, wherein the method comprises the following steps: the number of annular grooves in the step 2 is selected according to the width of the drift region, and is not less than 2; every 4-5 microns increase in drift region width, 1 annular groove is added.
CN202310969940.0A 2023-08-03 2023-08-03 Composite field limiting ring circular layout transverse power device and preparation method thereof Pending CN117038704A (en)

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