CN102097481B - P-type super-junction transverse double-diffusion metal oxide semiconductor tube - Google Patents
P-type super-junction transverse double-diffusion metal oxide semiconductor tube Download PDFInfo
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Abstract
The invention discloses a P-type super-junction transverse double-diffusion metal oxide semiconductor tube, which comprises an N-type substrate, wherein the N-type substrate is provided with a super-junction structure and an N-type body region; the super-junction structure consists of a P-type epitaxial layer and an N-type semiconductor region embedded therein; the N-type body region is provided with a P-type source region, an N-type body contact region and a grid oxide layer; the super-junction structure is provided with a P-type drain region; a first type field oxide layer is arranged above the super-junction structure and positioned in a region beyond the P-type drain region; a polycrystalline silicon grid is arranged above the grid oxide layer and extends to the upper part of the first type field oxide layer from the upper part of the grid oxide layer; a second type field oxide layer is arranged above the P-type source region, the N-type body contact region, the P-type drain region, the polycrystalline silicon grid and the first type field oxide layer; the P-type source region, the P-type drain region, the N-type body contact region and the polycrystalline silicon grid are all connected with a source metal lead, a grid metal lead and a drain metal lead; and the depth of the N-type semiconductor region in the super-junction structure is linearly reduced in the direction from the P-type source region to the P-type drain region.
Description
Technical field
The present invention relates to a kind of silicon system high-voltage power metal oxide semiconductor device, say more accurately, relate to a kind of silicon system high-voltage P-type super-junction laterally dmost.
Background technology
At present; Power device in the application in fields such as daily life, production more and more widely; Power metal oxide semiconductor field-effect transistor particularly; Because they have switching speed, less drive current, the safety operation area of broad faster, therefore received numerous researchers' favor.Integrated power device mainly contains landscape insulation bar double-pole-type transistor and laterally double diffused metal oxide semiconductor in the power integrated circuit.Although the current driving ability of landscape insulation bar double-pole-type transistor is more intense; Yet be restricted, so still selection relatively preferably of laterally double diffused metal oxide semiconductor in the power integrated circuit of upper frequency because the existence of shutoff hangover electric current makes the power integrated circuit speed of using landscape insulation bar double-pole-type transistor improve.Nowadays, power device is just towards improving operating voltage, increase operating current, reducing conducting resistance and integrated direction fast development.In to laterally double diffused metal oxide semiconductor optimization in Properties process, the puncture voltage that improves device is the problem of a pair of contradiction with the conducting resistance that reduces device all the time.Depend on the lower and long drift region of doping content because the puncture voltage of device improves, and try one's best height and length of the drift region doping content that lowers the requirement of conducting resistance is short as far as possible.So in actual design process, often adopt trading off of the two to reach the optimization of device performance.Yet the theoretical application at semiconductor power device of ultra knot overcomes the contradiction between conventional power mos field effect transistor conducting resistance and the puncture voltage; Changed the conventional power device and relied on the withstand voltage structure in drift region, but adopted a kind of " super-junction structure "---the form that P type, N type silicon semiconductor material are alternately arranged in the drift region each other.This structure has been improved puncture voltage and the difficult situation about taking into account simultaneously of conducting resistance; When off-state; Because the depletion region electric field in P type post and the N type post produces mutual compensating effect, the doping content that makes P type post and N type post can be done very highly and can not cause the decline of device electric breakdown strength.During conducting, the doping of this high concentration obviously reduces the conducting resistance of device.Yet, have the problem of substrate-assisted depletion P type post in traditional super-junction laterally bilateral diffusion metal oxide semiconductor tube, cause N type post and P type post on every side when reverse biased, can not exhaust fully simultaneously and made puncture voltage be lower than theoretical value.The present invention is the modified model P type super-junction laterally bilateral diffusion metal oxide semiconductor tube structure that proposes to this problem equally.
Summary of the invention
The present invention is directed to the deficiency of prior art; A kind of P type super-junction laterally bilateral diffusion metal oxide semiconductor tube of effective inhibition substrate-assisted depletion effect is proposed; This structure can improve the withstand voltage properties of device under the prerequisite that does not increase technology manufacturing complexity and degree of difficulty.
The present invention adopts following technical scheme:
A kind of P type super-junction laterally dmost; Comprise: N type substrate; On N type substrate, be provided with super-junction structure and N type tagma; Super-junction structure is made up of with the N type semiconductor district that is embedded in the P type epitaxial loayer P type epitaxial loayer; Above N type tagma, be provided with P type source region, N type body contact zone and gate oxide, above super-junction structure, be provided with P type drain region, above super-junction structure; And the zone that is positioned at beyond the P type drain region is provided with the first type field oxide; Being provided with polysilicon gate and polysilicon gate above the gate oxide from extending to above the gate oxide above the first type field oxide, above P type source region, N type body contact zone, P type drain region, polysilicon gate and the first type field oxide, be provided with the second type field oxide, P type source region, P type drain region, N type body contact zone and polysilicon gate all are connected to source metal lead-in wire, drain metal lead-in wire and the gate metal lead-in wire of the break-through second type field oxide; It is characterized in that the degree of depth in the N type semiconductor district in the super-junction structure diminishes along linearity on the direction of pointing to P type drain region from P type source region.
Compared with prior art, the present invention has following advantage:
(1) in conventional P type super-junction laterally dmost (with reference to Fig. 6), P type columnar semiconductor district 11 equates with N type columnar semiconductor district 12 impurity concentrations and vertical degree of depth.When device P type drain terminal 14 applies high pressure, P type columnar semiconductor district 11 is exhausted with N type substrate 1 by N type columnar semiconductor district 12 simultaneously, and N type columnar semiconductor district 12 is then only exhausted by P type semiconductor district 11.The extra phenomenon that exhausts between N type substrate 1 and the P type columnar semiconductor district 11 causes the charge unbalance between N in the super-junction structure, the P columnar semiconductor district, causes puncture voltage sharply to reduce.P type super-junction laterally dmost among the present invention has adopted follow-on super-junction structure; Promptly in super-junction structure N type columnar semiconductor district 12 (with reference to the Fig. 1) or N type strip-shaped semiconductor region 12 (with reference to Fig. 4) degree of depth less than the thickness of P type epitaxial loayer 11; Make like this and below N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12, have certain thickness P type epitaxial loayer 11; To isolate substrate-assisted depletion effect, help to improve the puncture voltage of device to exhausting the interference phenomenon of back charge balance between P type epitaxial loayer 11 and N type columnar semiconductor district 12 or the N type strip-shaped semiconductor region 12 fully.
(2) in conventional P type super-junction laterally dmost (with reference to Fig. 6), when device P type drain terminal 14 applied high pressure, the depletion layer thickness in the P type substrate 1 increased in the direction along the end 4 sensing P type drain terminals 14 from P type source gradually.This effect in this variation explanation N type substrate 1 assisted depletion P type semiconductor district 11 of the depletion layer thickness in the N type substrate 1 strengthens on the direction of pointing to P type drain terminal 14 from P type source end 4 gradually; And this assisted depletion effect has reached maximum below P type drain terminal 14; Cause N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12 impurity not to be exhausted by P type columnar semiconductor district 11 fully, produce the charge unbalance phenomenon.The serious charge unbalance of this drain terminal of traditional devices causes device electric breakdown strength to descend significantly.And the degree of depth of N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12 linearity on the direction of pointing to P type drain regions 14 from P type source region 4 reduces in the super-junction structure of the P type super-junction laterally dmost among the present invention; And through the degree of depth of different N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12 rationally is set; Can realize pointing to that each impurity doping region exhausts fully on the direction of P type drain terminals 14 from P type source end 4; That is: in the super-junction structure in N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12 and the super-junction structure P type epitaxial loayer 11 exhaust in the horizontal direction; N type columnar semiconductor district 12 or N type strip-shaped semiconductor region 12 exhaust with P type epitaxial loayer 11 in the vertical directions of its below in the super-junction structure, and the P type epitaxial loayer 11 in the super-junction structure exhausts with N type substrate 1.The super-junction structure that on all directions, all exhausts entirely of each zone can effectively have been eliminated the substrate-assisted depletion effect in the conventional P type super-junction laterally dmost like this; Accomplish in the drift region charge balance between the P type epitaxial loayer and N type columnar semiconductor district or N type strip-shaped semiconductor region, make the puncture voltage of device increase substantially.
(3) the N type semiconductor district that is not limited in the super-junction structure of applicability of the present invention is made up of N type columnar semiconductor district separated from one another; With reference to Fig. 1; Equally also can be used for the N type semiconductor district and form, with reference to Fig. 4 by the N type strip-shaped semiconductor region that the direction along the 4 sensing P type drain regions 14 from P type source region is connected to each other to one.
Description of drawings
Fig. 1 is the three-dimensional structure sketch map of the P type super-junction laterally bilateral diffusion metal oxide semiconductor tube among the present invention.
Fig. 2 is the device profile structure chart of AA section among three-dimensional structure sketch map Fig. 1 of the P type super-junction laterally bilateral diffusion metal oxide semiconductor tube among the present invention.
Fig. 3 is the device profile structure chart of BB section among three-dimensional structure sketch map Fig. 1 of the P type super-junction laterally bilateral diffusion metal oxide semiconductor tube among the present invention.
Fig. 4 is the three-dimensional structure sketch map of other a kind of P type super-junction laterally bilateral diffusion metal oxide semiconductor tube among the present invention.
Fig. 5 is the device profile structure chart of AA section among three-dimensional structure sketch map Fig. 4 of other a kind of P type super-junction laterally bilateral diffusion metal oxide semiconductor tube among the present invention.
Fig. 6 is the three-dimensional structure sketch map of conventional P type super-junction laterally bilateral diffusion metal oxide semiconductor tube.
Fig. 7 is the OFF state puncture voltage size comparison diagram of the P type super-junction laterally bilateral diffusion metal oxide semiconductor tube of three kinds of different structures, and the puncture voltage of visible structure of the present invention is the highest.
Embodiment
With reference to Fig. 1; A kind of P type super-junction laterally dmost; Comprise: N type substrate 1; On N type substrate 1, be provided with super-junction structure and N type tagma 2, super-junction structure is made up of with the N type semiconductor district 12 that is embedded in the P type epitaxial loayer 11 P type epitaxial loayer 11, above N type tagma 2, is provided with P type source region 4, N type body contact zone 5 and gate oxide 3; Above super-junction structure, be provided with P type drain region 14; Above super-junction structure, and the zone that is positioned at beyond the P type drain region 14 is provided with the first type field oxide 10, is being provided with polysilicon gate 6 and polysilicon gate 6 above the gate oxide 3 from extending to above the gate oxide 3 above the first type field oxide 10; Above P type source region 4, N type body contact zone 5, P type drain region 14, polysilicon gate 6 and the first type field oxide 10, be provided with the second type field oxide 8; P type source region 4, P type drain region 14, N type body contact zone 5 and polysilicon gate 6 all are connected to source metal lead-in wire 7, drain metal lead-in wire 13 and the gate metal lead-in wire 9 of the break-through second type field oxide 8, it is characterized in that, the degree of depth in the N type semiconductor district 12 in the super-junction structure diminishes along linearity on the direction of pointing to P type drain region 14 from P type source region 4.
Also adopt following technical measures to come further to improve performance of the present invention in the present embodiment:
N type semiconductor district 12 in the described super-junction structure can adopt repeatedly the outer ion implantation technology of delaying to form, and also can form through adopting anisotropic dry etch process to form groove and filling N type doped semiconductor materials.
The width in the N type semiconductor district 12 in the described super-junction structure equals the spacing between adjacent two N type semiconductor districts 12 recently.
The impurity concentration in the N type semiconductor district 12 in the described super-junction structure equals the impurity concentration of the P type epitaxial loayer 11 in the super-junction structure.
Described polysilicon gate 6 can extend to the first type field oxide, 10 tops, forms the crystal silicon field plate, further reduces the surface field peak value, to improve device electric breakdown strength.
Described drain terminal metal electrode 13 can extend to the first type field oxide, 10 tops, forms drain terminal metal field plate, reduces the surface field peak value near P type drain terminal 14, to improve device electric breakdown strength.
The present invention can adopt following method to prepare:
1, selects the substrate of a N type silicon chip as device, the epitaxial loayer of epitaxial growth one deck doping p type impurity on N type substrate then.
2, requiring the degree of depth maximum place in N type columnar semiconductor district to carry out surface ion injection phosphorus then; And the epitaxial loayer of continuation epitaxial growth one deck doping p type impurity, then requiring degree of depth place maximum and that take second place in N type columnar semiconductor district to carry out surface ion phosphorus.The epitaxial loayer of this continued epitaxial growth doping p type impurity, and carry out surface ion one by one in the place in needs formation N type columnar semiconductor district and inject phosphorus, need inject the places that form N type columnar semiconductor district until all and all accomplish surface ion injection phosphorus.Anneal then and form N type columnar semiconductor district.
3, inject phosphorus at surface ion then, and annealing pushes away trap, formation N type tagma, then the grow first type field oxide, gate oxide, deposit polysilicon and etching formation polysilicon gate then.
4, carry out the source then respectively and leak injection formation P type source region, P type drain region and N type body contact zone.
5, the second type field oxide of growing then, and carve source region, drain region and grid region contact hole, deposited metal and carry out etching forms source metal, drain metal and the gate metal of P type super-junction laterally dmost then.At last entire device is carried out Passivation Treatment.
The present invention also can adopt following method to prepare:
1, selects the substrate of a N type silicon chip as device, the epitaxial loayer of epitaxial growth one deck doping p type impurity on N type substrate then.
2, inject phosphorus at surface ion then; And annealing pushes away trap; Form N type tagma, carry out anisotropic plasma etch P type epitaxial loayer with formation silicon groove in the place of needs formation N type strip-shaped semiconductor region then, and formed N type strip-shaped semiconductor region with N type semiconductor material filling silicon groove.
3, then the grow first type field oxide, gate oxide, deposit polysilicon and etching form polysilicon gate then.
4, carry out the source then respectively and leak injection formation P type source region, P type drain region and N type body contact zone.
5, the second type field oxide of growing then, and carve source region, drain region and grid region contact hole, deposited metal and carry out etching forms source metal, drain metal and the gate metal of P type super-junction laterally dmost then.At last entire device is carried out Passivation Treatment.
Claims (3)
1. P type super-junction laterally dmost; Comprise: N type substrate (1); On N type substrate (1), be provided with super-junction structure and N type tagma (2); Super-junction structure is by P type epitaxial loayer (11) and be embedded in N type semiconductor district (12) formation in the P type epitaxial loayer (11); Be provided with P type source region (4), N type body contact zone (5) and gate oxide (3) in top, N type tagma (2); Above super-junction structure, be provided with P type drain region (14); Above super-junction structure, and be positioned at zone in addition, P type drain region (14) and be provided with the first type field oxide (10), be provided with polysilicon gate (6) in gate oxide (3) top and polysilicon gate (6) extends to the first type field oxide (10) top from gate oxide (3) top; In P type source region (4), N type body contact zone (5), P type drain region (14), polysilicon gate (6) and the first type field oxide (10) top be provided with the second type field oxide (8); P type source region (4), P type drain region (14), and polysilicon gate (6) be connected to source metal lead-in wire (7), drain metal lead-in wire (13) and the gate metal lead-in wire (9) of the break-through second type field oxide (8) respectively, it is characterized in that the degree of depth in the N type semiconductor district (12) in the super-junction structure diminishes along linearity on the direction in sensing P type drain region, P type source region (4) (14).
2. P type super-junction laterally dmost according to claim 1 is characterized in that, the N type semiconductor district (12) in the super-junction structure is N type columnar semiconductor district.
3. P type super-junction laterally dmost according to claim 1 is characterized in that the N type semiconductor district (12) in the super-junction structure is a N type strip-shaped semiconductor region.
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| CN102623345B (en) * | 2012-03-21 | 2014-08-20 | 中国科学院上海微系统与信息技术研究所 | Embedded multi-N-island P-channel hyperconjugation device and preparation method thereof |
| CN108767013A (en) * | 2018-06-05 | 2018-11-06 | 电子科技大学 | A kind of SJ-LDMOS devices with part buried layer |
| CN110808287B (en) * | 2019-10-31 | 2023-10-17 | 东南大学 | Superior quality factor transverse double-diffusion metal oxide semiconductor device |
| CN111244157B (en) * | 2020-01-20 | 2021-12-03 | 电子科技大学 | Lateral semiconductor device and manufacturing method thereof |
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| US7436025B2 (en) * | 2006-09-29 | 2008-10-14 | Freescale Semiconductor, Inc. | Termination structures for super junction devices |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN201904341U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | P type hyperconjugation lateral double diffusion metal oxide semiconductor tube |
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Patent Citations (3)
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| US7436025B2 (en) * | 2006-09-29 | 2008-10-14 | Freescale Semiconductor, Inc. | Termination structures for super junction devices |
| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN201904341U (en) * | 2010-12-22 | 2011-07-20 | 东南大学 | P type hyperconjugation lateral double diffusion metal oxide semiconductor tube |
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