CN101771081B - N-type super-junction transverse double-diffusion semiconductor metallic oxide transistor - Google Patents
N-type super-junction transverse double-diffusion semiconductor metallic oxide transistor Download PDFInfo
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- CN101771081B CN101771081B CN2009102632984A CN200910263298A CN101771081B CN 101771081 B CN101771081 B CN 101771081B CN 2009102632984 A CN2009102632984 A CN 2009102632984A CN 200910263298 A CN200910263298 A CN 200910263298A CN 101771081 B CN101771081 B CN 101771081B
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Abstract
The invention relates to an N-type super-junction transverse double-diffusion semiconductor metallic oxide transistor which comprises a P-type substrate, wherein a super-junction structure and a P-type body region are arranged on the P-type substrate; the super-junction structure consists of an N-type region and a P-type region which are connected to the direction of a source region and a drain region and distributed at intervals; an N-type source region, a P-type body contact region and a gate oxide layer are arranged above the P-type body region, and an N-type drain region is arranged above the super-junction structure; a first type field oxide layer is arranged in a region beyond the N-type drain region above the super-junction structure; a polysilicon gate is arranged above the gate oxide layer; a second type field oxide layer is arranged above the N-type resource region, the P-type body contact region, the N-type drain region, the polysilicon gate and the first type field oxide layer; and the N-type source region, the N-type drain region, the P-type body contact region and the polysilicon gate are all connected with a metal lead passing through the second type field oxide layer. The transistor is characterized in that the P-type substrate is internally provided with an N-type buffer region which is arranged below the P-type region in the super-junction structure and connected with the bottom of the P-type region in the super-junction structure.
Description
Technical field
The present invention relates to the power semiconductor field, is the structure that is applicable to the super-junction laterally double diffused metal oxide semiconductor of high-voltage applications about a kind of.
Background technology
Along with energy-conservation demand strengthens day by day, the performance of power integrated circuit product more and more receives publicity, and wherein the power loss of circuit is undoubtedly one of main performance index.The factor of decision power integrated circuit power loss size except the circuit structure of power integrated circuit own, design, the manufacturing process that circuit adopted, the power device performance that is adopted is the key of power integrated circuit power loss size.
At present, the manufacturing process according to power integrated circuit mainly is divided into based on body silicon, extension and silicon-on-insulator (SOI).Wherein, bulk silicon technological is because there is more defective in silicon face layer, so the large scale integrated circuit mainly adopts this technology in early days; Silicon-on-insulator (SOI) technology is owing to exist insulating barrier that surface silicon and substrate silicon layer are isolated, insulating barrier is generally silica in addition, vertical puncture voltage of the device of this technology of employing is higher like this, simultaneously substrate current there is good restraining, help reducing the power consumption of device, yet, cause the heat dissipation problem of power integrated circuit more serious, and the disk cost of silicon-on-insulator process is higher because the heat-sinking capability of silicon oxide layer is 1/100 of a silicon layer; Epitaxy technique has solved the blemish problem that bulk silicon technological exists well, has heat dispersion preferably simultaneously, so still wide based on the power integrated circuit prospect of epitaxy technique.
Integrated power device mainly contains landscape insulation bar double-pole-type transistor and laterally double diffused metal oxide semiconductor in the power integrated circuit.Although the current driving ability of landscape insulation bar double-pole-type transistor is more intense, yet be restricted, so still selection relatively preferably of laterally double diffused metal oxide semiconductor in the power integrated circuit of upper frequency because the existence of shutoff hangover electric current makes the power integrated circuit speed of using landscape insulation bar double-pole-type transistor improve.
In laterally double diffused metal oxide semiconductor optimization in Properties process, the puncture voltage that improves device is the problem of a pair of contradiction with the conducting resistance that reduces device all the time.Depend on the lower and long drift region of doping content because the puncture voltage of device improves, and try one's best height and length of the drift region doping content that lowers the requirement of conducting resistance is short as far as possible.So in actual design process, often adopt trading off of the two to reach the optimization of device performance.The laterally double diffused metal oxide semiconductor of super-junction structure has been proposed for this reason recently, the proposition of this structure mainly is the drift region of adopting super-junction structure, be implemented in the puncture voltage that does not reduce device when improving the drift region doping content, even the raising device electric breakdown strength, thereby reach optimization in Properties.Yet, present super-junction laterally double diffused metal oxide semiconductor is owing to exist the influence of substrate-assisted depletion factor, performance also has the leeway of improving, and the present invention is exactly the improvement structure super-junction laterally double diffused metal oxide semiconductor that proposes at this problem.
Summary of the invention
The invention provides a kind of puncture voltage that can effectively improve the laterally double diffused metal oxide semiconductor device, and can reduce the N type super-junction laterally double diffused metal oxide semiconductor of laterally double diffused metal oxide semiconductor break-over of device resistance.
The present invention adopts following technical scheme:
A kind of N type super-junction laterally double diffused metal oxide semiconductor, comprise: P type substrate, on P type substrate, be provided with super-junction structure and P type tagma, super-junction structure is made of N type district and the p type island region that connection source-drain area direction distributes alternately, above P type tagma, be provided with N type source region, P type body contact zone and gate oxide, above super-junction structure, be provided with N type drain region, above super-junction structure, and the zone that is positioned at beyond the N type drain region is provided with the first type field oxide, above gate oxide, be provided with polysilicon gate, in N type source region, P type body contact zone, N type drain region, polysilicon gate and first type field oxide top are provided with the second type field oxide, N type source region, N type drain region, P type body contact zone and polysilicon gate all are connected to the metal lead wire of the break-through second type field oxide, it is characterized in that in P type substrate, being provided with N type buffering area, N type buffering area is arranged in the below of super-junction structure p type island region, and with super-junction structure in the p type island region bottom connection.
Compared with prior art, the present invention has following advantage:
(1) the N type super-junction laterally double diffused metal oxide semiconductor among the present invention has adopted new construction, that is: in super-junction structure, added N type buffering area 15 below the p type island region 12 and between the P type substrate 1, can effectively eliminate the adverse effect that the substrate-assisted depletion effect between the N type district 11 brings in 1 pair of super-junction structure of P type substrate of traditional N type super-junction laterally double diffused metal oxide semiconductor with respect to traditional N type super-junction laterally double diffused metal oxide semiconductor (Fig. 4), thereby can further improve device electric breakdown strength, reduce break-over of device resistance, finally reach the raising device performance.
(2) the N type super-junction laterally double diffused metal oxide semiconductor among the present invention adopts the N type buffering area 15 that separates, adopt whole N type buffering area 16 with respect to other N type super-junction laterally double diffused metal oxide semiconductors (Fig. 5), whole N type buffering area 16 can only realize that N type district 11 isolates in P type substrate 1 and the super-junction structure, on certain Cheng Du, reduced substrate-assisted depletion effect, yet introduced the assisted depletion effect of p type island region 12 and whole N type buffering area 16 (Fig. 5) in the super-junction structure, this is that we are undesirable.Structure of the present invention has realized, the space of three directions except super knot superficial layer exhausts, that is: in the surperficial super-junction structure in p type island region 12 and the super-junction structure two sides between the N type district 11 exhaust, exhausting between p type island region 12 bottoms and its N type buffering area 15 tops, below in the super-junction structure, exhausting between 11 bottoms, N type district and P type substrate 1 top in the super-junction structure, the both sides of N type buffering area 15 and bottom all exhaust with P type substrate 1, like this exhaust the adverse effect that structure has effectively been eliminated assisted depletion effect entirely, make full use of super-junction structure, be of value to the raising device electric breakdown strength, simultaneously under the prerequisite of same breakdown voltage, be of value to the conducting resistance that reduces device, reduce chip area.
Description of drawings
Fig. 1 is the 3 D stereo profile, illustrates the three-dimensional cross-section structure of N type super-junction laterally double diffused metal oxide semiconductor embodiment of the present invention.
Fig. 2 is a profile, illustrates the device profile structure of AA section in the N type super-junction laterally double diffused metal oxide semiconductor 3 D stereo profile 1 of the present invention.
Fig. 3 is a profile, illustrates the device profile structure of BB section in the N type super-junction laterally double diffused metal oxide semiconductor 3 D stereo profile 1 of the present invention.
Fig. 4 is the 3 D stereo profile, illustrates the three-dimensional cross-section structure of traditional N type super-junction laterally double diffused metal oxide semiconductor embodiment.
Fig. 5 is the 3 D stereo profile, illustrates the three-dimensional cross-section structure of the N type super-junction laterally double diffused metal oxide semiconductor embodiment that has the integrated buffer plot structure.
Fig. 6 is the device analog simulation result, illustrates the ON state current ability size of three kinds of structure N type super-junction laterally double diffused metal oxide semiconductors, and more the low current driving force is stronger for visible break-over of device resistance of the present invention.
Fig. 7 is the device analog simulation result, illustrates the OFF state puncture voltage size of three kinds of structure N type super-junction laterally double diffused metal oxide semiconductors, and the puncture voltage of visible structure of the present invention is higher.
Embodiment
Below in conjunction with accompanying drawing 1, the present invention is elaborated, a kind of N type super-junction laterally double diffused metal oxide semiconductor, comprise: P type substrate 1, on P type substrate 1, be provided with super-junction structure and P type tagma 2, super-junction structure is made of N type district 11 and the p type island region 12 that connection source-drain area direction distributes alternately, above P type tagma 2, be provided with N type source region 4, P type body contact zone 5 and gate oxide 3, above super-junction structure, be provided with N type drain region 14, above super-junction structure, and the zone that is positioned at beyond the N type drain region 14 is provided with the first type field oxide 10, above gate oxide 3, be provided with polysilicon gate 6, in N type source region 4, P type body contact zone 5, N type drain region 14, polysilicon gate 6 and the first type field oxide, 10 tops are provided with the second type field oxide 8, N type source region 4, N type drain region 14, P type body contact zone 5 and polysilicon gate 6 all are connected to the metal lead wire of the break-through second type field oxide 8, it is characterized in that in P type substrate 1, being provided with N type buffering area 15, N type buffering area 15 is arranged in the below of super-junction structure p type island region 12, and with super-junction structure in p type island region 12 bottom connections.
The width of p type island region 12 equates with the width of corresponding N type buffering area 15 in the described super-junction structure, also can be not exclusively equal.
Described N type buffering area 15 can form by the mode that energetic ion injects with buried layer.
P type island region 12 doping contents are suitable in described N type buffering area 15 doping contents and the top super-junction structure.
Described N type buffering area 15 can inject by ion, and the mode of carrying out surperficial extension then forms.
Described N type buffering area 15 bottoms not necessarily will be positioned at same horizontal plane with 2 bottoms, P type tagma, need and decide according to actual design.
In the described super-junction structure in N type district 11 and the super-junction structure p type island region 12 doping contents suitable, need and decide according to actual design.
In the described super-junction structure in N type district 11 and the super-junction structure p type island region 12 width suitable, need and decide according to actual design.
Described polysilicon gate 6 can extend to the first type field oxide, 10 tops, forms the crystal silicon field plate, further reduces surface field, improves device electric breakdown strength.
Described drain terminal metal electrode 13 can extend to the first type field oxide, 10 tops, forms drain terminal metal field plate, further reduces surface field, improves device electric breakdown strength.
The present invention adopts following method to prepare:
The first step, get P type substrate, it is carried out prerinse, preparation N type buffering area on P type substrate, the N type of growing then epitaxial loayer, logical ion injects and elevated temperature heat diffuses to form P type tagma, on N type epitaxial loayer, make p type island region in the width super-junction structure suitable directly over the N type buffering area, form N type district in the super-junction structure simultaneously, then carry out the growth of the first type field oxide again with N type buffering area, carrying out an oxygen then injects, the adjustment channel threshold voltage is injected, growth of gate oxide layer, and the deposit etch polysilicon forms polysilicon gate and polysilicon field plate, the source is leaked to inject and is formed N type source region, N type drain region and P type body contact zone, the deposit second type field oxide then.
Second step: the etching second type oxide layer, form the metal electrode fairlead of N type source region, N type drain region, P type body contact zone and polysilicon gate, deposited metal, etching sheet metal forms the N type source region of N type super-junction laterally double diffused metal oxide semiconductor and extraction electrode, N type drain region extraction electrode and the polysilicon gate extraction electrode of P type body contact zone, carries out Passivation Treatment at last.
Claims (2)
1. N type super-junction laterally double diffused metal oxide semiconductor, comprise: P type substrate (1), on P type substrate (1), be provided with super-junction structure and P type tagma (2), super-junction structure is by connecting N type district (11) and p type island region (12) formation that the source-drain area direction distributes alternately, be provided with N type source region (4) in top, P type tagma (2), P type body contact zone (5) and gate oxide (3), above super-junction structure, be provided with N type drain region (14), above super-junction structure, and be positioned at zone in addition, N type drain region (14) and be provided with the first type field oxide (10), be provided with polysilicon gate (6) in gate oxide (3) top, in N type source region (4), P type body contact zone (5), N type drain region (14), polysilicon gate (6) and the first type field oxide (10) top are provided with the second type field oxide (8), N type source region (4), N type drain region (14), P type body contact zone (5) and polysilicon gate (6) all are connected to the metal lead wire of the break-through second type field oxide (8), it is characterized in that in P type substrate (1), being provided with N type buffering area (15), N type buffering area (15) is arranged in the below of super-junction structure p type island region (12), and with super-junction structure in p type island region (12) bottom connection.
2. N type super-junction laterally double diffused metal oxide semiconductor according to claim 1, the width that it is characterized in that p type island region in the super-junction structure (12) equates with the width of corresponding N type buffering area (15).
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| CN101771081B true CN101771081B (en) | 2011-04-20 |
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| CN101916780A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | LDMOS device with multilayer super-junction structure |
| TWI415173B (en) * | 2011-05-19 | 2013-11-11 | Anpec Electronics Corp | Method for fabricating a super junction power device with reduced miller capacitance |
| CN109980011A (en) * | 2017-12-28 | 2019-07-05 | 无锡华润上华科技有限公司 | A kind of semiconductor devices and preparation method thereof |
| CN112768521B (en) * | 2019-10-21 | 2022-08-12 | 东南大学 | Lateral double-diffused metal oxide semiconductor device |
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| CN1744329A (en) * | 2004-08-31 | 2006-03-08 | 株式会社电装 | Semiconductor device having super junction structure and method for manufacturing the same |
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| CN1744329A (en) * | 2004-08-31 | 2006-03-08 | 株式会社电装 | Semiconductor device having super junction structure and method for manufacturing the same |
| CN1909245A (en) * | 2005-08-01 | 2007-02-07 | 半导体元件工业有限责任公司 | Semiconductor structure with improved on resistance and breakdown voltage performance |
| CN101506940A (en) * | 2006-08-25 | 2009-08-12 | 飞思卡尔半导体公司 | Superjunction trench device and method |
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