CN101916780A - LDMOS device with multilayer super-junction structure - Google Patents
LDMOS device with multilayer super-junction structure Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 31
- 239000000463 material Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 6
- 239000002210 silicon-based material Substances 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 5
- 229910052594 sapphire Inorganic materials 0.000 claims description 4
- 239000010980 sapphire Substances 0.000 claims description 4
- 238000000034 method Methods 0.000 abstract description 13
- 230000000694 effects Effects 0.000 abstract description 5
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- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000002347 injection Methods 0.000 description 3
- 239000007924 injection Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
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- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention discloses an LDMOS device with a multilayer super-junction structure. An active region of the device comprises a grid region, a source region and a drain region positioned on two sides of the grid region, a body region positioned under the grid region, and the multilayer super-junction structure positioned between the body region and the drain region, wherein the multilayer super-junction structure comprises at least two layers of super-junction structures arranged from bottom to top in turn; each layer of super-junction structure consists of n-type columnar regions and p-type columnar regions which are transversely and alternately arranged, preferably, the n-type columnar regions and the p-type columnar regions of upper and lower layers of super-junction structures are alternately arranged. The multilayer super-junction structure of the device can further improve the contact area among the n-type columnar regions and the p-type columnar regions, and simultaneously a method for manufacturing the structure cannot bring obvious side effects, so the anti-breakdown capacity of the device can be ensured to be higher than that of the conventional super-junction LDMOS device, and the multilayer super-junction structure also has high expansibility.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET), especially a kind of LDMOS device with multi-layer super-junction structure belongs to technical field of manufacturing semiconductors.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit).Be primarily characterized in that to add one section relatively long light dope drift region between channel region and the drain region, this drift region doping type is consistent with drain terminal, by adding the drift region, can play the effect of sharing puncture voltage.
So-called super junction LDMOS is a kind of modified model LDMOS, and promptly the low-doped N type drift region of traditional LDMOST is replaced by one group of n type post district that alternately arranges and p type post district.In theory, because the charge compensation between the p/n post district, super junction LDMOS can obtain very high puncture voltage, and highly doped N type post district then can obtain very low conducting resistance, and therefore super junction device can be obtained a good balance between puncture voltage and conducting resistance.
The super junction LDMOS device, its essence is that introducing pn in the drift region ties, when device is operated in maximum breakdown voltage following time, the drift region can exhaust as far as possible fully, like this, except having born the main voltage in n post district, pn post district depletion layer has at the interface also been born part voltage, thus the higher puncture voltage that can bear than traditional LDMOS.
Generally, in order to make the device of identical drift region length and width under maximum breakdown voltage, exhaust as far as possible fully, can dwindle the width in p/n post district, improve the degree of depth in p/n post district, promptly improve the depth-to-width ratio in post district as far as possible, its essence is the contact area that increases between the p/n post district, that is the p/n that increases inside, drift region ties the area of depletion region, yet limit by process conditions, can't further obtain the less post sector width and the darker post district degree of depth, this be because: at first, in the super junction device high energy ion injection process afterwards, need carry out annealing in process, narrow like this post district causes the diffuse pollution each other of dissimilar impurity easily, cause the imbalance of p/n post district internal charge, can reduce actual breakdown characteristics; Secondly, cross dark post district and certainly will follow high-octane ion to inject, cause the device inside damage easily, and the inner Impurity Distribution in post district is very inhomogeneous, still can bring the problem of the interval charge unbalance of adjacent p/n post, thereby performance is worn in the actual resistance that reduces device.
Given this, the present invention proposes a kind of SOILDMOS device with multi-layer super-junction structure, can further improve the contact area in p/n post interval, improves the device breakdown characteristics.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of LDMOS device with multi-layer super-junction structure, improves the device breakdown characteristics.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of LDMOS device with multi-layer super-junction structure, comprise substrate and be positioned at active area on the substrate, its active area comprises: grid region, the multi-layer super-junction structure in the source region of both sides, described grid region and drain region, in the tagma under the described grid region, between described tagma and described drain region; Described multi-layer super-junction structure comprises the two-layer at least super-junction structure that is arranged in order from the bottom to top, and every layer of super-junction structure is made up of the n type post district and the p type post district of laterally alternately arranging.
As preferred version of the present invention, in multi-layer super-junction structure, the n type post district of upper strata super-junction structure is corresponding with the p type post district and the n type post zone position of its lower floor's super-junction structure respectively with p type post district, and the n type post district of levels super-junction structure and p type post district are staggered.Wherein, the width in n type post district and the degree of depth respectively with the width and the deep equality in p type post district; Width is 0.5um-1.5um, and its degree of depth is 1um-2um.
As preferred version of the present invention, around its active area, be provided with groove isolation construction.Described substrate preferably has the substrate of insulating buried layer, also can be other various types of substrates such as body silicon substrate or Sapphire Substrate.When choosing (SOI) substrate with insulating buried layer, this device active region also comprises the body contact zone, and this body contact zone can be positioned at the side, source region and contact with the tagma.
Wherein, described grid region comprises gate dielectric layer and the gate material layer that is positioned on the gate dielectric layer, and described gate material layer can adopt polycrystalline silicon material.
Beneficial effect of the present invention is:
The present invention is under existing process conditions, under the maximum depth-to-width ratio situation that established technology can satisfy, make the super-junction structure of multilayer, the p/n type post district of two-layer super-junction structure is staggered about making, can further improve the contact area in p/n type post interval, be equivalent to the depth-to-width ratio in post district has been enlarged one times, the manufacture method of this structure can not brought pronounced side effects simultaneously, can guarantee that like this breakdown characteristics of device is higher than traditional super junction LDMOS.
And this multi-layer super-junction structure also has favorable expansibility, not only can be used for the SOI substrate, also can be used for other all kinds substrates such as body silicon or sapphire, in addition, this multi-layer super-junction structure not only can be bilayer, also can expand to three layers and even more multi-layered, with the contact area in further raising p/n type post interval, thus the breakdown characteristics of boost device.
Description of drawings
Fig. 1 is the schematic diagram of step among the embodiment (1);
Fig. 2 is the schematic diagram of step among the embodiment (2);
Fig. 3 is the generalized section of ground floor super-junction structure among the embodiment;
Fig. 4 is the generalized section of the multi-layer super-junction structure be made up of first and second layers of super-junction structure among the embodiment;
Fig. 5 is the schematic diagram of the LDMOS device of multi-layer super-junction structure among the embodiment.
Each description of reference numerals is as follows among Fig. 1:
1, source electrode
2, grid
3, polysilicon gate material layer
4, p type post district
5, n type post district
6, drain electrode
7, groove isolation construction
8, SOI oxygen buried layer
9, SOI bottom silicon
10, body contact zone
11, source region
12, tagma
13, gate oxidation material layer
14, ground floor super-junction structure
15, second layer super-junction structure
16, drain region
Embodiment
Further specify the present invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is not proportionally drawn.
As shown in Figure 5, a kind of LDMOS device with multi-layer super-junction structure, comprise substrate and be positioned at active area on the substrate, its active area comprises: grid region, the multi-layer super-junction structure in the source region 11 of both sides, grid region and drain region 16, in the tagma under the grid region 12, between tagma 12 and drain region 16; Described multi-layer super-junction structure comprises the two-layer at least super-junction structure (comprising ground floor super-junction structure 14 and second layer super-junction structure 15) that is arranged in order from the bottom to top; every layer of super-junction structure is made up of the n type post district 5 and the p type post district 4 of laterally alternately arranging, and can share puncture voltage.Wherein, described grid region comprises gate dielectric layer and the gate material layer that is positioned on the gate dielectric layer, for example, and gate oxidation material layer 13 and polysilicon gate material layer 3.
As preferred version of the present invention, in multi-layer super-junction structure, the n type post district of upper strata super-junction structure is corresponding with the p type post district and the n type post zone position of its lower floor's super-junction structure respectively with p type post district, the n type post district and the p type post district of levels super-junction structure are staggered, can further improve the contact area in n, p type post interval.In addition, this multi-layer super-junction structure not only can be bilayer, also can expand to three layers and even more multi-layered.N type post district and p type post sector width and the degree of depth equate that respectively its width injects window width for the minimum ion that process conditions can provide, and scope is 0.5um-1.5um, and its degree of depth is injected the degree of depth for the maximum ion that impurity can provide, and scope is 1um-2um.
As preferred version of the present invention, around its active area, be provided with groove isolation construction 7, itself and other device electricity is isolated.Described substrate preferably has the substrate of insulating buried layer, as SOI (Silicon On Insulator) substrate (comprising SOI oxygen buried layer 8 and SOI bottom silicon 9), also can be other various types of substrates such as body silicon substrate or Sapphire Substrate.When choosing (SOI) substrate with insulating buried layer, this device also comprises body contact zone 10, and this body contact zone 10 can be positioned at 11 sides, source region and contact with tagma 12, is used to draw the unnecessary electric charge that assemble in tagma 12, avoids floater effect.
On grid region, source region, drain region, be respectively equipped with grid 2, source electrode 1, drain electrode 6.Wherein, have the device of the substrate of insulating buried layer for employing, source electrode 1 is located on body contact zone 10 and source region 11 intersections.
With the SOI substrate is example, realizes that the technology of this device may further comprise the steps:
(1) as shown in Figure 1, adopt the SOI substrate, its top layer silicon is carried out ion inject, form the n type post district and the p type post district of alternately arranging, as the ground floor super-junction structure.Wherein, ion injects the post district degree of depth that forms and is SOI top layer silicon thickness, the minimum widith design that the post sector width can provide with process conditions, and p type post district forms by implanted dopant boron, and n type post district forms by implanted dopant phosphorus.The profile of ground floor super-junction structure as shown in Figure 3, and is identical with the super-junction structure of traditional LDMOS.
(2) as shown in Figure 2, be formed with epitaxial growth monocrystalline silicon on the SOI substrate of ground floor super-junction structure, the preparation epitaxial loayer.The thickness of epitaxial loayer is identical with the thickness of ground floor super-junction structure, also will be as the thickness of second layer super-junction structure.Then, utilize the process conditions identical to make second layer super-junction structure at epitaxial loayer with making the ground floor super-junction structure, and make the n type post district of second layer super-junction structure corresponding with the p type post district and the n type post zone position of its following ground floor super-junction structure respectively, thereby the n type post district of levels super-junction structure and p type post district are staggered with p type post district.
The profile of the multi-layer super-junction structure of forming by first and second layers of super-junction structure, as shown in Figure 4, as seen the staggered contact area that can further improve p/n type post interval in p/n type post district, be equivalent to the depth-to-width ratio in post district has been enlarged one times, it makes compatible mutually with traditional handicraft simultaneously, can not bring pronounced side effects, can guarantee that like this breakdown characteristics of device is higher than traditional super junction LDMOS.
In addition, can also pass through the method for repeating step (2), the 3rd layer of continued growth and even more multi-layered super-junction structure further improve the contact area in p/n type post interval.
(3) utilize shallow trench isolation from (STI) fabrication techniques groove isolation construction, the part silicon materials that will comprise multi-layer super-junction structure isolate, and these part silicon materials are used for the active area of fabricate devices.
(4) utilize thermal oxidation method to form one deck gate oxidation material on above-mentioned segregate part silicon materials surface.
(5) utilize repeatedly the ion injection mode that the part except that multi-layer super-junction structure in the described part silicon materials is mixed, form the p trap body area.
(6) deposit polysilicon, doping form the polysilicon gate material on the gate oxidation material, and produce the grid region by photoetching end near multi-layer super-junction structure on the p trap body area.The grid region is made of gate oxidation material layer and polysilicon gate material layer.
(7) in a side in described grid region, be infused in organizator contact zone and source region on the p trap body area by ion.
(8) at the opposite side in described grid region, be infused in by ion that the end away from the grid region forms the drain region on the multi-layer super-junction structure, thereby finish the making of active area, obtain the core texture of device.
Wherein, make p trap body area, grid region, source region, body contact zone and drain region and adopt conventional semiconductor technologies such as ion injection, etching, present embodiment only is a kind of preferred step method, and other variation also can be arranged when specifically making.Vertically arrange in the grid region and the drain region that make, and multi-layer super-junction structure is made up of the n type post district and the p type post district of laterally alternately arranging.
(9) adopt LTO (low temperature silicon dioxide) mode growthing silica, cover whole active area.
(10) on described silicon dioxide, etch window, depositing metal then, grid, source electrode, drain electrode are drawn in photoetching.Source electrode is located on body contact zone and the source region intersection.
(11) last deposit silicon nitride generates passivation layer.
The device that obtains at last as shown in Figure 5.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and do not repeat them here.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (10)
1. LDMOS device with multi-layer super-junction structure, comprise substrate and the active area that is positioned on the substrate, it is characterized in that described active area comprises: grid region, multi-layer super-junction structure in the source region of both sides, described grid region and drain region, in the tagma under the described grid region, between described tagma and described drain region; Described multi-layer super-junction structure comprises the two-layer at least super-junction structure that is arranged in order from the bottom to top, and every layer of super-junction structure is made up of the n type post district and the p type post district of laterally alternately arranging.
2. according to the described a kind of LDMOS device of claim 1 with multi-layer super-junction structure, it is characterized in that: in described multi-layer super-junction structure, the n type post district of upper strata super-junction structure is corresponding with the p type post district and the n type post zone position of its lower floor's super-junction structure respectively with p type post district, and the n type post district of levels super-junction structure and p type post district are staggered.
3. according to the described a kind of LDMOS device of claim 2, it is characterized in that with multi-layer super-junction structure: the width in n type post district and the degree of depth respectively with the width and the deep equality in p type post district.
4. according to the described a kind of LDMOS device with multi-layer super-junction structure of claim 3, it is characterized in that: the width in n type post district and p type post district is 0.5um-1.5um.
5. according to the described a kind of LDMOS device with multi-layer super-junction structure of claim 3, it is characterized in that: the degree of depth in n type post district and p type post district is 1um-2um.
6. according to the described a kind of LDMOS device of claim 1, it is characterized in that: around described active area, be provided with groove isolation construction with multi-layer super-junction structure.
7. according to the described a kind of LDMOS device with multi-layer super-junction structure of claim 1, it is characterized in that: described substrate is substrate, body silicon substrate or the Sapphire Substrate with insulating buried layer.
8. according to the described a kind of LDMOS device of claim 7 with multi-layer super-junction structure, it is characterized in that: described substrate is when having the substrate of insulating buried layer, described active area also comprises the body contact zone, and this body contact zone is positioned at side, described source region and contacts with described tagma.
9. according to the described a kind of LDMOS device with multi-layer super-junction structure of claim 1, it is characterized in that: described grid region comprises gate dielectric layer and the gate material layer that is positioned on the gate dielectric layer.
10. according to the described a kind of LDMOS device with multi-layer super-junction structure of claim 9, it is characterized in that: described gate material layer adopts polycrystalline silicon material.
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| CN 201010234287 CN101916780A (en) | 2010-07-22 | 2010-07-22 | LDMOS device with multilayer super-junction structure |
| PCT/CN2010/079831 WO2012009928A1 (en) | 2010-07-22 | 2010-12-15 | Ldmos device with multi-layer super-junction structure |
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Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102593007A (en) * | 2012-03-21 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Super junction device with multiple embedded P islands and N channels and preparation method thereof |
| CN104979382A (en) * | 2014-04-02 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| US20170054018A1 (en) * | 2014-05-04 | 2017-02-23 | Csmc Technologies Fab1 Co., Ltd. | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
| CN108767013A (en) * | 2018-06-05 | 2018-11-06 | 电子科技大学 | A kind of SJ-LDMOS devices with part buried layer |
| CN110534566A (en) * | 2019-09-05 | 2019-12-03 | 电子科技大学 | A kind of IGBT power device |
| CN113113495A (en) * | 2021-04-12 | 2021-07-13 | 东南大学 | Transverse double-diffusion metal oxide semiconductor device with staggered groove grid structure |
| CN113410299A (en) * | 2020-03-16 | 2021-09-17 | 电子科技大学 | High-voltage-resistance n-channel LDMOS device and preparation method thereof |
| CN114122113A (en) * | 2022-01-27 | 2022-03-01 | 江苏游隼微电子有限公司 | High-reliability MOSFET power semiconductor device structure |
| CN116525655A (en) * | 2023-06-30 | 2023-08-01 | 江苏应能微电子股份有限公司 | Three-dimensional super-junction LDMOS structure and manufacturing method thereof |
| CN117766588A (en) * | 2024-02-22 | 2024-03-26 | 南京邮电大学 | Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method |
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| CN102593007A (en) * | 2012-03-21 | 2012-07-18 | 中国科学院上海微系统与信息技术研究所 | Super junction device with multiple embedded P islands and N channels and preparation method thereof |
| CN104979382A (en) * | 2014-04-02 | 2015-10-14 | 世界先进积体电路股份有限公司 | Semiconductor device and manufacturing method thereof |
| US20170054018A1 (en) * | 2014-05-04 | 2017-02-23 | Csmc Technologies Fab1 Co., Ltd. | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
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| KR101929639B1 (en) * | 2014-05-04 | 2018-12-14 | 씨에스엠씨 테크놀로지스 에프에이비1 코., 엘티디. | Laterally diffused metal oxide semiconductor device and manufacturing method therefor |
| CN108767013A (en) * | 2018-06-05 | 2018-11-06 | 电子科技大学 | A kind of SJ-LDMOS devices with part buried layer |
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| CN113113495A (en) * | 2021-04-12 | 2021-07-13 | 东南大学 | Transverse double-diffusion metal oxide semiconductor device with staggered groove grid structure |
| CN114122113A (en) * | 2022-01-27 | 2022-03-01 | 江苏游隼微电子有限公司 | High-reliability MOSFET power semiconductor device structure |
| CN116525655A (en) * | 2023-06-30 | 2023-08-01 | 江苏应能微电子股份有限公司 | Three-dimensional super-junction LDMOS structure and manufacturing method thereof |
| CN117766588A (en) * | 2024-02-22 | 2024-03-26 | 南京邮电大学 | Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method |
| CN117766588B (en) * | 2024-02-22 | 2024-04-30 | 南京邮电大学 | Super-junction double SOI-LDMOS device with extended drain structure and manufacturing method |
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| WO2012009928A1 (en) | 2012-01-26 |
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