CN101916730B - Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer - Google Patents
Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 9
- 239000010703 silicon Substances 0.000 title claims abstract description 9
- 239000004065 semiconductor Substances 0.000 title abstract description 6
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 4
- 150000004706 metal oxides Chemical class 0.000 title abstract description 4
- 239000012212 insulator Substances 0.000 title abstract 2
- 239000012535 impurity Substances 0.000 claims abstract description 27
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000009826 distribution Methods 0.000 claims abstract description 17
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 4
- 239000011248 coating agent Substances 0.000 claims description 49
- 238000000576 coating method Methods 0.000 claims description 49
- 239000000463 material Substances 0.000 claims description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 10
- 229910052760 oxygen Inorganic materials 0.000 claims description 10
- 239000001301 oxygen Substances 0.000 claims description 10
- 239000003989 dielectric material Substances 0.000 claims description 8
- 238000002347 injection Methods 0.000 claims description 8
- 239000007924 injection Substances 0.000 claims description 8
- 238000002955 isolation Methods 0.000 claims description 8
- 230000003647 oxidation Effects 0.000 claims description 8
- 238000007254 oxidation reaction Methods 0.000 claims description 8
- 239000002210 silicon-based material Substances 0.000 claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 238000010276 construction Methods 0.000 claims description 5
- 235000012239 silicon dioxide Nutrition 0.000 claims description 5
- 238000001259 photo etching Methods 0.000 claims description 4
- 238000002513 implantation Methods 0.000 claims description 3
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000000694 effects Effects 0.000 abstract description 17
- 230000015556 catabolic process Effects 0.000 abstract description 5
- 230000005684 electric field Effects 0.000 abstract description 3
- 210000000746 body region Anatomy 0.000 abstract 3
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 6
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000009825 accumulation Methods 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 2
- 238000009828 non-uniform distribution Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009795 derivation Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
- H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/063—Reduced surface field [RESURF] pn-junction structures
- H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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Abstract
The invention discloses a method for manufacturing a silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with a linear buffer layer. The method comprises the following steps of: manufacturing a buffer layer doped layout by calculating a buffer layer impurity concentration so as to manufacture the buffer layer with impurities approximately linearly distributed in the transverse direction by using ion implantation, then extending single crystal silicon to a thickness required by a device on an SOI substrate with the buffer layer, forming a p well body region beside the buffer layer, manufacturing a gate region, a source region a and a body contact region on the p well body region, and manufacturing a drift region and a drain region on the buffer layer, wherein the drift region is positioned between the p well body region and the drain region. The manufacturing method compensates the residual charge of the longitudinal electric field by introducing the buffer layer with the impurity concentration approximately linearly distributed in the transverse direction below a super-junction so as to eliminate the influence of substrate aid depletion effect on the charge distribution of the drift region of the SOI super-junction LDMOS and improve the breakdown voltage of the device.
Description
Technical field
The present invention relates to a kind of lateral double diffusion metal oxide semiconductor (LDMOS; Lateral Double-diffused MOSFET) manufacture craft; Especially a kind of SOI super junction LDMOS manufacture method with linear buffer layer that solves substrate-assisted depletion effect belongs to technical field of manufacturing semiconductors.
Background technology
Lateral double diffusion metal oxide semiconductor (LDMOS, Lateral Double-diffused MOSFET) is the key technology of high voltage integrated circuit HVIC (High Voltage Integrated Circuit) and power integrated circuit PIC (Power Integrated Circuit).Be primarily characterized in that to add one section relatively long light dope drift region between channel region and the drain region, this drift region doping type is consistent with drain terminal, through adding the drift region, can play the effect of sharing puncture voltage.
So-called super junction LDMOS is a kind of modified model LDMOS, and promptly the low-doped N type drift region of traditional LDMOST is replaced by one group of n type post district that alternately arranges and p type post district.In theory; Because the charge compensation between the p/n post district; Super junction LDMOS can obtain very high puncture voltage, and highly doped N type post district then can obtain very low conducting resistance, and therefore ultra junction device can be obtained a good balance between puncture voltage and conducting resistance.But, owing to the existence of substrate-assisted depletion effect (substrate-assisteddepletion effects), reduced the puncture voltage of super junction LDMOS device.
So-called substrate-assisted depletion effect is meant horizontal ultra knot owing to receive the influence of longitudinal electric field, and the p/n post district of symmetry in the ultra knot can not be exhausted simultaneously fully, and its essence is that the charge balance between the p/n post district is broken.For the SOI substrate; Under OFF state; Because the back of the body grid effect of substrate; The electric charge of non-uniform Distribution is accumulated in the upper and lower interface place of oxygen buried layer and silicon under the effect of longitudinal electric field, strengthened the charge difference between the p/n post district, causes p/n post district under the puncture voltage that theory is calculated, to exhaust fully simultaneously.
Under the ideal situation; Even adopt accurate doping techniques; Make that total amount of electric charge is consistent in the p/n post district, still can't solve device after applying bias voltage, the SOI oxygen buried layer that is brought by substrate-assisted depletion effect is the problem of accumulation at the interface; This will bring new charge unbalance, and this electric charge is on the direction of oxygen buried layer interface and non-uniform Distribution.
Given this, the present invention proposes a kind of influence that substrate-assisted depletion effect distributes to SOI LDMOS drift region charge of eliminating, and improves the linear buffer layer manufacture craft of device electric breakdown strength.
Summary of the invention
The technical problem that the present invention will solve is to provide a kind of SOI super junction LDMOS manufacture method with linear buffer layer, can eliminate the influence that substrate-assisted depletion effect distributes to SOI LDMOS drift region charge, improves device electric breakdown strength.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme:
A kind of SOI super junction LDMOS manufacture method with linear buffer layer may further comprise the steps:
(A) use formula:
calculate required resilient coating impurity concentration;
ρ wherein
BLBe resilient coating impurity concentration, T
BLBe buffer layer thickness, V
dBe drain terminal bias voltage, L
dBe drift region length, ε
sBe the dielectric coefficient of silicon, ε
OxBe the dielectric coefficient of silicon dioxide, T
sBe the thickness of SOI, T
OxBe the oxygen buried layer thickness of SOI, W
pAnd W
nBe respectively the width in p, n type post district, q is an electronic charge;
(B) make the undoped buffer layer domain, make and offer N the window that is arranged in parallel on this undoped buffer layer domain, the distance of the center of each window and domain one lateral edges is L
i=i*L
d/ N, wherein i representes i window, window width is W
i=i*L
d/ N
2
(C) adopt the SOI substrate, the undoped buffer layer domain that utilizes step (B) to make, according to the required resilient coating impurity concentration that step (A) is calculated, the control implantation dosage carries out ion to the top layer silicon of SOI substrate and injects, and obtains the resilient coating of the vertical linear distribution of impurity;
(D) making epitaxial monocrystalline silicon to device desired thickness on the said SOI substrate that resilient coating arranged;
(E) utilize repeatedly ion injection method in the other p of formation of said resilient coating trap body area;
(F) end near said resilient coating is made the grid region on said p trap body area;
(G) utilize ion injection method on said p trap body area, to make source region and body contact zone in a side in said grid region;
(H) opposite side in said grid region utilizes ion injection method on said resilient coating, to make drift region and drain region, makes said drift region between said p trap body area and drain region.
Wherein, the resilient coating of step (C) making is a n type resilient coating.
As one of preferred version of the present invention; In step (D) afterwards; Utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise resilient coating are isolated out and are used for follow-up making p trap body area, grid region, source region, body contact zone, drift region and drain region.
As one of preferred version of the present invention, when step (H) was made the drift region, the mode that adopts repeatedly ion to inject formed the n type post district and the p type post district of laterally alternately arranging on resilient coating.Wherein, when repeatedly ion injects manufacturing n type post district and p type post district, make their CONCENTRATION DISTRIBUTION consistent.
As one of preferred version of the present invention; When step (F) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said resilient coating on said p trap body area then, make said grid region comprise gate dielectric material and grid material.Preferably, utilize thermal oxidation method to form said gate dielectric material; Said grid material is a polycrystalline silicon material.
Beneficial effect of the present invention is:
For SOI LDMOS device, after applying bias voltage, because substrate-assisted depletion effect is in SOI oxygen buried layer accumulation at the interface; Suppose that it is linear that surface potential distributes; And the drift region exhausts under puncture voltage fully, can put the linear apart from x of raceway groove with this through the charge density that the derivation of equation is buried the oxygen interface somewhere, i.e. Q (X) ∝ X; That is should locate far away more apart from raceway groove; Uneven charge number is big more, and its maximum occurs in the place near drain terminal, thereby punctures the most easily.
For solving residual charge density along this problem of linear distribution on the direction of oxygen buried layer interface; The present invention is through introduce the n type resilient coating that one deck impurity concentration is a linear distribution too below p/n post district; Offset this unnecessary electric charge, thereby solve pn post district's electronics and this problem of hole charge mismatch that substrate-assisted depletion effect brings.
Therefore; The present invention through calculating the residual charge corresponding buffered layer impurity concentration of linear distribution, only needs one deck photolithography plate on the basis of theory; Just can form ladder ground, impurity concentration resilient coating near linear distribution; Thereby offset the residual charge of oxygen buried layer linear distribution at the interface, and then eliminate the influence that substrate-assisted depletion effect distributes to SOI super junction LDMOS drift region charge, improve the puncture voltage of device.
Description of drawings
The SOI super junction LDMOS sketch map that Fig. 1 makes for embodiment with linear buffer layer;
Fig. 2 is a undoped buffer layer domain sketch map among the embodiment;
Fig. 3 prepares the sketch map of resilient coating for embodiment step (3).
Each description of reference numerals is following among Fig. 1:
1, source electrode
2, grid
3, polysilicon gate material layer
4, n type post district
5, p type post district
6, drain electrode
7, groove isolation construction
8, insulating buried layer
9, body contact zone
10, source region
11, tagma
12, gate oxidation material layer
13, drift region
14, resilient coating
15, drain region
Embodiment
Further specify the present invention below in conjunction with accompanying drawing, for the accompanying drawing that makes things convenient for that illustrates is not proportionally drawn.
As shown in Figure 1; SOI super junction LDMOS device is formed by the active area on the insulating buried layer 8 with the groove isolation construction 7 that active area surrounds usually, and its active area comprises: grid region (comprising polysilicon gate material layer 3 and gate oxidation material layer 12), body contact zone 9, source region 10, tagma 11 (its part under the grid region is as raceway groove), drift region 13 and drain region 15.Source region 10, drain region 15 lay respectively at the raceway groove two ends.Drift region 13 is located between drain region 15 and the raceway groove, and it is made up of n type post district of laterally alternately arranging 4 and p type post district 5, can share puncture voltage.Body contact zone 9 contacts with tagma 11, avoids floater effect.
Because substrate-assisted depletion effect, SOI super junction LDMOS device applied bias voltage after, the insulating buried layer 8 below drift region 13 is accumulation at the interface, and residual charge linear distribution in theory.In order to improve device electric breakdown strength; The present invention introduces the n type resilient coating 14 that one deck impurity concentration is a linear distribution below drift region 13; Thereby offset the residual charge of linear distribution, eliminate the influence that substrate-assisted depletion effect distributes to SOI super junction LDMOS drift region charge.
The technology that realizes this device may further comprise the steps:
(1) calculate required resilient coating impurity concentration:
ρ wherein
BLBe resilient coating impurity concentration, T
BLBe buffer layer thickness, V
dBe drain terminal bias voltage, L
dBe drift region length, ε
sBe the dielectric coefficient of silicon, ε
OxBe the dielectric coefficient of silicon dioxide, T
sBe the thickness of SOI, T
OxBe the thickness of SOI oxygen buried layer, W
pAnd W
nBe respectively the width in p, n type post district, q is an electronic charge.
(2) make the undoped buffer layer domain according to process conditions and required precision, the undoped buffer layer domain is resolved into N window, the distance of the center of each window and domain one lateral edges is L
i=i*L
d/ N, wherein i representes i window, window width is W
i=i*L
d/ N
2Fig. 2 is the undoped buffer layer domain of 10 windows.
(3) as shown in Figure 3; Adopt the SOI substrate; Its top layer silicon is carried out ion inject making resilient coating 14: utilize the undoped buffer layer domain of step (2) made, according to the required resilient coating impurity concentration that step (1) is calculated, the control implantation dosage carries out ion and injects; Obtain the resilient coating 14 of the vertical linear distribution of impurity, and this resilient coating 14 is a n type resilient coating.When using the undoped buffer layer domain; Its first window is near the position of raceway groove, and N window forms and a window corresponding N linear impurity range resilient coating 14 near the position in drain region 15; Because window width progressively increases; The width of impurity range also progressively increases, and is 0 thereby make resilient coating 14 near raceway groove place impurity concentration, and the highest near the impurity concentration at 15 places, drain region.
(4) epitaxial monocrystalline silicon to device desired thickness on the above-mentioned SOI substrate that is manufactured with resilient coating 14.Wherein the thickness of extension is about the required thickness in p or n type post district 4,5 on the resilient coating 14.
(5) utilize shallow trench isolation to leave (STI) fabrication techniques groove isolation construction 7, the part top layer silicon material that will comprise resilient coating 14 isolates out, and these part silicon materials are used for the active area of fabricate devices.
(6) form one deck gate oxidation material at above-mentioned segregate part silicon materials surface by utilizing thermal oxidation method.
(7) utilize repeatedly the ion injection mode that the part except that resilient coating 14 in the said part silicon materials is mixed, form p trap body area 11.P trap body area 11 is near an end of resilient coating 14 impurity concentrations little (the impurity range width is minimum).
(8) deposit polysilicon, doping form the polysilicon gate material on the gate oxidation material, and produce the grid region through photoetching end near resilient coating 14 on p trap body area 11.The grid region is made up of gate oxidation material layer 12 and polysilicon gate material layer 3.
(9) make drift region 13: the mode that adopts repeatedly ion to inject, on resilient coating 14, form the n type post district 4 and p type post district 5 of laterally alternately arranging successively, make n type post district 4 consistent with the CONCENTRATION DISTRIBUTION in p type post district 5.Wherein, can be based on process conditions and electricity index, Theoretical Calculation goes out under the required width in n type post district 4 and p type post district 5 and the degree of depth and the maximum breakdown voltage to exhaust the concentration of electric charges of situation correspondence fully, thereby produces satisfactory device.
(10) in a side in said grid region, be infused in organizator contact zone 9 and source region 10 on the p trap body area 11 through ion.
(11) at the opposite side in said grid region, be infused in through ion that the end away from the grid region forms drain region 15 on the drift region 13, thereby accomplish the making of active area, obtain the core texture of device.
Wherein, make p trap body area 11, grid region, source region 10, body contact zone 9, drift region 13 and drain region 15 and adopt conventional semiconductor technologies such as ion injection, etching, present embodiment only is a kind of preferred step method, and other variation also can be arranged when specifically making.Vertically arrange in the grid region and the drain region 15 that make, is parallel to vertical linear distribution impurity of resilient coating 14; And drift region 13 is made up of n type post district of laterally alternately arranging 4 and p type post district 5, and is vertical with vertical linear distribution impurity of its below resilient coating 14.
(12) adopt LTO (low temperature silicon dioxide) mode growthing silica, cover whole active area.
(13) on said silicon dioxide, etch window, depositing metal then, grid 2, source electrode 1, drain electrode 6 are drawn in photoetching.
(14) last deposit silicon nitride generates passivation layer.
The device that obtains at last is as shown in Figure 1.
The other technologies that relate among the present invention belong to the category that those skilled in the art are familiar with, and repeat no more at this.The foregoing description is the unrestricted technical scheme of the present invention in order to explanation only.Any technical scheme that does not break away from spirit and scope of the invention all should be encompassed in the middle of the patent claim of the present invention.
Claims (8)
1. the SOI super junction LDMOS manufacture method with linear buffer layer is characterized in that, may further comprise the steps:
(A) use formula:
Calculate required resilient coating impurity concentration; ρ wherein
BLBe resilient coating impurity concentration, T
BLBe buffer layer thickness, V
dBe drain terminal bias voltage, L
dBe drift region length, ε
sBe the dielectric coefficient of silicon, ε
OxBe the dielectric coefficient of silicon dioxide, T
sBe the thickness of SOI, T
OxBe the oxygen buried layer thickness of SOI, W
pAnd W
nBe respectively the width in p, n type post district, q is an electronic charge;
(B) make the undoped buffer layer domain, make and offer N the window that is arranged in parallel on this undoped buffer layer domain, the distance of the center of each window and domain one lateral edges is L
i=i*L
d/ N, wherein i representes i window, window width is Wi=i*L
d/ N
2
(C) adopt the SOI substrate, the undoped buffer layer domain that utilizes step (B) to make, according to the required resilient coating impurity concentration that step (A) is calculated, the control implantation dosage carries out ion to the top layer silicon of SOI substrate and injects, and obtains the resilient coating of the vertical linear distribution of impurity;
(D) be manufactured with epitaxial monocrystalline silicon to device desired thickness on the SOI substrate of said resilient coating;
(E) utilize repeatedly ion injection method in the other p of formation of said resilient coating trap body area;
(F) end near said resilient coating is made the grid region on said p trap body area;
(G) utilize ion injection method on said p trap body area, to make source region and body contact zone in a side in said grid region;
(H) opposite side in said grid region utilizes ion injection method on said resilient coating, to make drift region and drain region, makes said drift region between said p trap body area and drain region.
2. according to the said a kind of SOI super junction LDMOS manufacture method with linear buffer layer of claim 1, it is characterized in that: the resilient coating that step (C) is made is a n type resilient coating.
3. according to the said a kind of SOI super junction LDMOS manufacture method of claim 1 with linear buffer layer; It is characterized in that: afterwards in step (D); Utilize shallow trench isolation to leave the fabrication techniques groove isolation construction, the part silicon materials that will comprise resilient coating are isolated out and are used for follow-up making p trap body area, grid region, source region, body contact zone, drift region and drain region.
4. according to the said a kind of SOI super junction LDMOS manufacture method of claim 1 with linear buffer layer; It is characterized in that: when step (H) is made the drift region; The mode that adopts repeatedly ion to inject forms the n type post district and the p type post district of laterally alternately arranging on resilient coating.
5. according to the said a kind of SOI super junction LDMOS manufacture method of claim 4, it is characterized in that: when manufacturing n type post district and p type post district, make their CONCENTRATION DISTRIBUTION consistent with linear buffer layer.
6. according to the said a kind of SOI super junction LDMOS manufacture method of claim 1 with linear buffer layer; It is characterized in that: when step (F) is made the grid region; Prepare one deck gate dielectric material earlier; On said gate dielectric material, prepare grid material again, produce the grid region through photoetching end near said resilient coating on said p trap body area then, make said grid region comprise gate dielectric material and grid material.
7. according to the said a kind of SOI super junction LDMOS manufacture method of claim 6, it is characterized in that: utilize thermal oxidation method to form said gate dielectric material with linear buffer layer.
8. according to the said a kind of SOI super junction LDMOS manufacture method with linear buffer layer of claim 6, it is characterized in that: said grid material is a polycrystalline silicon material.
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| CN2010102342946A CN101916730B (en) | 2010-07-22 | 2010-07-22 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
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| CN2010102342946A CN101916730B (en) | 2010-07-22 | 2010-07-22 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
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| CN102969244B (en) * | 2012-12-11 | 2015-03-25 | 中国科学院上海微系统与信息技术研究所 | SJ-insulated gate bipolar transistor (SJ-IGBT) device structure and manufacturing method thereof |
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| CN113451387B (en) * | 2020-03-24 | 2022-12-23 | 清华大学 | Buffer region variable doping structure for overvoltage breakdown function and semiconductor device |
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