CN101064307A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit Download PDFInfo
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- CN101064307A CN101064307A CNA2007101017033A CN200710101703A CN101064307A CN 101064307 A CN101064307 A CN 101064307A CN A2007101017033 A CNA2007101017033 A CN A2007101017033A CN 200710101703 A CN200710101703 A CN 200710101703A CN 101064307 A CN101064307 A CN 101064307A
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823493—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
Abstract
A semiconductor integrated circuit including digital circuits and analog circuits integrated over a single substrate includes the substrate including portions where the digital circuits and the analog circuits are to be formed, and a plurality of deep-wells formed to a certain thickness inside the substrate to surround portions where devices of the digital circuits and devices of the analog circuits are to be formed to reduce interference between the devices of the analog circuits and the digital circuits.
Description
Cross reference
The present invention requires respectively on April 26th, 2006 and the korean patent application No.10-2006-0037865 of submission on March 16th, 2007 and the priority of No.10-2007-0026209, and its full content is incorporated herein by reference.
Technical field
The present invention relates to a kind of integrated circuit and manufacture method thereof of semiconductor device, and more specifically relate to and a kind ofly can support the integrated circuit of digital circuit, analog circuit and radio frequency (RF) circuit by using single microchip.
Background technology
Comprise that the modular bipolar complementary metal oxide semiconductor-sheet upper module formula system (MSOC) of discrete metal oxide semiconductor single integrated circuit has been used for the integrated circuit of smart card, to implement the telecommunication system of high-frequency and high internal pressure, it comprises the ever-increasing automobile power integrated circuit of demand and direct current/direct current conversion.Single integrated circuit is supported digital circuit, analog circuit and radio frequency (RF) circuit simultaneously.Therefore, digital circuit, analog circuit and RF circuit are integrated on the single integrated circuit.Via the use of single integrated circuit, can improve the quality and the quantity of the portable RF device that is used for wireless and optical communication applications.
Yet all kinds circuit integrated causes various limitations.One of limitation be since all kinds circuit unique nature caused crosstalks.Arranging on the single integrated circuit that the interaction between the circuit may be by the substrate of single integrated circuit under the situation of various circuit.The use of single integrated circuit is very unable to crosstalking in digital circuit, analog circuit and the RF circuit.
Analog circuit is to very responsive by the electrical noise that other circuit or devices produced.Digital circuit is because its digital nature and to compare electrical noise more insensitive with analog circuit.Yet digital circuit is owing to this digital nature produces a large amount of current noises.Therefore, under situation about analog circuit and digital circuit being integrated in jointly on the single integrated circuit owing to can influence analog circuit by the noise that digital circuit produced, thus analog circuit should with isolate by the electrical noise that analog circuit produced.
Summary of the invention
Embodiments of the invention at provide a kind of semiconductor integrated circuit, wherein for the single integrated circuit of supporting digital circuit, analog circuit and radio frequency (RF) circuit simultaneously, described semiconductor integrated circuit can stably be isolated analog circuit and electrical noise.
Embodiments of the invention at provide a kind of semiconductor integrated circuit, wherein semiconductor integrated circuit can reduce the size of single integrated circuit to support digital circuit, analog circuit and RF circuit simultaneously.
Embodiments of the invention at provide a kind of semiconductor integrated circuit, wherein with regard to the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, semiconductor integrated circuit can stably be isolated the device that enables with the high pressure greater than about 30V level, for example, diffused metal oxide emiconductor (DMOS) device.
Embodiments of the invention at provide a kind of semiconductor integrated circuit, wherein with regard to the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, semiconductor integrated circuit minimizes manufacturing cost.
According to an aspect of the present invention, provide a kind of digital circuit that is integrated on the single substrate and semiconductor integrated circuit of analog circuit of comprising, described semiconductor integrated circuit comprises: substrate, and it comprises the part that wherein will form digital circuit and analog circuit; And a plurality of deep traps, it is formed up to specific thicknesses in the substrate with the part around the device of device that wherein will form digital circuit and analog circuit, to reduce crosstalking between the device of the device of analog circuit and digital circuit.
Description of drawings
Fig. 1 explanation is according to the semiconductor integrated circuit of one embodiment of the invention.
Fig. 2 A to Fig. 2 F explanation is used to make the method for semiconductor integrated circuit shown in Figure 1.
Embodiment
Hereinafter, with the detailed description that provides with reference to the accompanying drawings some embodiment of the present invention.At this, can amplify with clear presentation layer and zone layer and regional thickness in the accompanying drawings.In addition, when layer was described to be formed on other layers or the substrate, layer was formed directly on other layers or the substrate, or the 3rd layer can be inserted between it.In addition, even the identical or similar composed component of identical or similar reference number indication in different figure.
In more detail, for the purpose of explaining, in this embodiment illustrated of the present invention comprise some devices of digital circuit, analog circuit and radio frequency (RF) circuit.For example, the device of analog circuit comprises heterojunction bipolar transistor (HBT), bipolar junction transistor (BJT) and complementary metal oxide semiconductors (CMOS) (CMOS) device.The device of digital circuit comprises lateral double diffusion metal oxide semiconductor (LDMOS) device.The device of RF circuit comprises the RF cmos device.
Fig. 1 explanation is according to the semiconductor integrated circuit of one embodiment of the invention.Described semiconductor integrated circuit support is arranged at analog circuit device, radio frequency (RF) circuit devcie and the digital circuit device on the single substrate 100.The number of the device of each circuit, structure and be arranged among this embodiment of the present invention to nonrestrictive.
Semiconductor integrated circuit comprises a plurality of deep trap 104A that are formed up to the certain depth in the substrate 100.Deep trap 104A is around the zone that wherein will form analog circuit device, RF circuit devcie and digital circuit device.
Owing to mainly produce from the electrical noise that semiconductor integrated circuit produced, so deep trap 104A is formed at the zone that wherein forms the digital circuit device in digital circuit.Therefore, aspect manufacturing cost, only form around the deep trap 104A in the zone that wherein will form the digital circuit device than formation around the deep trap 104 in two zones that wherein will form analog circuit device and RF circuit devcie to more favourable.Yet, as shown in this embodiment of the present invention, if the zone that wherein will form the digital circuit device is greater than the zone that wherein will form analog circuit device and RF circuit devcie, then deep trap 104A can be formed at the zone that wherein will form analog circuit device and RF circuit devcie.
With regard to charged side, various circuit are integrated on the single substrate of specific conductivity type of semiconductor integrated circuit.Single substrate serves as the resistance that all types of circuit devcies are coupled.Therefore, being arranged at deep trap 104A on various types of circuit devcie strategies goes up so that the device of circuit is isolated from each other.As a result, the device of various circuit can be integrated on the single substrate.
As mentioned above, deep trap 104A prevents crosstalking between analog circuit and digital circuit.Deep trap 104A can form via the ion implantation technology that is considered to relative simple process.In addition, silicon-on-insulator (SOI) substrate that wherein forms buried oxide (BOX) layer can replace using deep trap 104A and be used to prevent crosstalking between analog circuit and digital circuit.Yet the use of SOI substrate influences manufacturing cost.Therefore, use cheap structure base board and form deep trap 104A via ion implantation technology.
For example, can change deep trap 104A according to each conduction type of substrate 100.Under the situation of using P type substrate, deep trap 104A is with N type doping impurity; And under the situation of using N type substrate, deep trap 104A mixes with p type impurity.
Semiconductor integrated circuit comprises that further shallow trench isolation is from (STI) type device isolation structure 101, middle trench isolations (MTI) type device isolation structure 102 and deep trench isolation (DTI) type device isolation structure 103 dynamic range with the device of implementing various circuit, for example, voltage range.
STI type device isolation structure 101 is formed in the groove with the degree of depth less than about 1 μ m from end face, is used for carrying out electricity and isolates between the low-voltage device that can enable less than the voltage of about 10V.For example, low-voltage device comprises that bipolar junction transistor (BJT), complementary metal oxide semiconductors (CMOS) (CMOS) device, RF-CMOS device and shallow trench isolation are from lateral double diffusion metal oxide semiconductor (ST-LDMOS) device.
MTI type device isolation structure 102 is formed in the groove to the degree of depth of about 3 mu m ranges with about certainly 1 μ m from the end face of substrate 100, is used in the middle of can the voltage device that the voltage to about 30V scope enables from about 10V or carries out the electricity isolation between low-voltage device and middle voltage device.For example, channel lateral diffused metal oxide emiconductor (MT-LDMOS) device during middle voltage device comprises.
DTI type device isolation structure 103 is formed in the groove with the degree of depth greater than about 3 μ m from the end face of substrate 100, is used in the middle of the high tension apparatus that can enable greater than the voltage of about 30V, is carrying out the electricity isolation between high tension apparatus and the low-voltage device or between high tension apparatus and voltage device.For example, high tension apparatus comprise deep trench isolation Laterally Diffused Metal Oxide Semiconductor (DTI-LDMOS) device that enables to the voltage of about 50V scope with about certainly 30V, with about certainly 50V extremely high pressure trap Laterally Diffused Metal Oxide Semiconductor (HV-LDMOS) device that enables of the voltage of about hundreds of V scope and the heterojunction bipolar transistor (HBT) that is used for high pressure.Concrete, groove has the degree of depth to about 50 mu m ranges from about 3 μ m.For example, groove has the degree of depth to about 10 mu m ranges from about 3 μ m.
Semiconductor integrated circuit comprises that the trap (not shown) that is used for high pressure is to be implemented in the middle of the digital circuit device HV-LDMOS device that enables to the voltage of about hundreds of V scope with about certainly 50V.In order to be formed for the trap of high pressure, replace forming epitaxial loayer at the part place of the substrate 100 that will form the HV-LDMOS device, inject (MI) technology but carry out medium, and carry out injection process subsequently to be formed for the trap of high pressure.
Inject (MI) technology for medium, the part of the degree of depth to about 3 mu m ranges is set at that ion injects target so that impurity is injected into the part corresponding to end face degree of depth to about 3 mu m ranges from about 1 μ m of distance substrate 100 from about 1 μ m by will be corresponding to the end face of distance substrate 100, and impurity is flow in the substrate 100.Injection process control temperature and process cycle have required ion to inject the degree of depth and CONCENTRATION DISTRIBUTION so that be injected into the measurer of the impurity of certain depth.
To describe in detail among Fig. 1 with reference to figure 2A to Fig. 2 F and show but unaccounted device.Fig. 2 A to Fig. 2 F explanation is used for the method for the semiconductor integrated circuit shown in the shop drawings 1.
As shown in Fig. 2 A,, therefore form the trap that is used for high pressure (not shown) with maximum heat budget because the HV-LDMOS device needs maximum depletion region.Be formed for the trap of high pressure via medium injection technology and injection process.More contents about the formation of the trap that is used for high pressure are that N type or p type impurity are injected in the substrate 100 to certain depth.Subsequently, to the temperature of about 1,200 ℃ of scope, carried out injection process about 2 hours to about 15 hours, to be formed for the trap of high pressure to the degree of depth of about tens mu m ranges at oneself several approximately μ m of end face of distance substrate 100 at about certainly 1,000 ℃.The degree of depth of trap that is used for high pressure is identical with the degree of depth of the epitaxial loayer of typical high tension apparatus.The trap that is used for DT-LDMOS can use the trap of the high pressure that is used for HV-LDMOS usually.
STI, MTI and DTI type device isolation structure 101,102 and 103 are formed in the substrate 100 and are used for device isolation.STI, MTI and DTI type device isolation structure 101,102 and 103 form with different structure.STI type device isolation structure 101, MTI type device isolation structure 102 and DTI type device isolation structure 103 have different depth, to obtain to be implemented on the dynamic range of the device on the semiconductor integrated circuit as much as possible.
Can form in STI, MTI and DTI type device isolation structure 101,102 and 103 each via two kinds of methods.First method is for using the fill method of insulating barrier.According to first method, substrate 100 is etched to certain depth to form groove.Subsequently, by insulating barrier, for example, has high-density plasma (HDP) oxide skin(coating) of good filling property, filling groove.Carry out chemico-mechanical polishing (CMP) technology with planarization HDP oxide skin(coating).
Second method is for using the ion injection method of oxonium ion.According to second method, the oxonium ion that will have insulating property (properties) directly is injected into substrate 100.In order to form STI, MTI and DTI structure via second method, do not use typical ion implantation technology and be to use stack injection technology (stack implantation process).
Carry out the stack injection technology, change the ion implantation energy level during whole processing step.Oxonium ion is injected into uses the deepest part that macroion injects energy level.Subsequently, the ion implantation energy level reduces gradually to form STI, MTI and DTI type device isolation structure.
For example, hereinafter explanation is used for by using first method to form the method for STI type device isolation structure 101 with sti structure.The buffer oxide layer and the pad nitride layer that serve as hard mask are formed on the substrate 100.Subsequently, carry out photoetching process to form etching mask thereon.Use etching mask to carry out the part of etch process with etching pad nitride layer, buffer oxide layer and substrate 100.As a result, form the groove have at least less than the little thickness of about 1 μ m.On the madial wall of groove, carry out oxidation technology to form the wall oxide skin(coating).Form the HDP oxide skin(coating) with filling groove, carry out chemico-mechanical polishing (CMP) technology subsequently with planarization HDP oxide skin(coating).Remove pad nitride layer and buffer oxide layer, obtain STI type device isolation structure 101 by this.
Can use the same procedure that is used to form STI type device isolation structure 101 to form MTI type device isolation structure 102 and DTI type device isolation structure 103.Yet MTI type device isolation structure 102 is formed up to from about 1 μ m to the thickness of about 3 mu m ranges, and the thickness that is formed up to greater than about 3 μ m of DTI type device isolation structure 103.
As shown in Fig. 2 B, form deep trap 104A so that around wherein will forming the part of analog circuit or wherein will form the part of digital circuit, to reduce crosstalking between the device of the device of analog circuit and digital circuit.For example, deep trap 104A in P type substrate 100 with N type doping impurity.The part that therein formation is comprised the analog circuit device of cmos device and RF-CMOS device applies macroion and injects energy level to form deep trap 104A.When forming deep trap 104A, collector electrode 104B is formed at part and another collector electrode 104C that wherein will form HBT and is formed at the part that wherein forms BJT.Collector electrode 104B and 104C have concentration and the thickness identical with deep trap 104A.
As shown in Fig. 2 C, a plurality of trap 105A are formed at the part of the device (for example, cmos device, RF-CMOS device, ST-LDMOS device and MT-LDMOS device) that wherein will form except that HV-LDMOS device and DT-LDMOS device.Trap 105A has the concentration less than deep trap 104A.Although for the purpose of explaining, do not show that trap 105A also is formed at the part that wherein will form ST-LDMOS device and MT-LDMOS device.
As shown in Fig. 2 D, when forming trap 105A, base stage 105B is formed at the part that wherein will form BJT.In order to increase the gain of BJT, preferably reduce the width of base stage 105B.Therefore, carry out independent photoetching process and independent ion implantation technology, with by apply than applied and form the low ion implantation energy level of deep trap 104A and form collector electrode 104B.Therefore, collector electrode 104B is formed up to the thickness less than deep trap 104A, and wherein deep trap 104A forms end face from substrate 100 around the adjacent devices in the device of analogue device.
A plurality of gate electrodes 108 are formed on the substrate 100.Each gate electrode 108 is through piled grids insulating barrier 106 and grid conducting layer 107 and form.Gate insulator 106 can be oxide skin(coating) (for example, silica (SiO
2) layer) and one of comprise in the stacked structure of oxide skin(coating) and nitride layer.Use selected a kind of grid conducting layer 107 that forms among the group that free polysilicon layer, transition metal, rare earth metal, alloy-layer, metal nitride layer, metal silicide layer and combination thereof form.As shown in Fig. 2 D, the gate electrode 108 of LDMOS device forms with vertical stratification; Yet the gate electrode 108 of LDMOS device can form by sunk structure.
As shown in Fig. 2 E, carry out ion implantation technology to form light dope interface (not shown), reach the little thickness in the substrate 100 of the both sides that are exposed to each gate electrode 108.A plurality of grid spacers 109 are formed on the sidewall of gate electrode 108.Grid spacer 109 comprises among the group that free oxidation thing layer, nitride layer and combination thereof form selected a kind of.
A plurality of high doped interface 110A is formed in the substrate 100 of the both sides that are exposed to sept 109, reaches the thickness greater than light dope interface (not shown).As a result, acquisition comprises the multiple source of light dope drain electrode (LDD) structure of light dope interface and high doped interface 110A.
When forming high doped interface 110A, emitter 110B is formed at the part that wherein will form BJT.A plurality of pick-up area (pick up region) 110C is formed at the part except that the part that wherein will form the BJT device, so that a biasing (bias) is supplied to each trap 105A.
As shown in Fig. 2 F, base stage 111 and emitter 112 are formed on the substrate 100 that wherein will form the HBT device.Base stage 111 comprises SiGe (SiGe).Emitter 112 comprises polysilicon layer.
Although not shown, RF passive device and transformer apparatus can be formed at the part that wherein will form the RFCMOS device.The RF passive device comprises among the group that free metal-insulator-metal (MIM) capacitor, resistor and inductor form selected a kind of.In addition, metal interconnecting wires can be formed so that the device in the integrated circuit is connected to each other.Inductor comprises aluminium or copper.
According to this embodiment of the invention, can obtain following effect.At first, for the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, deep trap with around wherein will form the part of analog circuit device or wherein will form the digital circuit device part mode and form.Therefore, analog circuit can stably be kept apart with electrical noise.
Secondly, for the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, form STI type device isolation structure, MTI type device isolation structure and DTI type device isolation structure, rather than form the typical device isolation structure via local oxidation of silicon (LOCOS) technology.Therefore, compare, can reduce the size of single integrated circuit with the size of typical integrated circuit.
The 3rd, the device that for the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, because the formation of STI, MTI and DTI device isolation structure, can stably isolate and have great dynamic range (that is, big voltage range).
The 4th, for the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, owing to come isolating device by forming STI, MTI and DTI type device isolation structure, therefore may reduce the length in interface, described interface forms with the big relatively length in the interface (source area and drain region) of LDD structure, and wherein LDD symmetrical configuration ground forms to isolate typical device.As a result, can reduce the overall dimensions of semiconductor integrated circuit.
At last, for the single integrated circuit of supporting digital circuit, analog circuit and RF circuit simultaneously, be formed for the trap of high pressure, rather than form epitaxial loayer via ion implantation technology and injection process.The trap that is used for high pressure serves as and the epitaxial loayer identical functions.As a result, and form typical integrated circuit and compare, can reduce manufacturing cost by forming epitaxial loayer.
Though described the present invention with reference to specific embodiment, it will be apparent to those skilled in the art that under situation about not deviating from as subsequently spirit of the present invention that claims limited and scope, can carry out various changes and modification.
[main element symbol description]
100 substrates
101 shallow trench isolations are from (STI) type device isolation structure
Trench isolations in 102 (MTI) type device isolation structure
103 deep trench isolation (DTI) type device isolation structure
104 deep traps
106 gate insulators
107 grid conducting layers
108 gate electrodes
109 grid spacers
111 base stages
112 emitters
The 104A deep trap
The 104B collector electrode
The 104C collector electrode
The 105A trap
The 105B base stage
110A high doped interface
The 110B emitter
The 110C picking region
The BJT bipolar junction transistor
The CMOS complementary metal oxide semiconductors (CMOS)
DT-LDMOS deep trench isolation lateral double diffusion metal oxide semiconductor
The HBT heterojunction bipolar transistor
HV-LDMOS high pressure trap Laterally Diffused Metal Oxide Semiconductor
Trench isolations Laterally Diffused Metal Oxide Semiconductor among the MT-LDMOS
RF-LDMOS radio frequency-lateral double diffusion metal oxide semiconductor
The ST-LDMOS shallow trench isolation is from lateral double diffusion metal oxide semiconductor
Claims (43)
1. semiconductor integrated circuit, it comprises digital circuit and the analog circuit that is integrated on the single substrate, described semiconductor integrated circuit comprises:
Described substrate, it comprises the part that wherein will form described digital circuit and described analog circuit; And
A plurality of deep traps, it is formed up to a specific thicknesses in the described substrate with the part around the device of device that wherein forms described digital circuit and described analog circuit, to reduce crosstalking between the described device of the described device of described analog circuit and described digital circuit.
2. semiconductor integrated circuit as claimed in claim 1, it further comprises the device of radio frequency (RF) circuit that is formed on the described substrate.
3. semiconductor integrated circuit as claimed in claim 2, the described device of wherein said RF circuit by described deep trap around.
4. semiconductor integrated circuit as claimed in claim 3, wherein said deep trap one of comprise in N type trap and the P type trap.
5. semiconductor integrated circuit as claimed in claim 1, the described device of wherein said analog circuit comprises a plurality of devices with Different Dynamic scope.
6. semiconductor integrated circuit as claimed in claim 1, the described device of wherein said digital circuit comprises a plurality of devices with Different Dynamic scope.
7. semiconductor integrated circuit as claimed in claim 5, it further comprises a plurality of device isolation structures, described a plurality of device isolation structures are formed up to different-thickness has described Different Dynamic scope with isolation described device respectively from the end face of described substrate.
8. semiconductor integrated circuit as claimed in claim 6, it further comprises a plurality of device isolation structures, described a plurality of device isolation structures are formed up to different-thickness has described Different Dynamic scope with isolation described device respectively from the end face of described substrate.
9. semiconductor integrated circuit as claimed in claim 7, the described device that wherein has described Different Dynamic scope comprises:
First device, it has first dynamic range;
Second device, it has second dynamic range greater than described first dynamic range; And
The 3rd device, it has the 3rd dynamic range greater than described second dynamic range.
10. semiconductor integrated circuit as claimed in claim 8, the described device that wherein has described Different Dynamic scope comprises:
First device, it has first dynamic range;
Second device, it has second dynamic range greater than described first dynamic range; And
The 3rd device, it has the 3rd dynamic range greater than described second dynamic range.
11. semiconductor integrated circuit as claimed in claim 9, wherein said first dynamic range at about certainly 1V to the scope of about 10V.
12. as the semiconductor integrated circuit of claim 10, wherein said first dynamic range at about certainly 1V to the scope of about 10V.
13. semiconductor integrated circuit as claimed in claim 9, wherein said second dynamic range at about certainly 10V to the scope of about 30V.
14. as the semiconductor integrated circuit of claim 10, wherein said second dynamic range at about certainly 10V to the scope of about 30V.
15. semiconductor integrated circuit as claimed in claim 9, wherein said the 3rd dynamic range at about certainly 30V to the scope of about 50V.
16. as the semiconductor integrated circuit of claim 10, wherein said the 3rd dynamic range at about certainly 30V to the scope of about 50V.
17. semiconductor integrated circuit as claimed in claim 9, the described device that wherein has described Different Dynamic scope further comprises four device, and described four device has the 4th dynamic range greater than described the 3rd dynamic range.
18. as the semiconductor integrated circuit of claim 10, the described device that wherein has described Different Dynamic scope further comprises four device, described four device has the 4th dynamic range greater than described the 3rd dynamic range.
19. as the semiconductor integrated circuit of claim 17, wherein said the 4th dynamic range at about certainly 50V to the scope of about 900V.
20. as the semiconductor integrated circuit of claim 18, wherein said the 4th dynamic range at about certainly 50V to the scope of about 900V.
21. semiconductor integrated circuit as claimed in claim 9, the device isolation structure of isolating described first device in the wherein said device isolation structure are formed up to the thickness to about 1 mu m range at about certainly 0.1 μ m.
22. as the semiconductor integrated circuit of claim 10, the device isolation structure of isolating described first device in the wherein said device isolation structure is formed up to the thickness to about 1 mu m range at about certainly 0.1 μ m.
23. semiconductor integrated circuit as claimed in claim 9, the device isolation structure of isolating described second device in the wherein said device isolation structure are formed up to the thickness to about 3 mu m ranges at about certainly 1 μ m.
24. as the semiconductor integrated circuit of claim 10, the device isolation structure of isolating described second device in the wherein said device isolation structure is formed up to the thickness to about 3 mu m ranges at about certainly 1 μ m.
25. semiconductor integrated circuit as claimed in claim 9, the device isolation structure of isolating described second device in the wherein said device isolation structure are formed up to the thickness to about 3 mu m ranges at about certainly 1 μ m.
26. as the semiconductor integrated circuit of claim 10, the device isolation structure of isolating described second device in the wherein said device isolation structure is formed up to the thickness to about 3 mu m ranges at about certainly 1 μ m.
27. semiconductor integrated circuit as claimed in claim 9, wherein said device isolation structure forms by an insulating barrier being filled in the groove in the described substrate.
28. as the semiconductor integrated circuit of claim 10, wherein said device isolation structure forms by an insulating barrier being filled in the groove in the described substrate.
29. semiconductor integrated circuit as claimed in claim 9, wherein said device isolation structure is formed in the described substrate by the stack injection technology of using oxonium ion.
30. as the semiconductor integrated circuit of claim 10, wherein said device isolation structure is formed in the described substrate via the stack injection technology of using oxonium ion.
31. semiconductor integrated circuit as claimed in claim 1, the described device of wherein said digital circuit comprise that shallow trench isolation is from lateral double diffusion metal oxide semiconductor (ST-LDMOS), middle trench isolations lateral double diffusion metal oxide semiconductor (MT-LDMOS), deep trench isolation lateral double diffusion metal oxide semiconductor (DT-LDMOS) and high pressure trap Laterally Diffused Metal Oxide Semiconductor (HV-LDMOS).
32. as the semiconductor integrated circuit of claim 31, wherein said HV-LDMOS device by the trap that is used for high pressure around.
33. as the semiconductor integrated circuit of claim 32, the described trap that wherein is used for described high pressure comprises one of N type trap and P type trap.
34. as the semiconductor integrated circuit of claim 32, the described trap that wherein is used for described high pressure is by impurity is injected into a specific thicknesses and forms by described implanted dopant is carried out injection process from the end face of described substrate.
35. as the semiconductor integrated circuit of claim 34, wherein said impurity is injected into the thickness to about 3 mu m ranges at about certainly 1 μ m from the described end face of described substrate.
36. as the semiconductor integrated circuit of claim 34, wherein said injection process is in the period of carrying out under about certainly 1,000 ℃ of temperature to about 1,200 ℃ of scope in about certainly 2 hours to about 15 hours scopes.
37. semiconductor integrated circuit as claimed in claim 1, the described device of wherein said analog circuit comprise bipolar junction transistor (BJT), complementary metal oxide semiconductors (CMOS) (CMOS) device and heterojunction bipolar transistor (HBT).
38. as the semiconductor integrated circuit of claim 37, wherein said bipolar junction transistor (BJT) comprising:
Collector electrode, it is formed up to a specific thicknesses in described substrate;
Emitter, it forms in described substrate with described collector electrode and separates; And
Base stage, it is formed between described collector electrode and the described base stage.
39. as the semiconductor integrated circuit of claim 38, wherein said collector electrode is formed up to concentration and identical concentration and the thickness of thickness with described deep trap.
40. as the semiconductor integrated circuit of claim 38, wherein said collector electrode is formed up to the thickness less than described deep trap, described deep trap forms described end face from described substrate around the adjacent devices in the described device of described analogue device.
41. as the semiconductor integrated circuit of claim 37, wherein said heterojunction bipolar transistor (HBT) comprising:
Collector electrode, it is formed up to the specific thicknesses in the described substrate;
Base stage, it is formed on the described end face of described substrate; And
Emitter, it is formed on the described base stage.
42. as the semiconductor integrated circuit of claim 41, wherein said collector electrode is formed up to concentration and identical concentration and the thickness of thickness with described deep trap.
43. as the semiconductor integrated circuit of claim 42, wherein said collector electrode forms via the stack injection technology.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020060037865 | 2006-04-26 | ||
| KR20060037865 | 2006-04-26 | ||
| KR1020070026209 | 2007-03-16 |
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| Publication Number | Publication Date |
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| CN101064307A true CN101064307A (en) | 2007-10-31 |
| CN100536138C CN100536138C (en) | 2009-09-02 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101017033A Active CN100536138C (en) | 2006-04-26 | 2007-04-24 | Semiconductor integrated circuit |
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| Country | Link |
|---|---|
| KR (1) | KR100854440B1 (en) |
| CN (1) | CN100536138C (en) |
| TW (1) | TWI345301B (en) |
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| CN101916730A (en) * | 2010-07-22 | 2010-12-15 | 中国科学院上海微系统与信息技术研究所 | Method for manufacturing silicon on insulator (SOI) super-junction laterally diffused metal oxide semiconductor (LDMOS) with linear buffer layer |
| CN103515378A (en) * | 2012-06-26 | 2014-01-15 | 英飞凌科技股份有限公司 | Semiconductor device and structure |
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| CN104241279A (en) * | 2013-06-18 | 2014-12-24 | 中芯国际集成电路制造(上海)有限公司 | Integrated circuit and manufacturing method thereof |
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| JP3631464B2 (en) * | 2001-12-27 | 2005-03-23 | 株式会社東芝 | Semiconductor device |
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| KR20060010885A (en) * | 2004-07-29 | 2006-02-03 | 매그나칩 반도체 유한회사 | Image sensor capable of interrupting inter block noise inflow |
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- 2007-03-16 KR KR1020070026209A patent/KR100854440B1/en active IP Right Grant
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Also Published As
| Publication number | Publication date |
|---|---|
| TW200746393A (en) | 2007-12-16 |
| CN100536138C (en) | 2009-09-02 |
| KR20070105843A (en) | 2007-10-31 |
| TWI345301B (en) | 2011-07-11 |
| KR100854440B1 (en) | 2008-08-26 |
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